DATASHEET

X9420
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Low Noise/Low Power/SPI Bus
April 26, 2006
FN8195.1
DESCRIPTION
Single Digitally Controlled (XDCP™)
Potentiometer
The X9420 integrates a single digitally controlled
potentiometers (XDCP) on a monolithic CMOS
integrated microcircuit.
FEATURES
• Solid-State Potentiometer
• SPI Serial Interface
• Register Oriented Format
—Direct read/write/transfer wiper positions
—Store as many as four positions per
potentiometer
• Power Supplies
—VCC = 2.7V to 5.5V
—V+ = 2.7V to 5.5V
—V– = -2.7V to -5.5V
• Low Power CMOS
—Standby current < 1µA
• High Reliability
—Endurance–100,000 data changes per bit per
register
—Register data retention–100 years
• 8-bytes of Nonvolatile EEPROM Memory
• 10kΩ or 2.5kΩ Resistor Arrays
• Resolution: 64 Taps Each Pot
• 14 Ld TSSOP and 16 Ld SOIC Packages
• Pb-Free Plus Anneal Available (RoHS Compliant)
The digitally controlled potentiometer is implemented
using 63 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the SPI bus
interface. The potentiometer has associated with it a
volatile Wiper Counter Register (WCR) and 4
nonvolatile Data Registers (DR0:DR3) that can be
directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the
resistor array through the switches. Power-up recalls
the contents of DR0 to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
BLOCK DIAGRAM
HOLD
CS
SCK
S0
Interface
and
Control
Circuitry
SI
A0
R0 R1
8
Data
R2 R3
Wiper
Counter
Register
(WCR)
VH/RH
VL/RL
VW/RW
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9420
Ordering Information
PART NUMBER
PART
MARKING
X9420WS16*
X9420WS
X9420WS16Z* (Note)
POTENTIOMETER
ORGANIZATION TEMP. RANGE
(k)
(°C)
VCC LIMITS (V)
5 ±10%
10
PACKAGE
PKG.
DWG. #
0 to +70
16 Ld SOIC (300 mil)
M16.3
X9420WS Z
0 to +70
16 Ld SOIC (300 mil) (Pb-free)
M16.3
X9420WS16I*
X9420WS I
-40 to +85
16 Ld SOIC (300 mil)
M16.3
X9420WS16IZ* (Note)
X9420WS ZI
-40 to +85
16 Ld SOIC (300 mil) (Pb-free)
M16.3
X9420WV14*
X9420 W
0 to +70
14 Ld TSSOP (4.4mm)
M14.173
X9420WV14Z* (Note)
X9420 WZ
0 to +70
14 Ld TSSOP (4.4mm) (Pb-free) M14.173
X9420WV14I*
X9420 WI
-40 to +85
14 Ld TSSOP (4.4mm)
X9420WV14IZ* (Note)
X9420 WZI
-40 to +85
14 Ld TSSOP (4.4mm) (Pb-free) M14.173
X9420YS16*
X9420YS
X9420YS16Z* (Note)
2.5
M14.173
0 to +70
16 Ld SOIC (300 mil)
M16.3
X9420YS Z
0 to +70
16 Ld SOIC (300 mil) (Pb-free)
M16.3
X9420YS16I*
X9420YS I
-40 to +85
16 Ld SOIC (300 mil)
M16.3
X9420YS16IZ* (Note)
X9420YS ZI
-40 to +85
16 Ld SOIC (300 mil) (Pb-free)
M16.3
X9420YV14*
X9420 Y
0 to +70
14 Ld TSSOP (4.4mm)
M14.173
X9420YV14Z* (Note)
X9420 YZ
0 to +70
14 Ld TSSOP (4.4mm) (Pb-free) M14.173
X9420YV14I*
X9420 YI
-40 to +85
14 Ld TSSOP (4.4mm)
X9420YV14IZ* (Note)
X9420 YZI
-40 to +85
14 Ld TSSOP (4.4mm) (Pb-free) M14.173
X9420WS16-2.7*
X9420WS F
2.7 to 5.5
10
X9420WS16Z-2.7* (Note) X9420WS ZF
M14.173
0 to +70
16 Ld SOIC (300 mil)
M16.3
0 to +70
16 Ld SOIC (300 mil) (Pb-free)
M16.3
X9420WS16I-2.7*
X9420WS G
-40 to +85
16 Ld SOIC (300 mil)
M16.3
X9420WS16IZ-2.7*
(Note)
X9420WS ZG
-40 to +85
16 Ld SOIC (300 mil) (Pb-free)
M16.3
X9420WV14-2.7*
X9420 WF
0 to +70
14 Ld TSSOP (4.4mm)
M14.173
0 to +70
14 Ld TSSOP (4.4mm) (Pb-free) M14.173
X9420WV14Z-2.7* (Note) X9420 WZF
X9420WV14I-2.7*
X9420 WG
-40 to +85
14 Ld TSSOP (4.4mm)
X9420WV14IZ-2.7*
(Note)
X9420 WZG
-40 to +85
14 Ld TSSOP (4.4mm) (Pb-free) M14.173
X9420YS16-2.7*
X9420YS F
X9420YS16Z-2.7* (Note) X9420YS ZF
X9420YS16I-2.7*
X9420YS G
X9420YS16IZ-2.7* (Note) X9420YS ZG
X9420YV14-2.7*
X9420 YF
X9420YV14Z-2.7* (Note) X9420 YZF
X9420YV14I-2.7*
X9420 YG
X9420YV14IZ-2.7* (Note) X9420 YZG
2.7 to 5.5
2.5
M14.173
0 to +70
16 Ld SOIC (300 mil)
M16.3
0 to +70
16 Ld SOIC (300 mil) (Pb-free)
M16.3
-40 to +85
16 Ld SOIC (300 mil)
M16.3
-40 to +85
16 Ld SOIC (300 mil) (Pb-free)
M16.3
0 to +70
14 Ld TSSOP (4.4mm)
M14.173
0 to +70
14 Ld TSSOP (4.4mm) (Pb-free) M14.173
-40 to +85
14 Ld TSSOP (4.4mm)
M14.173
-40 to +85
14 Ld TSSOP (4.4mm) (Pb-free) M14.173
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2
FN8195.1
April 26, 2006
X9420
PIN DESCRIPTIONS
Potentiometer Pins
Host Interface Pins
VH/RH, VL/RL
Serial Output (SO)
The VH/RH and VL/RL input are equivalent to the
terminal connections on either end of a mechanical
potentiometer.
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked
out by the falling edge of the serial clock.
VW/RW
The wiper output is equivalent to the wiper output of a
mechanical potentiometer.
Serial Input
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the potentiometer
and pot register are input on this pin. Data is latched
by the rising edge of the serial clock.
Serial Clock (SCK)
The SCK input is used to clock data into and out of the
X9420.
Chip Select (CS)
When CS is HIGH, the X9420 is deselected and the
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device will be in the
standby state. CS LOW enables the X9420, placing it
in the active power mode. It should be noted that after
a power-up, a HIGH to LOW transition on CS is
required prior to the start of any operation.
Hold (HOLD)
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD must
be brought LOW while SCK is LOW. To resume
communication, HOLD is brought HIGH, again while
SCK is LOW. If the pause feature is not used, HOLD
should be held HIGH at all times.
Hardware Write Protect Input (WP)
The WP pin when LOW prevents nonvolatile writes to
the Data Registers. Writing to the Wiper Counter
Register is not restricted.
Analog Supplies (V+, V-)
The analog supplies V+, V- are the supply voltages for
the XDCP analog section.
System/Digital Supply (VCC)
VCC is the supply voltage for the system/digital
section. VSS is the system ground.
PIN CONFIGURATION
DIP/SOIC
VCC
1
16
V+
CS
2
15
NC
RL/VL
3
14
A0
RH/VH
4
13
SO
RW/VW
5
12
HOLD
SI
6
11
SCK
WP
7
10
NC
VSS
8
9
X9420
V-
TSSOP
Device Address (A0)
The address inputs is used to set the least significant
bit of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
address input in order to initiate communication with
the X9420. A maximum of 2 devices may occupy the
SPI serial bus.
3
CS
1
14
VCC
RL/VL
2
13
V+
RH/VH
3
12
A0
RW/VW
4
X9420 11
SO
SI
5
10
WP
6
9
SCK
VSS
7
8
V-
HOLD
FN8195.1
April 26, 2006
X9420
Wiper Counter Register (WCR)
PIN NAMES
Symbol
Description
SCK
Serial Clock
SI, SO
Serial Data
A0
Device Address
VH/RH,
VL/RL
Potentiometer Pins (terminal equivalent)
VW/RW
Potentiometer Pins (wiper equivalent)
WP
Hardware Write Protection
HOLD
Serial Communication Pause
V+,V-
Analog Supplies
VCC
System Supply Voltage
VSS
System Ground
NC
No Connection
PRINCIPLES OF OPERATION
The X9420 is a highly integrated microcircuit
incorporating a resistor array and associated registers
and counter and the serial interface logic providing
direct communication between the host and the XDCP
potentiometer.
Serial Interface
The X9420 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked in on the rising SCK. CS must be
LOW and the HOLD and WP pins must be HIGH
during the entire operation.
The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.
The X9420 contains a Wiper Counter Register. The
WCR can be envisioned as a 6-bit parallel and serial
load counter with its outputs decoded to select one of
sixty-four switches along its resistor array. The
contents of the WCR can be altered in four ways: it
may be written directly by the host via the Write Wiper
Counter Register instruction (serial load); it may be
written indirectly by transferring the contents of one of
four associated data registers via the XFR Data
Register instruction (parallel load); it can be modified
one step at a time by the Increment/ Decrement
instruction. Finally, it is loaded with the contents of its
data register zero (DR0) upon power-up.
The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9420 is powereddown. Although the register is automatically loaded
with the value in DR0 upon power-up, this may be
different from the value present at power-down.
Data Registers
The potentiometer has four 6-bit nonvolatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the WCR. It should be noted all
operations changing data in one of the Data Registers is
a nonvolatile operation and will take a maximum of 10ms.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user preference data.
Register Descriptions
Table 1. Data Registers, (6-bit), Nonvolatile
0
Array Description
The X9420 is comprised of one resistor array
containing 63 discrete resistive segments that are
connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
potentiometer (VH/RH and VL/RL inputs).
At both ends of the array and between each resistor
segment is a CMOS switch connected to the wiper
(VW/RW) output. Within the individual array only one
switch may be turned on at a time.
These switches are controlled by a Wiper Counter
Register (WCR). The six bits of the WCR are decoded to
select, and enable, one of sixty-four switches. The block
diagram of the potentiometer is shown in Figure 1.
4
0
(MSB)
D5
D4
D3
D2
D1
D0
(LSB)
There are four 6-bit Data Registers associated with the
potentiometer.
– {D5~D0}: These bits are for general purpose Nonvolatile data storage or for storage of up to four different wiper values.
Table 2. Wiper Counter Register, (6-bit), Volatile
0
(MSB)
0
WP5 WP4 WP3 WP2 WP1 WP0
(LSB)
– {WP5~WP0}: These bits specify the wiper position
of the potentiometer.
FN8195.1
April 26, 2006
X9420
Figure 1. Detailed Potentiometer Block Diagram
Serial Data Path
VH
Serial
Bus
Input
From Interface
Circuitry
Register 0
8
REGISTER 2
C
O
U
N
T
E
R
Register 1
6
Parallel
Bus
Input
Wiper
Counter
Register
(WCR)
REGISTER 3
IF WCR = 00[H] THEN VW = VL
IF WCR = 3F[H] THEN VW = VH
UP/DN
Modified SCK
D
E
C
O
D
E
INC/DEC
Logic
UP/DN
VL
CLK
VW
Figure 2. Address/Identification Byte Format
Write in Process
The contents of the Data Registers are saved to
nonvolatile memory when the CS pin goes from LOW to
HIGH after a complete write sequence is received by
the device. The progress of this internal write operation
can be monitored by a Write In Process bit (WIP). The
WIP bit is read with a Read Status command.
Device Type
Identifier
0
1
0
1
1
1
0
A0
Device Address
INSTRUCTIONS
Address/Identification (ID) Byte
Instruction Byte
The first byte sent to the X9420 from the host,
following a CS going HIGH to LOW, is called the
Address or Identification byte. The most significant
four bits of the slave address are a device type
identifier, for the X9420 this is fixed as 0101[B] (refer
to Figure 2).
The next byte sent to the X9420 contains the
instruction and register pointer information. The four
most significant bits are the instruction. The next two
bits point to one of four data registers. The format is
shown below in Figure 3.
The least significant bit in the ID byte selects one of
two devices on the bus. The physical device address
is defined by the state of the A0 input pin. The X9420
compares the serial data stream with the address
input state; a successful compare of the address bit is
required for the X9420 to successfully continue the
command sequence. The A0 input can be actively
driven by a CMOS input signal or tied to VCC or VSS.
Figure 3. Instruction Byte Format
Register
Select
I3
I2
I1
I0
R1
R0
0
0
Instructions
The remaining three bits in the ID byte must be set to 110.
5
FN8195.1
April 26, 2006
X9420
The four high order bits of the instruction byte specify
the operation. The next two bits (R1 and R0) select
one of the four registers that is to be acted upon when
a register oriented instruction is issued. The last two
bits are defined as 0.
Five instructions require a three-byte sequence to
complete. These instructions transfer data between
the host and the X9420; either between the host and
one of the Data Registers or directly between the host
and the WCR. These instructions are:
Two of the eight instructions are two bytes in length
and end with the transmission of the instruction byte.
These instructions are:
– Read Wiper Counter Register—read the current
wiper position of the pot,
– Write Wiper Counter Register—change current
wiper position of the pot,
– XFR Data Register to Wiper Counter Register —
This instruction transfers the contents of one specified Data Register to the Wiper Counter Register.
– Read Data Register—read the contents of the
selected data register;
– XFR Wiper Counter Register to Data Register—This
instruction transfers the contents of the Wiper
Counter Register to the specified associated Data
Register.
– Write Data Register—write a new value to the
selected data register.
– Read Status—This command returns the contents
of the WIP bit which indicates if the internal write
cycle is in progress.
The basic sequence of the two byte instructions is
illustrated in Figure 4. These two-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the wiper
to this action will be delayed by tWRL. A transfer from
the WCR (current wiper position), to a Data Register is
a write to nonvolatile memory and takes a minimum of
tWR to complete. The transfer can occur between the
potentiometer and one of its associated registers.
The sequence of these operations is shown in Figure
5 and Figure 6.
The final command is Increment/Decrement. It is
different from the other commands, because it’s length
is indeterminate. Once the command is issued, the
master can clock the wiper up and/or down in one
resistor segment steps; thereby, providing a fine
tuning capability to the host. For each SCK clock pulse
(tHIGH) while SI is HIGH, the selected wiper will move
one resistor segment towards the VH/RH terminal.
Similarly, for each SCK clock pulse while SI is LOW,
the selected wiper will move one resistor segment
towards the VL/RL terminal. A detailed illustration of
the sequence and timing for this operation are shown
in Figure 7 and Figure 8.
Figure 4. Two-Byte Instruction Sequence
CS
SCK
SI
0
6
1
0
1
1
1
0
A0
I3
I2
I1
I0
R1 R0
0
0
FN8195.1
April 26, 2006
X9420
Figure 5. Three-Byte Instruction Sequence (Write)
CS
SCL
SI
0
1
0
1
1
1
0
A0
I3
I2
I1 I0
R1 R0
0
0
0
0
D5 D4 D3 D2 D1 D0
Figure 6. Three-Byte Instruction Sequence (Read)
CS
SCL
SI
Don’t Care
0
1
0
1
1
1
0
A0
I3
I2
I1 I0
R1 R0 0
0
S0
0
0
D5 D4 D3 D2 D1 D0
Figure 7. Increment/Decrement Instruction Sequence
CS
SCK
SI
0
1
0
1
1
1
0
A0
I3
I2
I1
I0
0
0
0
0
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
Figure 8. Increment/Decrement Timing Limits
tWRID
SCK
SI
Voltage Out
VW
INC/DEC CMD Issued
7
FN8195.1
April 26, 2006
X9420
Table 3. Instruction Set
I3
1
I2
0
Instruction Set
I1 I0 R1 R0
0
1
0
0
1
0
1
0
0
0
0
0
Write new value to the Wiper Counter Register
1
0
1
1
R1
R0
0
0
Write Data Register
1
1
0
0
R1
R0
0
0
XFR Data Register to
Wiper Counter
Register
XFR Wiper Counter
Register to Data
Register
Increment/Decrement
Wiper Counter
Register
Read Status (WIP bit)
1
1
0
1
R1
R0
0
0
Read the contents of the Data Register pointed to by
R1 - R0
Write new value to the Data Register pointed to by
R1 - R0
Transfer the contents of the Data Register pointed to
by R1 - R0 to the Wiper Counter Register
1
1
1
0
R1
R0
0
0
Transfer the contents of the Wiper Counter
Register to the Data Register pointed to by R1 - R0
0
0
1
0
0
0
0
0
Enable Increment/decrement of the Wiper Counter
Register
0
1
0
1
0
0
0
1
Read the status of the internal write cycle, by checking the WIP bit.
Instruction
Read Wiper Counter
Register
Write Wiper Counter
Register
Read Data Register
8
Operation
0
0
Read the contents of the Wiper Counter Register
FN8195.1
April 26, 2006
X9420
Instruction Format
Notes: (1) “A1 ~ A0”: stands for the device addresses sent by the master.
(2) WPx refers to wiper position data in the Wiper Counter Register
“I”: stands for the increment operation, SI held HIGH during active SCK phase (high).
(3) “D”: stands for the decrement operation, SI held LOW during active SCK phase (high).
Read Wiper Counter Register (WCR)
device type
device
instruction
wiper position
identifier
addresses
opcode
(sent by X9420 on SO)
CS
CS
Falling
Rising
W W W W W W
Edge 0 1 0 1 1 1 0 A 1 0 0 1 0 0 0 0 0 0 P P P P P P Edge
0
5 4 3 2 1 0
Write Wiper Counter Register (WCR)
device type
identifier
device
addresses
instruction
opcode
Data Byte
(sent by Host on SI)
CS
CS
Falling
W W W W W W Rising
Edge 0 1 0 1 1 1 0 A 1 0 1 0 0 0 0 0 0 0 P P P P P P Edge
0
5 4 3 2 1 0
Read Data Register (DR)
Read the contents of the Register pointed to by R1 - R0.
device type
device
instruction
register
Data Byte
identifier
addresses
opcode
addresses
(sent by X9420 on SO)
CS
CS
Falling
Rising
W W W W W W
Edge 0 1 0 1 1 1 0 A 1 0 1 1 R R 0 0 0 0 P P P P P P Edge
0
1 0
5 4 3 2 1 0
Write Data Register (DR)
Write a new value to the Register pointed to by R1 - R0.
device type
device
identifier
addresses
instruction
opcode
register
addresses
Data Byte
(sent by host on SI)
CS
CS
Falling
W W W W W W Rising
Edge 0 1 0 1 1 1 0 A 1 1 0 0 R R 0 0 0 0 P P P P P P Edge
0
1 0
5 4 3 2 1 0
HIGH-VOLTAGE
WRITE CYCLE
Transfer Data Register (DR) to Wiper Counter Register (WCR)
Transfer the contents of the Register pointed to by R1 - R0 to the WCR.
device type
device
instruction
register
CS
CS
identifier
addresses
opcode
addresses
Falling
Rising
Edge 0 1 0 1 1 1 0 A 1 1 0 1 R R 0 0 Edge
0
1 0
9
FN8195.1
April 26, 2006
X9420
Transfer Wiper Counter Register (WCR) to Data Register (DR)
device type
device
instruction
register
CS
CS
identifier
addresses
opcode
addresses
Falling
Rising
Edge 0 1 0 1 1 1 0 A 1 1 1 0 R R 0 0 Edge
0
1 0
HIGH-VOLTAGE
WRITE CYCLE
Increment/Decrement Wiper Counter Register (WCR)
device type
device
instruction
increment/decrement
CS
CS
identifier
addresses
opcode
(sent by master on SDA)
Falling
Rising
Edge 0 1 0 1 1 1 0 A 0 0 1 0 0 0 0 0 I/D I/D . . . . I/D I/D Edge
0
Read Status
device type
device
instruction
Data Byte
identifier
addresses
opcode
(sent by X9420 on SO)
CS
CS
Falling
Rising
W
Edge 0 1 0 1 1 1 0 A 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 I Edge
0
P
10
FN8195.1
April 26, 2006
X9420
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias .....................-65 C to +135 C
Storage temperature ..........................-65 C to +150 C
Voltage on SCK, SCL or any
address input with respect to VSS ........... -1V to +7V
Voltage on V+ (referenced to VSS)........................ 10V
Voltage on V- (referenced to VSS)........................-10V
(V+) - (V-) .............................................................. 12V
Any VH/RH, VL/RL, VW/RW ........................... V- to V+
Lead temperature (soldering, 10s) .....................300 C
IW (10s) ..............................................................±6mA
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification)
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
RECOMMENDED OPERATING CONDITIONS
Temp
Commercial
Industrial
Min.
0°C
-40°C
Max.
Device
X9420
X9420-2.7
+70°C
+85°C
Supply Voltage (VCC) Limits
5V ± 10%
2.7V to 5.5V
ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Symbol
RTOTAL
IW
RW
Parameter
Min.
End to End Resistance
Power Rating
Wiper Current
Wiper Resistance
Limits
Typ.
Max.
±20
50
±3
150
250
40
Vv+
Voltage on V+ Pin
X9420
X9420-2.7
VvVoltage on V- Pin
X9420
X9420-2.7
VTERM
Voltage on any VH/RH, VL/RL, VW/RW
Noise
Resolution(4)
Absolute Linearity(1)
Relative Linearity(2)
Temperature Coefficient of RTOTAL
Ratiometric Temperature Coefficient
CH/CL/CW Potentiometer Capacitances
Rh, RI, Rw leakage current
IAL
+4.5
+2.7
-5.5
-5.5
V-
100
Ω
+5.5
+5.5
-4.5
-2.7
V+
V
-140
1.6
±1
±0.2
±300
±20
10/10/25
0.1
Units
%
mW
mA
Ω
10
Test Conditions
25 C, each pot
Wiper Current = ± 1mA,
V+/V- = ±3V
Wiper Current = ± 1mA,
V+/V- = ±5V
V
V
dBV
%
MI(3)
MI(3)
ppm/ C
ppm/ C
pF
µA
Ref: 1kHz
See Note 5
Vw(n)(actual) - Vw(n)(expected)
Vw(n + 1) - [Vw(n) + MI]
See Note 5
See Note 5
See Circuit #3
Vin = V- to V+. Device is in
stand-by mode.
Notes: (1) Absolute Linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as
a potentiometer.
(2) Relative Linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size.
(3) MI = RTOT/63 or (VH - VL)/63, single pot.
(4) Typical = Individual array resolution.
11
FN8195.1
April 26, 2006
X9420
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
ICC1
VCC Supply Current (Active)
ICC2
Typ.
Max.
Units
Test Conditions
400
µA
fSCK = 2MHz, SO = Open,
Other Inputs = VSS
VCC Supply Current
(Non-volatile Write)
1
mA
fSCK = 2MHz, SO = Open,
Other Inputs = VSS
ISB
VCC Current (Standby)
1
μA
SCK = SI = VSS, Addr. = VSS
ILI
Input Leakage Current
10
μA
VIN = VSS to VCC
ILO
Output Leakage Current
10
μA
VOUT = VSS to VCC
VIH
Input HIGH Voltage
VCC x 0.7
VCC + 0.5
V
VIL
Input LOW Voltage
-0.5
VCC x 0.1
V
VOL
Output LOW Voltage
0.4
V
IOL = 3mA
ENDURANCE AND DATA RETENTION
Parameter
Min.
Units
Minimum Endurance
100,000
Data Changes per Bit per Register
Data Retention
100
Years
CAPACITANCE
Symbol
COUT
CIN
Test
Max.
Units
Test Conditions
Output Capacitance (SO)
8
pF
VOUT = 0V
Input Capacitance (A0, SI, and SCK)
6
pF
VIN = 0V
(5)
(5)
POWER-UP TIMING
Symbol
tPUR
Parameter
Max.
Max.
Units
(6)
Power-up to Initiation of Read Operation
1
1
ms
(6)
Power-up to Initiation of Write Operation
5
5
ms
VCC Power-up Ramp
0.2
50
V/msec
tPUW
tRVCC
POWER-UP REQUIREMENTS (Power-up sequencing can affect correct recall of the wiper registers)
The preferred power-on sequence is as follows: First VCC, then V+ and V-, and then the potentiometer pins, RH, RL,
and RW. Voltage should not be applied to the potentiometer pins before V+ or V- is applied. The VCC ramp rate
specification should be met, and any glitches or slope changes in the VCC line should be held to <100mV if possible.
If VCC powers down, it should be held below 0.1V for more than 1 second before powering up again in order for
proper wiper register recall. Also, VCC should not reverse polarity by more than 0.5V. Recall of wiper position will not
be complete until VCC, V+ and V- reach their final value.
Notes: (5) This parameter is periodically sampled and not 100% tested.
(6) tPUR and tPUW are the delays required from the time the third (last) power supply (VCC, V+ or V-) is stable until the specific instruction
can be issued. These parameters are periodically sampled and not 100% tested.
12
FN8195.1
April 26, 2006
X9420
A.C. TEST CONDITIONS
EQUIVALENT A.C. LOAD CIRCUIT
Input pulse levels
VCC x 0.1 to VCC x 0.9
Input rise and fall times
10ns
Input and output timing level
VCC x 0.5
5V
1533Ω
SDA Output
100pF
AC TIMING
Symbol
Parameter
Min.
Max.
Units
2.0
MHz
fSCK
SSI/SPI Clock Frequency
tCYC
SSI/SPI Clock Cycle Time
500
ns
tWH
SSI/SPI Clock High Time
200
ns
tWL
SSI/SPI Clock Low Time
200
ns
tLEAD
Lead Time
250
ns
tLAG
Lag Time
250
ns
tSU
SI, SCK, HOLD and CS Input Setup Time
50
ns
tH
SI, SCK, HOLD and CS Input Hold Time
50
ns
tRI
SI, SCK, HOLD and CS Input Rise Time
2
µs
tFI
SI, SCK, HOLD and CS Input Fall Time
2
µs
500
ns
100
ns
tDIS
SO Output Disable Time
0
tV
SO Output Valid Time
tHO
SO Output Hold Time
tRO
SO Output Rise Time
50
ns
tFO
SO Output Fall Time
50
ns
0
ns
tHOLD
HOLD Time
400
ns
tHSU
HOLD Setup Time
100
ns
tHH
HOLD Hold Time
100
ns
tHZ
HOLD Low to Output in High Z
100
ns
tLZ
HOLD High to Output in Low Z
100
ns
TI
Noise Suppression Time Constant at SI, SCK, HOLD and CS inputs
20
ns
tCS
CS Deselect Time
2
µs
tWPASU
WP, A0 and A1 Setup Time
0
ns
tWPAH
WP, A0 and A1 Hold Time
0
ns
13
FN8195.1
April 26, 2006
X9420
HIGH-VOLTAGE WRITE CYCLE TIMING
Symbol
Parameter
Typ.
Max.
Units
tWR
High-voltage Write Cycle Time (Store Instructions)
5
10
ms
XDCP TIMING
Symbol
Parameter
Min.
Max. Units
tWRPO
Wiper Response Time After The Third (Last) Power Supply Is Stable
10
µs
tWRL
Wiper Response Time After Instruction Issued (All Load Instructions)
10
µs
tWRID
Wiper Response Time From An Active SCL/SCK Edge (Increment/Decrement
Instruction)
450
ns
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
14
FN8195.1
April 26, 2006
X9420
TIMING DIAGRAMS
Input Timing
tCS
CS
tCYC
tLEAD
SCK
tSU
tH
...
tWL
tRI
tFI
tWH
...
MSB
SI
tLAG
LSB
High Impedance
SO
Output Timing
CS
SCK
tV
...
tDIS
...
MSB
SO
SI
tHO
LSB
ADDR
Hold Timing
CS
tHSU
SCK
tHH
...
tRO
tFO
SO
tHZ
tLZ
SI
tHOLD
HOLD
15
FN8195.1
April 26, 2006
X9420
XDCP Timing (for All Load Instructions)
CS
SCK
SI
...
tWRL
...
MSB
LSB
VW
SO
High Impedance
XDCP Timing (for Increment/Decrement Instruction)
CS
SCK
...
tWRID
...
VW
SI
SO
ADDR
Inc/Dec
Inc/Dec
...
High Impedance
Write Protect and Device Address Pins Timing
(Any Instruction)
CS
tWPASU
WP
tWPAH
A0
A1
16
FN8195.1
April 26, 2006
X9420
APPLICATIONS INFORMATION
Electronic potentiometers provide three powerful application advantages: (1) the variability and reliability of a solidstate potentiometer, (2) the flexibility of computer-based digital controls, and (3) the retentivity of nonvolatile memory
used for the storage of multiple potentiometer settings or data.
Basic Configurations of Electronic Potentiometers
VR
VR
VH
VW
VL
I
Three terminal Potentiometer;
Variable voltage divider
Two terminal Variable Resistor;
Variable current
Basic Circuits
Buffered Reference Voltage
Cascading Techniques
R1
+V
+V
+5V
+V
VS
+5V
VW
VW
VOUT = VW
–
LM308A
+
X
OP-07
+
Noninverting Amplifier
VO
–
-5V
VW
R2
+V
-5V
R1
VW
(a)
Offset Voltage Adjustment
Voltage Regulator
VIN
VO = (1+R2/R1)VS
(b)
VO (REG)
317
R1
R2
–
+
100kΩ
–
10kΩ
+12V
10kΩ
}
10kΩ
}
TL072
R2
VO
VO
+
Iadj
17
VS
VS
R1
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
Comparator with Hysterisis
R1
R2
VUL = {R1/CR1+R2} VO(max)
VLL = {R1/CR1+R2} VO(min)
-12V
FN8195.1
April 26, 2006
X9420
Thin Shrink Small Outline Plastic Packages (TSSOP)
M14.173
N
INDEX
AREA
E
0.25(0.010) M
E1
2
SYMBOL
3
0.05(0.002)
-A-
INCHES
GAUGE
PLANE
-B1
14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
B M
L
A
D
-C-
α
e
A1
b
0.10(0.004) M
0.25
0.010
SEATING PLANE
A2
c
0.10(0.004)
C A M
B S
MIN
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
MILLIMETERS
MIN
MAX
NOTES
A
-
0.047
-
1.20
-
A1
0.002
0.006
0.05
0.15
-
A2
0.031
0.041
0.80
1.05
-
b
0.0075
0.0118
0.19
0.30
9
c
0.0035
0.0079
0.09
0.20
-
D
0.195
0.199
4.95
5.05
3
E1
0.169
0.177
4.30
4.50
4
e
0.026 BSC
0.65 BSC
-
E
0.246
0.256
6.25
6.50
-
L
0.0177
0.0295
0.45
0.75
6
8o
0o
N
NOTES:
MAX
α
14
0o
14
7
8o
Rev. 2 4/06
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
18
FN8195.1
April 26, 2006
X9420
Small Outline Plastic Packages (SOIC)
M16.3 (JEDEC MS-013-AA ISSUE C)
N
16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
H
0.25(0.010) M
B M
INCHES
E
-B1
2
3
L
SEATING PLANE
-A-
A
D
h x 45°
-C-
e
A1
B
C
0.10(0.004)
0.25(0.010) M
C A M
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.0926
0.1043
2.35
2.65
-
A1
0.0040
0.0118
0.10
0.30
-
B
0.013
0.0200
0.33
0.51
9
C
0.0091
0.0125
0.23
0.32
-
D
0.3977
0.4133
10.10
10.50
3
E
0.2914
0.2992
7.40
7.60
4
e
α
B S
0.050 BSC
1.27 BSC
-
H
0.394
0.419
10.00
10.65
-
h
0.010
0.029
0.25
0.75
5
L
0.016
0.050
0.40
1.27
6
N
α
NOTES:
MILLIMETERS
16
0°
16
8°
0°
7
8°
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 1 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm (0.024
inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
19
FN8195.1
April 26, 2006
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