DATASHEET

DATASHEET
Single Supply/Low Power/256-Tap/2-Wire Bus Quad
Digitally-Controlled (XDCP™) Potentiometers
X9259
Features
The X9259 integrates four digitally controlled potentiometers
(XDCP) on a monolithic CMOS integrated circuit.
• Four separate potentiometers in one package
The digitally controlled potentiometers are implemented with
a combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the
2-wire bus interface. Each potentiometer has associated with
it a volatile Wiper Counter Register (WCR) and four nonvolatile
Data Registers that can be directly written to and read by the
user. The content of the WCR controls the position of the wiper.
At power-up, the device recalls the content of the default Data
Registers of each DCP (DR00, DR10, DR20, and DR30) to the
corresponding WCR.
• 2-wire serial interface for write, read, and
transfer operations of the potentiometer
• 256 resistor taps–0.4% resolution
• Wiper resistance: 100Ω typical at VCC = 5V
• 4 nonvolatile data registers for each potentiometer
• Nonvolatile storage of multiple wiper positions
• Standby current <5µA max
• VCC: 2.7V to 5.5V operation
• 50kΩ version of total resistance
The XDCP can be used as a three-terminal potentiometer or as
a two-terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.
• Endurance: 100,000 data changes per bit per register
• 100 year data retention
• Single supply version of X9258
• 24 Ld SOIC, 24 Ld TSSOP
• Low power CMOS
• Pb-Free (RoHS compliant)
Functional Diagram
A3
A2
2-WIRE
INTERFACE
A1
A0
RH1
RH0
VCC
WCR0
DR00
DR01
DR02
DR03
POWER UP,
INTERFACE
CONTROL
AND
STATUS
DCP0
WCR1
DR10
DR11
DR12
DR13
DCP1
RH3
RH2
WCR2
DR20
DR21
DR22
DR23
DCP2
WCR3
DR30
DR31
DR32
DR33
DCP3
SDA
SCL
VSS
December 12, 2014
FN8169.6
WP
1
RW0
RL0
RW1
RL1
RW2
RL2
RW3
RL3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2005-2007, 2014. All Rights Reserved
Intersil (and design) and XDCP are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
X9259
Ordering Information
PART NUMBER
(Notes 1, 3)
PART
MARKING
VCC LIMITS
(V)
RTOTAL
(kΩ)
TEMP RANGE
(°C)
5 ±10%
50
0 to +70
24 Ld SOIC
M24.3
24 Ld TSSOP
M24.173
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
X9259US24Z (Note 2)
X9259US Z
X9259UV24Z
X9259UV Z
0 to +70
X9259US24IZ (Note 2)
X9259US ZI
-40 to +85
24 Ld SOIC
M24.3
X9259UV24IZ (Note 2)
X9259UV ZI
-40 to +85
24 Ld TSSOP
M24.173
X9259US24Z-2.7 (Note 2)
X9259US ZF
0 to +70
24 Ld SOIC
M24.3
X9259US24IZ-2.7 (Note 2)
X9259US ZG
-40 to +85
24 Ld SOIC
M24.3
X9259UV24Z-2.7
X9259UV ZF
0 to +70
24 Ld TSSOP
M24.173
X9259UV24IZ-2.7 (Note 2)
X9259UV ZG
-40 to +85
24 Ld TSSOP
M24.173
2.7 to 5.5
NOTES:
1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. Add "T1" suffix for tape and reel.
3. For Moisture Sensitivity Level (MSL), please see product information page for X9259. For more information on MSL, please see tech brief TB363.
Circuit Level Applications
System Level Applications
• Vary the gain of a voltage amplifier
• Adjust the contrast in LCD displays
• Provide programmable DC reference voltages for comparators
and detectors
• Control the power level of LED transmitters in
communication systems
• Control the volume in audio circuits
• Set and regulate the DC biasing point in an RF power amplifier
in wireless systems
• Trim out the offset voltage error in a voltage amplifier circuit
• Set the output voltage of a voltage regulator
• Trim the resistance in Wheatstone bridge circuits
• Control the gain, characteristic frequency and
Q-factor in filter circuits
• Set the scale factor and zero point in sensor signal
conditioning circuits
• Vary the frequency and duty cycle of timer ICs
• Control the gain in audio and home entertainment systems
• Provide the variable DC bias for tuners in RF wireless systems
• Set the operating points in temperature control
systems
• Control the operating point for sensors in industrial systems
• Trim offset and gain errors in artificial intelligent
systems
• Vary the DC biasing of a pin diode attenuator in RF circuits
• Provide a control variable (I, V, or R) in feedback
circuits
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December 12, 2014
X9259
Pin Configuration
X9259
24 LD SOIC/TSSOP
TOP VIEW
DNC
1
24
A3
A0
2
23
SCL
RW3
3
22
RL2
RH3
4
21
RH2
RL3
5
20
RW2
19
NC
18
VSS
NC
6
VCC
7
RL0
8
17
RW1
X9259
RH0
9
16
RH1
RW0
10
15
RL1
A2
11
14
A1
WP
12
13
SDA
Pin Descriptions
PIN
#
PIN
NAME
2
A0
3
RW3
Wiper Terminal of DCP3
4
RH3
High Terminal of DCP3
5
RL3
Low Terminal of DCP3
7
VCC
System Supply Voltage
8
RL0
Low Terminal of DCP0
9
RH0
High Terminal of DCP0
10
RW0
Wiper Terminal of DCP0
11
A2
Device Address for 2-wire bus. (See Note 4)
12
WP
Hardware Write Protect – Active Low
13
SDA
Serial Data Input/Output for 2-wire bus.
14
A1
Device Address for 2-wire bus. (See Note 4)
15
RL1
Low Terminal of DCP1
16
RH1
High Terminal of DCP1
17
RW1
Wiper Terminal of DCP1
18
VSS
System Ground
20
RW2
Wiper Terminal of DCP2
21
RH2
High Terminal of DCP2
22
RL2
Low Terminal of DCP2
23
SCL
Serial Clock for 2-wire bus.
24
A3
Device Address for 2-wire bus. (See Note 4)
6, 19
NC
No Connect
1
DNC
DESCRIPTION
Device Address for 2-wire bus. (See Note 4)
Do Not Connect
NOTE:
4. A0 through A3 Device address pins must be tied to a logic level.
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December 12, 2014
X9259
Functional Pin Descriptions
Potentiometer Pins
Bus Interface Pins
RH, RL
SERIAL DATA INPUT/OUTPUT (SDA)
The SDA is a bidirectional serial data input/output pin for a
2-wire slave device and is used to transfer data into and out of
the device. It receives device address, opcode, wiper register
address and data sent from a 2-wire master at the rising edge of
the serial clock SCL, and it shifts out data after each falling edge
of the serial clock SCL.
It is an open-drain output and may be wire-ORed with any
number of open drain or open collector outputs. An open-drain
output requires the use of a pull-up resistor.
The RH and RL pins are equivalent to the terminal connections on
a mechanical potentiometer. Since there are 4 potentiometers,
there are 4 sets of RH and RL such that RH0 and RL0 are the
terminals of DCP0 and so on.
RW
The wiper pin are equivalent to the wiper terminal of a
mechanical potentiometer. Since there are 4 potentiometers,
there are 4 sets of RW such that RW0 is the terminal of DCP0 and
so on.
Bias Supply Pins
SERIAL CLOCK (SCL)
SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY
GROUND (VSS)
This input is used by a 2-wire master to supply a 2-wire serial
clock to the X9259.
The VCC pin is the system supply voltage. The VSS pin is the
system ground.
DEVICE ADDRESS (A3 THROUGH A0)
The Address inputs are used to set the least significant 4 bits of
the 8-bit slave address. A match in the slave address serial data
stream must be made with the address input in order to initiate
communication with the X9259. A maximum of 16 devices may
occupy the 2-wire serial bus. Device pins A3 through A0 must be
tied to a logic level, which specifies the external address of the
device, see Figures 3, 4, and 5.
Other Pins
NO CONNECT
No connect pins should be left open. These pins are used for
Intersil manufacturing and testing purposes.
HARDWARE WRITE PROTECT INPUT (WP)
The WP pin when LOW, prevents nonvolatile writes to the Data
Registers.
One of Four Potentiometers
RH
#: 0, 1, 2, or 3
SERIAL
BUS
INPUT
SERIAL DATA PATH
FROM INTERFACE
CIRCUITRY
DR#0
DR#1
8
DR#2
IF WCR = 00[H] then RW is closest to RL
IF WCR = FF[H] then RW is closest to RH
8
PARALLEL
BUS
INPUT
WIPER
COUNTER
REGISTER
(WCR#)
DR#3
COUNTER
--DECODE
DCP
CORE
RW
INC/DEC
LOGIC
UP/DN
MODIFIED SCK
UP/DN
CLK
RL
FIGURE 1. DETAILED POTENTIOMETER BLOCK DIAGRAM
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X9259
Principles of Operation
The X9259 is an integrated circuit incorporating four DCPs and
their associated registers and counters, and the serial interface
providing direct communication between a host and the
potentiometers.
DCP Description
Each DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each DCP are
equivalent to the fixed terminals of a mechanical potentiometer
(RH and RL pins). The RW pin is an intermediate node, equivalent
to the wiper terminal of a mechanical potentiometer.
The position of the wiper terminal within the DCP is controlled by
an 8-bit volatile Wiper Counter Register (WCR).
Power Up and Down Recommendations
There are no restrictions on the power-up or power-down
conditions of VCC and the voltages applied to the potentiometer
pins provided that VCC is always more positive than or equal to
VH, VL, and VW, i.e., VCC  VH, VL, VW. The VCC ramp rate
specification is always in effect.
Wiper Counter Register (WCR)
The X9259 contains four Wiper Counter Registers, one for each
potentiometer. The Wiper Counter Register can be envisioned as
a 8-bit parallel and serial load counter with its outputs decoded
to select one of 256 wiper positions along its resistor array. The
contents of the WCR can be altered in four ways: it may be
written directly by the host via the Write Wiper Counter Register
instruction (serial load); it may be written indirectly by
transferring the contents of one of four associated data registers
via the XFR Data Register instruction (parallel load); it can be
modified one step at a time by the Increment/Decrement
instruction (see “Instructions” section on page 8 for more
details). Finally, it is loaded with the contents of its data register
zero (DR#0) upon power-up, (see Figure 1 on page 4).
The Wiper Counter Register is a volatile register; that is, its
contents are lost when the X9259 is powered-down. Although the
register is automatically loaded with the value in DR#0 upon
power-up, this may be different from the value present at
power-down. Power-up guidelines are recommended to ensure
proper loadings of the DR#0 value into the WCR# (see AN162).
Data Registers (DR)
Each of the four DCPs has four 8-bit nonvolatile Data Registers.
These can be read or written directly by the host. Data can also
be transferred between any of the four data registers and the
associated Wiper Counter Register. All operations changing data
in one of the data registers is a nonvolatile operation and takes a
maximum of 10ms.
If the application does not require storage of multiple settings for
the potentiometer, the Data Registers can be used as regular
memory locations for system parameters or user preference
data.
Bit [7:0] are used to store one of the 256 wiper positions
(0 ~ 255).
TABLE 1. WIPER COUNTER REGISTER, WCR (8-BIT), WCR[7:0]: USED TO STORE THE CURRENT WIPER POSITION (VOLATILE).
WCR7
WCR6
WCR5
WCR4
WCR3
WCR2
WCR1
(MSB)
WCR0
(LSB)
TABLE 2. DATA REGISTER, DR (8-BIT), BIT [7:0]: USED TO STORE WIPER POSITIONS OR DATA (NONVOLATILE).
BIT 7
BIT 6
BIT 5
(MSB)
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BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
(LSB)
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X9259
Serial Interface
condition can only be issued after the transmitting device has
released the bus.
The X9259 supports a bidirectional bus oriented protocol. The
protocol defines any device that sends data onto the bus as a
transmitter and the receiving device as the receiver. The device
controlling the transfer is a master and the device being
controlled is the slave. The master always initiates data transfers
and provide the clock for both transmit and receive operations.
Therefore, the X9259 operates as a slave device in all
applications.
All 2-wire interface operations must begin with a START, followed
by an Identification Byte, that selects the X9259. All
communication over the 2-wire interface is conducted by sending
the MSB of each byte of data first.
Clock and Data Conventions
Data states on the SDA line can change only during SCL LOW
periods. SDA state changes during SCL HIGH are reserved for
indicating START and STOP conditions (see Figure 2). On
power-up of the X9259, the SDA pin is in the input mode.
START Condition
All commands to the X9259 are preceded by the start condition,
which is a HIGH to LOW transition of SDA while SCL is HIGH. The
X9259 continuously monitors the SDA and SCL lines for the
START condition and does not respond to any command until this
condition is met (see Figure 2).
STOP Condition
All communications must be terminated by a STOP condition,
which is a LOW to HIGH transition of SDA while SCL is HIGH, (see
Figure 2). The STOP condition is also used to place the device
into the Standby Power mode after a Read sequence. A STOP
Acknowledge
An ACK, Acknowledge, is a software convention used to indicate
a successful data transfer. The transmitting device, either master
or slave, releases the SDA bus after transmitting eight bits.
During the ninth clock cycle, the receiver pulls the SDA line LOW
to acknowledge the reception of the eight bits of data, (see
Figure 3).
The X9259 responds with an ACK after recognition of a START
condition followed by a valid Identification Byte, and once again
after successful receipt of an Instruction Byte. The X9259 also
responds with an ACK after receiving a Data Byte after a Write
Instruction.
A valid Identification Byte contains the Device Type Identifier
0101, as the four MSBs, and the Device Address bits matching
the logic states of pins A3, A2, A1, and A0, as the four LSBs (see
Figure 4 on page 8).
In the Read mode, the device transmits eight bits of data,
releases the SDA line, and then monitors the line for an ACK. The
device continues transmitting data if an ACK is detected. The
device terminates further data transmissions if an ACK is not
detected. The master must then issue a STOP condition to place
the device into a known state.
During the internal nonvolatile Write operation, the X9259
ignores the inputs at SDA and SCL, and does not issue an ACK
after Identification bytes.
SCL
SDA
START
DATA
STABLE
DATA
CHANGE
DATA
STABLE
STOP
FIGURE 2. VALID DATA CHANGES, START, AND STOP CONDITIONS
SCL FROM
MASTER
1
8
9
SDA OUTPUT FROM
TRANSMITTER
SDA OUTPUT FROM
RECEIVER
START
ACK
FIGURE 3. ACKNOWLEDGE RESPONSE FROM RECEIVER
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X9259
Identification Byte
The least two significant bits point to one of four Wiper Counter
Registers or DCPs. The format is shown in Table 4.
The first byte sent to the X9259 from the host is called the
Identification Byte. The most significant four bits are a Device
Type Identifier, ID[3:0] bits, which must be 0101. Refer to
Table 3.
Data Register Selection
REGISTER
RB
RA
DR#0
0
0
DR#1
0
1
DR#2
1
0
DR#3
1
1
Only the device which Slave Address matches the incoming
device address sent by the master executes the instruction. The
A3 - A0 inputs can be actively driven by CMOS input signals or
tied to VCC or VSS.
#: 0, 1, 2, or 3
INSTRUCTION BYTE (I)
The next byte sent to the X9259 contains the instruction and
register pointer information. The four most significant bits are
used provide the instruction opcode I [3:0]. The RB and RA bits
point to one of the four data registers of each associated XDCP.
The least significant four bits of the Identification Byte are the
Slave Address bits, AD[3:0]. To access the X9259, these four bits
must match the logic values of pins A3, A2, A1, and A0.
TABLE 3. IDENTIFICATION BYTE FORMAT
DEVICE TYPE IDENTIFIER
SLAVE ADDRESS
ID3
ID2
ID1
ID0
0
1
0
1
A3
A2
A1
A0
Logic value of pins A3, A2, A1, and A0
(MSB)
(LSB)
TABLE 4. INSTRUCTION BYTE FORMAT
INSTRUCTION OPCODE
I3
I2
REGISTER SELECTION
I1
I0
RB
RA
DCP SELECTION
(WCR SELECTION)
P1
(MSB)
P0
(LSB)
TABLE 5. INSTRUCTION SET
INSTRUCTION SET
I3
I2
I1
I0
RB
RA
P1
P0
Read Wiper Counter
Register
INSTRUCTION
1
0
0
1
0
0
1/0
1/0 Read the contents of the Wiper Counter Register pointed
to by P1 - P0
OPERATION
Write Wiper Counter Register
1
0
1
0
0
0
1/0
1/0 Write new value to the Wiper Counter
Register pointed to by P1 - P0
Read Data Register
1
0
1
1
1/0
1/0
1/0
1/0 Read the contents of the Data Register pointed to by
P1 - P0 and RB - RA
Write Data Register
1
1
0
0
1/0
1/0
1/0
1/0 Write new value to the Data Register
pointed to by P1 - P0 and RB - RA
XFR Data Register to Wiper Counter
Register
1
1
0
1
1/0
1/0
1/0
1/0 Transfer the contents of the Data Register pointed to by
P1 - P0 and RB - RA to its
associated Wiper Counter Register
XFR Wiper Counter Register to Data
Register
1
1
1
0
1/0
1/0
1/0
1/0 Transfer the contents of the Wiper Counter Register
pointed to by P1 - P0 to the Data Register pointed to by
RB - RA
Global XFR Data Registers to Wiper
Counter Registers
0
0
0
1
1/0
1/0
0
0
Transfer the contents of the Data Registers pointed to by
RB - RA of all four pots to their respective Wiper Counter
Registers
Global XFR Wiper Counter Registers
to Data Register
1
0
0
0
1/0
1/0
0
0
Transfer the contents of both Wiper Counter Registers to
their respective data Registers pointed to by RB - RA of
all four DCPs
Increment/Decrement Wiper Counter
Register
0
0
1
0
0
0
1/0
1/0 Enable Increment/decrement of the Control Latch
pointed to by P1 - P0
NOTE: 1/0 = data is one or zero
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X9259
Instructions
between the host and the Wiper Counter Register. These
instructions are:
Four of the nine instructions are three bytes in length. These
instructions are:
• XFR Data Register to Wiper Counter Register – This transfers
the contents of one specified Data Register to the associated
Wiper Counter Register.
• Read Wiper Counter Register – read the current wiper position
of the selected potentiometer.
• XFR Wiper Counter Register to Data Register – This transfers
the contents of the specified Wiper Counter Register to the
specified associated Data Register.
• Write Wiper Counter Register – change current wiper position
of the selected potentiometer.
• Read Data Register – read the contents of the selected Data
Register.
• Global XFR Data Register to Wiper Counter
Register – This transfers the contents of all specified Data
Registers to the associated Wiper Counter Registers.
• Write Data Register – write a new value to the selected Data
Register.
• Global XFR Wiper Counter Register to Data
Register – This transfers the contents of all Wiper Counter
Registers to the specified associated Data Registers.
The basic sequence of the three byte instructions is illustrated in
Figure 5. These three-byte instructions exchange data between
the WCR and one of the Data Registers. A transfer from a Data
Register to a WCR is essentially a write to a static RAM, with the
static RAM controlling the wiper position. The response of the
wiper to this action is delayed by tWRL. A transfer from the WCR
(current wiper position), to a Data Register is a write to
nonvolatile memory and takes a minimum of tWR to complete.
The transfer can occur between one of the four potentiometer’s
WCR, and one of its associated registers, DRs; or it may occur
globally, where the transfer occurs between all potentiometers
and one associated register.
Increment/Decrement Command
The final command is Increment/Decrement (Figures 6 and 7).
The Increment/Decrement command is different from the other
commands. Once the command is issued and the X9259 has
responded with an Acknowledge, the master can clock the
selected wiper up and/or down in one segment steps; thereby,
providing a fine tuning capability to the host. For each SCL clock
pulse (tHIGH) while SDA is HIGH, the selected wiper moves one
wiper position towards the RH terminal. Similarly, for each SCL
clock pulse while SDA is LOW, the selected wiper moves one
resistor wiper position towards the RL terminal.
Four instructions require a two-byte sequence to complete. These
instructions transfer data between the host and the X9259;
either between the host and one of the data registers or directly
See “Instruction Format” on page 10 for more details.
SCL
SDA
0
1
0
1
S ID3 ID2 ID1 ID0 A3
T
A
R
Device ID
T
A2 A1
A0
A I3
C
K
External
Address
I2
I1
Instruction
Opcode
A
C
K
DCP/WCR
Address
S
T
O
P
D6 D5 D4
D3
RB RA P1 P0
I0
Register
Address
FIGURE 4. TWO-BYTE INSTRUCTION SEQUENCE
SCL
SDA
0
S
T
A
R
T
1
0
1
ID3 ID2 ID1 ID0 A3
A2
A1
A0
External
Address
Device ID
A
C
K
I3
I2
I1
I0
Instruction
Opcode
RB RA
P1 P0
Register Pot/WCR
Address Address
A
C
K
D7
D2
D1 D0
Data for WCR[7:0] or DR[7:0]
A
C
K
S
T
O
P
FIGURE 5. THREE-BYTE INSTRUCTION SEQUENCE 2-WIRE INTERFACE
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December 12, 2014
X9259
SCL
SDA
S
T
A
R
T
0
1
ID3
ID2
0
1
ID1 ID0
A3
A2
A1
External
Address
Device ID
A0
A
C
K
I3
I2
I1
Instruction
Opcode
I0
RB RA P1
P0
A
C
Register Pot/WCR K
Address Address
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
S
T
O
P
FIGURE 6. INCREMENT/DECREMENT INSTRUCTION SEQUENCE 2-WIRE INTERFACE
INC/DEC
CMD
ISSUED
tWRID
SCL
SDA
VOLTAGE OUT
RW
FIGURE 7. INCREMENT/DECREMENT TIMING SPECIFICATION
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December 12, 2014
X9259
Instruction Format
Read Wiper Counter Register (WCR)
S
T
A
R
T
DEVICE TYPE
IDENTIFIER
0
1
0
DEVICE
ADDRESSES
1
A3
A2
A1
INSTRUCTION
OPCODE
S
A
C
K
A0
1
0
0
DR/WCR
ADDRESSES
1
0
0
P1
P0
S
A
C
K
P0
S
A
C
K
WIPER POSITION
(SENT BY X9259 ON SDA)
W
C
R
7
W
C
R
6
W
C
R
5
W
C
R
1
W
C
R
2
W
C
R
3
W
C
R
4
W
C
R
0
M
A
C
K
S
T
O
P
S
A
C
K
S
T
O
P
Write Wiper Counter Register (WCR)
S
T
A
R
T
DEVICE TYPE
IDENTIFIER
0
1
0
DEVICE
ADDRESSES
1
A3
A2
A1
INSTRUCTION
OPCODE
S
A
C
K
A0
1
0
1
DR/WCR
ADDRESSES
0
0
0
P1
WIPER POSITION
(SENT BY MASTER ON SDA)
W
C
R
7
W
C
R
6
W
C
R
5
W
C
R
1
W
C
R
2
W
C
R
3
W
C
R
4
W
C
R
0
Read Data Register (DR)
S
T
A
R
T
DEVICE TYPE
IDENTIFIER
0
1
0
DEVICE
ADDRESSES
1
A3
A2
A1
A0
INSTRUCTION
OPCODE
S
A
C
K
1
0
1
DR/WCR
ADDRESSES
1
RB
RA
P1
WIPER POSITION
(SENT BY X9259 ON SDA)
S
A
C
K
P0
W W W W W W W W
C C C C C C C C
R R R R R R R R
7 6 5 4 3 2 1 0
M
A
C
K
S
T
O
P
S
T
A
R
T
DEVICE TYPE
IDENTIFIER
0
1
0
DEVICE
ADDRESSES
1
A3
A2
A1
A0
S
A
C
K
INSTRUCTION
OPCODE
1
1
0
0
DR/WCR
ADDRESSES
RB
RA
P1
P0
WIPER POSITION
(SENT BY MASTER ON SDA)
S
A W W W W W W W W
C C C C C C C C C
K R R R R R R R R
7 6 5 4 3 2 1 0
S
A
C
K
S
T
O
P
HIGH-VOLTAGE
WRITE CYCLE
Write Data Register (DR)
Global XFR Data Register (DR) to Wiper Counter Register (WCR)
S
T
A
R
T
DEVICE TYPE
IDENTIFIER
0
1
0
DEVICE
ADDRESSES
1
A3
A2
A1
INSTRUCTION
OPCODE
S
A
C
K
A0
0
0
0
DR/WCR
ADDRESSES
1
RB
RA
0
S
A
C
K
0
S
T
O
P
Global XFR Wiper Counter Register (WCR) to Data Register (DR)
S
T
A
R
T
DEVICE TYPE
IDENTIFIER
0
1
0
DEVICE
ADDRESSES
1
A3
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A2
A1
10
A0
S
A
C
K
INSTRUCTION
OPCODE
1
0
0
0
DR/WCR
ADDRESSES
RB
RA
0
0
S
A
C
K
S
T
O
P
HIGH-VOLTAGE
WRITE CYCLE
FN8169.6
December 12, 2014
X9259
Transfer Wiper Counter Register (WCR) to Data Register (DR)
S
T
A
R
T
DEVICE TYPE
IDENTIFIER
0
1
0
DEVICE
ADDRESSES
1
A3
A2
A1
INSTRUCTION
OPCODE
S
A
C
K
A0
1
1
1
0
DR/WCR
ADDRESSES
RB
RA
P1
S
A
C
K
P0
S
T
O
P
HIGH-VOLTAGE
WRITE CYCLE
Transfer Data Register (DR) to Wiper Counter Register (WCR)
S
T
A
R
T
DEVICE TYPE
IDENTIFIER
0
1
0
DEVICE
ADDRESSES
1
A3
A2
A1
A0
INSTRUCTION
OPCODE
S
A
C
K
1
1
0
DR/WCR
ADDRESSES
1
RB
RA
P1
S
A
C
K
P0
S
T
O
P
Increment/Decrement Wiper Counter Register (WCR)
S
T
A
R
T
DEVICE TYPE
IDENTIFIER
0
1
0
1
DEVICE
ADDRESSES
A3
A2
A1
A0
S
A
C
K
INSTRUCTION
OPCODE
0
0
1
0
DR/WCR
ADDRESSES
0
0
P1
P0
S
A
C
K
INCREMENT/DECREMENT
(SENT BY MASTER ON SDA)
I/D
I/D
.
.
.
.
I/D
I/D
S
T
O
P
NOTES:
5. “MACK”/”SACK”: stands for the acknowledge sent by the Master/Slave.
6. “A3 ~ A0”: stands for the device addresses sent by the master.
7. “X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition.
8. “I”: stands for the increment operation, SDA held high during active SCL phase (high).
9. “D”: stands for the decrement operation, SDA held low during active SCL phase (high).
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X9259
Absolute Maximum Ratings
Recommended Operating Conditions
Temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +135C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C
Voltage on SCL, SDA, any address input, VCC
with respect to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-1V to +7V
V = | (VH–VL) | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5.5V
Lead temperature (soldering, 10 seconds) . . . . . . . . . . . . . . . . . . . . . 300C
IW (10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
Temperature (Commercial) . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Temperature (Industrial) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Supply Voltage (VCC) (Note 13) Limits
X9259 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ± 10%
X9259-2.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Wiper current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3mA
Power rating (each pot) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mW
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
Analog Specifications
Over recommended industrial (2.7V) operating conditions unless otherwise stated.
LIMITS
SYMBOL
RTOTAL
PARAMETER
End-to-End Resistance
TEST CONDITIONS
MIN
U version
TYP
Wiper Resistance
IW =
IW =
V TERM
V(VCC)
RTOTAL
V(VCC)
RTOTAL
Voltage on any RH or RL Pin
VSS = 0V
Noise (Note 15)
Ref: 1V
kΩ
±20
%
300
Ω
220
Ω
VCC
V
at VCC = 3V
at VCC = 5V
VSS
Resolution
CH/CL/CW
UNITS
50
End-to-End Resistance Tolerance
RW
MAX
Absolute Linearity (Note 10)
Rw(n)(actual) - Rw(n)(expected) (Note 14)
Relative Linearity (Note 11)
Rw(n + 1) - [Rw(n) + MI] (Note 14)
-120
dBHz
0.4
%
-1
+1
MI (Note 12)
-0.6
+0.6
MI (Note 12)
Temperature Coefficient of RTOTAL
(Note 15)
300
ppm/C
Ratiometric Temp. Coefficient (Note 15)
20
ppm/°C
10/10/25
pF
Potentiometer Capacitances (Note 15)
See SPICE Macromodel on page 14.
NOTES:
10. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
11. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
12. MI = RTOT / 255 or (RH – RL) / 255, single pot
13. During power up VCC > VH, VL, and VW.
14. n = 0, 1, 2, …,255; m = 0, 1, 2, …, 254.
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X9259
DC Electrical Specifications
Over the recommended operating conditions unless otherwise specified.
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ICC1
VCC supply current
(active)
fSCL = 400kHz; VCC = +6V;
SDA = Open; (for 2-Wire, Active, Read and
Volatile Write States only)
3
mA
ICC2
VCC supply current
(nonvolatile write)
fSCL = 400kHz; VCC = +6V;
SDA = Open; (for 2-Wire, Active,
Nonvolatile Write State only)
5
mA
ISB
VCC current (standby)
VCC = +6V; VIN = VSS or VCC; SDA = VCC;
(for 2-Wire, Standby State only)
5
µA
ILI
Input leakage current
VIN = VSS to VCC
10
µA
ILO
Output leakage current
VOUT = VSS to VCC
10
µA
VIH
Input HIGH voltage
VCC x 0.7
V
VIL
Input LOW voltage
VOL
Output LOW voltage
IOL = 3mA
VOH
Output HIGH voltage
IOH = -1mA, VCC  +3V
VCC - 0.8
V
VOH
Output HIGH voltage
IOH = -0.4mA, VCC  +3V
VCC - 0.4
V
VCC x 0.3
V
0.4
V
Endurance and Data Retention
PARAMETER
Minimum endurance
MIN
UNITS
100,000
Data changes per bit per register
100
years
Data retention
Capacitance
SYMBOL
TEST
MAX
UNITS
TEST CONDITIONS
CIN/OUT (Note 15) Input / Output capacitance (SDA)
8
pF
VOUT = 0V
CIN (Note 15)
6
pF
VIN = 0V
Input capacitance (SCL, WP, A2, A1 and A0)
Power-up Timing
SYMBOL
tr VCC (Note 15)
PARAMETER
VCC Power-up rate
MIN
MAX
0.2
UNITS
V/ms
tPUR (Note 16)
Power-up to initiation of read operation
1
ms
tPUW (Note 16)
Power-up to initiation of write operation
50
ms
AC Test Conditions
Input Pulse Levels
VCC x 0.1 to VCC x 0.9
Input rise and fall times
10ns
Input and output timing level
VCC x 0.5
NOTES:
15. This parameter is not 100% tested
16. tPUR and tPUW are the delays required from the time the power supply (VCC) is stable until the specific instruction can be issued. These parameters
are periodically sampled and not 100% tested.
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December 12, 2014
X9259
Equivalent AC Load Circuit
5V
SPICE Macromodel
1533Ω
RTOTAL
RH
SDA pin
RL
CW
CL
CL
10pF
100pF
25pF
10pF
RW
AC Timing
SYMBOL
PARAMETER
MIN
MAX
UNITS
400
kHz
fSCL
Clock Frequency
tCYC
Clock Cycle Time
2500
ns
tHIGH
Clock High Time
600
ns
tLOW
Clock Low Time
1300
ns
tSU:STA
Start Setup Time
600
ns
tHD:STA
Start Hold Time
600
ns
tSU:STO
Stop Setup Time
600
ns
tSU:DAT
SDA Data Input Setup Time
100
ns
tHD:DAT
SDA Data Input Hold Time
30
ns
tR
SCL and SDA Rise Time
300
ns
tF
SCL and SDA Fall Time
300
ns
tAA
SCL Low to SDA Data Output Valid Time
0.9
µs
tDH
SDA Data Output Hold Time
0
ns
Noise Suppression Time Constant at SCL and SDA inputs
50
ns
1200
ns
TI
tBUF
Bus Free Time (Prior to Any Transmission)
tSU:WPA
A0, A1 Setup Time
0
ns
tHD:WPA
A0, A1 Hold Time
0
ns
High-Voltage Write Cycle Timing
SYMBOL
PARAMETER
tWR
High-voltage write cycle time (store instructions)
TYP
MAX
UNITS
5
10
ms
XDCP Timing
SYMBOL
tWRPO
tWRL
PARAMETER
MIN
MAX
UNITS
Wiper response time after the third (last) power supply is stable
5
10
µs
Wiper response time after instruction issued (all load instructions)
5
10
µs
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FN8169.6
December 12, 2014
X9259
Symbol Table
WAVEFORM
.
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
Timing Diagrams
Start and Stop Timing
(START)
(STOP)
tR
tF
SCL
tSU:STA
tHD:STA
tSU:STO
tR
tF
SDA
Input Timing
tCYC
tHIGH
SCL
tLOW
SDA
tSU:DAT
tHD:DAT
tBUF
Output Timing
SCL
SDA
tAA
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tDH
FN8169.6
December 12, 2014
X9259
XDCP Timing (for All Load Instructions)
(STOP)
SCL
LSB
SDA
tWRL
VWx
Write Protect and Device Address Pins Timing
(START)
(STOP)
SCL
...
(Any Instruction)
...
SDA
...
tSU:WPA
tHD:WPA
WP
A0, A1
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16
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December 12, 2014
X9259
Applications Information
Basic Configurations of Electronic Potentiometers
+VR
VR
RW
I
Three-terminal
Potentiometer;
Variable voltage divider
Two-terminal Variable
Resistor;
Variable current
Application Circuits
Non inverting Amplifier
VS
Voltage Regulator
+
VO
–
VIN
VO (REG)
317
R1
R2
Iadj
R1
R2
VO = (1+R2/R1)VS
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
Offset Voltage Adjustment
R1
Comparator with Hysteresis
R2
VS
VS
–
+
VO
100kΩ
–
VO
+
+12V
10kΩ
}
10kΩ
}
TL072
10kΩ
R1
R2
VUL = {R1/(R1+R2)} VO(max)
RLL = {R1/(R1+R2)} VO(min)
-12V
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FN8169.6
December 12, 2014
X9259
Application Circuits (continued)
Attenuator
Filter
C
VS
+
R2
R1
VS
VO
–
–
R
VO
+
R3
R4
R2
R1 = R2 = R3 = R4 = 10kΩ
R1
GO = 1 + R2/R1
fc = 1/(2RC)
VO = G VS
-1/2  G  +1/2
R1
R2
}
}
Inverting Amplifier
Equivalent L-R Circuit
VS
R2
C1
–
VS
VO
+
+
–
R1
ZIN
VO = G VS
G = - R2/R1
R3
ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq
(R1 + R3) >> R2
Function Generator
C
R2
–
R1
–
+
} RA
+
} RB
frequency  R1, R2, C
amplitude  RA, RB
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December 12, 2014
X9259
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE
REVISION
December 12, 2014
FN8169.6
CHANGE
Updated Datasheet to Intersil new standards.
Updated Ordering Information Table on page 2, by removing obsoleted parts and 100kΩ referenced parts,
adding Note 3 and changed TSSOP POD references from “MDP0044” to “M24.173”.
On page 3. in the Pin Descriptions table removed duplicate entry for Pin 6.
Added Revision History and About Intersil Verbiage
Updated M24.3 POD to the latest revision.
-“Updated to new POD standard by removing table listing dimensions and putting dimensions on drawing.
Added Land Pattern.”
Replaced MDP0044 POD with M24.173 POD to update to new format and only show 24LD version.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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19
FN8169.6
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X9259
Package Outline Drawing
M24.3
24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE (SOIC)
Rev 2, 3/11
24
INDEX
AREA
7.60 (0.299)
7.40 (0.291) 10.65 (0.419)
10.00 (0.394)
DETAIL "A"
1
2
3
TOP VIEW
1.27 (0.050)
0.40 (0.016)
SEATING PLANE
2.65 (0.104)
2.35 (0.093)
15.60 (0.614)
15.20 (0.598)
0.75 (0.029)
x 45°
0.25 (0.010)
0.30 (0.012)
0.10 (0.004)
1.27 (0.050)
0.51 (0.020)
0.33 (0.013)
8°
0°
0.32 (0.012)
0.23 (0.009)
SIDE VIEW “B”
SIDE VIEW “A”
1.981 (0.078)
9.373 (0.369)
1.27 (0.050)
NOTES:
1. Dimensioning and tolerancing per ANSI Y14.5M-1982.
2. Package length does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
3. Package width does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm
(0.010 inch) per side.
4. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
5. Terminal numbers are shown for reference only.
6. The lead width as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch).
7. Controlling dimension: MILLIMETER. Converted inch dimensions in
( ) are not necessarily exact.
8. This outline conforms to JEDEC publication MS-013-AD ISSUE C.
0.533 (0.021)
TYPICAL RECOMMENDED LAND PATTERN
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FN8169.6
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X9259
Package Outline Drawing
M24.173
24 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Rev 1, 5/10
A
1
3
7.80 ±0.10
SEE DETAIL "X"
13
24
6.40
PIN #1
I.D. MARK
4.40 ±0.10
2
3
0.20 C B A
1
12
0.15 +0.05
-0.06
B
0.65
TOP VIEW
END VIEW
1.00 REF
H
- 0.05
C
0.90 +0.15
-0.10
1.20 MAX
GAUGE
PLANE
SEATING PLANE
0.25 +0.05
-0.06
0.10 M C B A
0.10 C
5
0°-8°
0.05 MIN
0.15 MAX
SIDE VIEW
0.25
0.60± 0.15
DETAIL "X"
(1.45)
NOTES:
1. Dimension does not include mold flash, protrusions or gate burrs.
(5.65)
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
2. Dimension does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.25 per side.
3. Dimensions are measured at datum plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Dimension does not include dambar protrusion. Allowable protrusion
shall be 0.08mm total in excess of dimension at maximum material
condition. Minimum space between protrusion and adjacent lead
(0.65 TYP)
(0.35 TYP)
TYPICAL RECOMMENDED LAND PATTERN
is 0.07mm.
6. Dimension in ( ) are for reference only.
7. Conforms to JEDEC MO-153.
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FN8169.6
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