DATASHEET

X9312
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8
8
1-8
®
Digitally Controlled Potentiometer
(XDCP™)
•
•
•
•
•
March 15, 2005
FN8176.0
DESCRIPTION
The Intersil X9312 is a digitally controlled
potentiometer (XDCP). The device consists of a
resistor array, wiper switches, a control section, and
nonvolatile memory. The wiper position is controlled
by a 3-wire interface.
FEATURES
•
•
•
•
Terminal Voltage 0V to +15V, 100 Taps
Solid-state potentiometer
3-wire serial interface
Terminal voltage, 0 to +15V
100 wiper tap points
—Wiper position stored in nonvolatile memory
and recalled on power-up
99 resistive elements
—Temperature compensated
—End to end resistance range ± 20%
Low power CMOS
—VCC = 5V
—Active current, 3mA max.
—Standby current, 1mA max.
High reliability
—Endurance, 100,000 data changes per bit
—Register data retention, 100 years
RTOTAL values = 10kΩ, 50kΩ, and 100kΩ
Packages
—8-lead SOIC and DIP
The potentiometer is implemented by a resistor array
composed of 99 resistive elements and a wiper
switching network. Between each element and at
either end are tap points accessible to the wiper
terminal. The position of the wiper element is
controlled by the CS, U/D, and INC inputs. The
position of the wiper can be stored in nonvolatile
memory and then be recalled upon a subsequent
power-up operation.
The device can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including:
– control
– parameter adjustments
– signal processing
BLOCK DIAGRAM
U/D
INC
CS
VCC (Supply Voltage)
Control
and
Memory
RW/VW
Device Select
(CS)
RH/VH
99
98
97
RH/VH
Up/Down
(U/D)
Increment
(INC)
7-Bit
Up/Down
Counter
7-Bit
Nonvolatile
Memory
RL/VL
96
One
of
One
Hundred
Decoder
Transfer
Gates
Resistor
Array
2
VSS (Ground)
VCC
VSS
General
Store and
Recall
Control
Circuitry
1
0
RL/VL
RW/VW
Detailed
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9312
PIN NAMES
PIN DESCRIPTIONS
RH/VH and RL/VL
Symbol
The high (RH/VH) and low (RL/VL) terminals of the
X9312 are equivalent to the fixed terminals of a
mechanical potentiometer. The minimum voltage is 0V
and the maximum is +15V. The terminology of RL/VL
and RH/VH references the relative position of the
terminal in relation to wiper movement direction
selected by the U/D input and not the voltage potential
on the terminal.
RW/VW
Rw/Vw is the wiper terminal and is equivalent to the
movable terminal of a mechanical potentiometer. The
position of the wiper within the array is determined by
the control inputs. The wiper terminal series resistance
is typically 40Ω.
Up/Down (U/D)
The U/D input controls the direction of the wiper
movement and whether the counter is incriminated or
decremented.
Increment (INC)
The INC input is negative-edge triggered. Toggling
INC will move the wiper and either increment or
decrement the counter in the direction indicated by the
logic level on the U/D input.
Chip Select (CS)
The device is selected when the CS input is LOW. The
current counter value is stored in nonvolatile memory
when CS is returned HIGH while the INC input is also
HIGH. After the store operation is complete the X9312
will be placed in the low power standby mode until the
device is selected once again.
PIN CONFIGURATION
DIP/SOIC
INC
1
8
VCC
U/D
2
7
CS
RH/VH
3
6
RL/VL
VSS
4
5
RW/VW
X9312
2
Description
RH/VH
High terminal
RW/VW
Wiper terminal
RL/VL
Low terminal
VSS
Ground
VCC
Supply voltage
U/D
Up/Down control input
INC
Increment control input
CS
Chip select control input
PRINCIPLES OF OPERATION
There are three sections of the X9312: the input
control, counter and decode section; the nonvolatile
memory; and the resistor array. The input control
section operates just like an up/down counter. The
output of this counter is decoded to turn on a single
electronic switch connecting a point on the resistor
array to the wiper output. Under the proper conditions
the contents of the counter can be stored in
nonvolatile memory and retained for future use. The
resistor array is comprised of 99 individual resistors
connected in series. At either end of the array and
between each resistor is an electronic switch that
transfers the potential at that point to the wiper.
The wiper, when at either fixed terminal, acts like its
mechanical equivalent and does not move beyond the
last position. That is, the counter does not wrap
around when clocked to either extreme.
The electronic switches on the device operate in a
“make before break” mode when the wiper changes
tap positions. If the wiper is moved several positions,
multiple taps are connected to the wiper for tIW (INC to
VW change). The RTOTAL value for the device can
temporarily be reduced by a significant amount if the
wiper is moved several positions.
When the device is powered-down, the last wiper
position stored will be maintained in the nonvolatile
memory. When power is restored, the contents of the
memory are recalled and the wiper is set to the value
last stored.
FN8176.0
March 15, 2005
X9312
INSTRUCTIONS AND PROGRAMMING
The INC, U/D and CS inputs control the movement of
the wiper along the resistor array. With CS set LOW
the device is selected and enabled to respond to the
U/D and INC inputs. HIGH to LOW transitions on INC
will increment or decrement (depending on the state of
the U/D input) a seven bit counter. The output of this
counter is decoded to select one of one hundred wiper
positions along the resistive array.
The value of the counter is stored in nonvolatile
memory whenever CS transitions HIGH while the INC
input is also HIGH.
The system may select the X9312, move the wiper
and deselect the device without having to store the
latest wiper position in nonvolatile memory. After the
wiper movement is performed as described above and
once the new position is reached, the system must
keep INC LOW while taking CS HIGH. The new wiper
position will be maintained until changed by the
system or until a powerup/down cycle recalled the
previously stored data.
This procedure allows the system to always power-up
to a preset value stored in nonvolatile memory; then
during system operation minor adjustments could be
made. The adjustments might be based on user
preference, system parameter changes due to
temperature drift, etc...
MODE SELECTION
CS
INC
U/D
Mode
L
H
Wiper up
L
L
Wiper down
H
X
Store wiper position
X
X
Standby current
L
X
No store, return to standby
H
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
The state of U/D may be changed while CS remains
LOW. This allows the host system to enable the
device and then move the wiper up and down until the
proper trim is attained.
3
FN8176.0
March 15, 2005
X9312
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias .................... -65°C to +135°C
Storage temperature ......................... -65°C to +150°C
Voltage on CS, INC, U/D and VCC
with respect to VSS ................................. -1V to +7V
∆V = |VH - VL| ........................................................ 15V
Lead temperature (soldering 10 seconds) ......... 300°C
IW (10 seconds) ...............................................±8.8mA
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification)
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature
Min.
Max.
Supply Voltage (VCC)
Limits
Commercial
0°C
+70°C
X9312
5V ±10%
Industrial
-40°C
+85°C
POTENTIOMETER CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Limits
Symbol
Parameter
Min.
Typ.
End to end resistance tolerance
Max.
Unit
Test Conditions/Notes
±20
%
VVH
VH terminal voltage
VSS
15
V
VSS = 0V
VVL
VL terminal voltage
VSS
15
V
VSS = 0V
Power rating
25
mW
RTOTAL ≥ 10kΩ
Power rating
225
mW
RTOTAL = 1kΩ
100
Ω
±4.4
mA
RW
Wiper resistance
IW
Wiper current
Noise
40
-120
Resolution
dBV
1
IW = 1mA, VCC = 5V
Ref: 1kHz
%
Absolute linearity(1)
±1
MI(3)
Rw(n)(actual) - Rw(n)(expected)
Relative linearity(2)
±0.2
MI(3)
Rw(n+1) - [Rw(n) + MI]
RTOTAL temperature coefficient
±300
Ratiometric temperature coefficient
CH/CL/CW Potentiometer capacitances
ppm/°C
±20
10/10/25
ppm/°C
pF
See circuit #3
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage = (Vw(n)(actual) - Vw(n)(expected)) = ±1 Ml
Maximum.
(2) Relative linearity is a measure of the error in step size between taps = RW(n+1 - [Rw(n) + Ml] = ±0.2 Ml.
(3) 1 Ml = Minimum Increment = RTOT/99.
4
FN8176.0
March 15, 2005
X9312
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Typ.(4)
Max.
Unit
1
3
mA
CS = VIL, U/D = VIL or VIH and
INC = 0.4V/2.4V @ max. tCYC
500
1000
µA
CS = VCC - 0.3V, U/D and
INC = VSS or VCC - 0.3V
±10
µA
VIN = VSS to VCC
ICC
VCC active current (Increment)
ISB
Standby supply current
ILI
CS, INC, U/D input leakage current
VIH
CS, INC, U/D input HIGH voltage
2
VCC + 1
V
VIL
CS, INC, U/D input LOW voltage
-1
0.8
V
CIN(5)
CS, INC, U/D input capacitance
10
pF
Test Conditions
VCC = 5V, VIN = VSS, TA = 25°C,
f = 1MHz
ENDURANCE AND DATA RETENTION
Parameter
Min.
Unit
Minimum endurance
100,000
Data changes per bit
Data retention
100
Years
Notes: (4) Typical values are for TA = 25°C and nominal supply voltage.
(5) This parameter is periodically sampled and not 100% tested.
Test Circuit #1
Test Circuit #2
VH/RH
VH/RH
VS
Circuit #3 SPICE Macro Model
Test Point
Test Point
VW/RW
VLL/RL
VL/RL
VW/RW
VW
Force
Current
RTOTAL
RH
CW
CH
CL
RL
10pF
25pF
10pF
RW
A.C. CONDITIONS OF TEST
Input pulse levels
0V to 3V
Input rise and fall times
10ns
Input reference levels
1.5V
5
FN8176.0
March 15, 2005
X9312
A.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified)
Limits
Symbol
Parameter
Typ.6
Min.
Max.
Unit
tCl
CS to INC setup
100
ns
tlD
INC HIGH to U/D change
100
ns
tDI
U/D to INC setup
1
µs
tlL
INC LOW period
1
µs
tlH
INC HIGH period
1
µs
tlC
INC inactive to CS inactive
1
µs
tCPH
CS deselect time (STORE)
20
ms
tCPH
CS deselect time (NO STORE)
100
ns
tIW
INC to Vw change
100
500
µs
tCYC
INC cycle time
t R , t F7
INC input rise and fall time
500
µs
Power-up to wiper stable
500
µs
50
V/ms
tPU
7
tR VCC
7
4
VCC power-up rate
µs
0.2
POWER-UP AND DOWN REQUIREMENTS
There are no restrictions on the sequencing of VCC and the voltages applied to the potentiometer pins during powerup or power-down conditions. During power-up, the data sheet parameters for the DCP do not fully apply until 1
millisecond after VCC reaches is final value. The VCC ramp spec is always in effect.
A.C. TIMING
CS
tCYC
tCI
tIL
tIC
tIH
tCPH
90%
90%
10%
INC
tID
tDI
tF
tR
U/D
tIW
MI
VW
(8)
Notes: (6) Typical values are for TA = 25°C and nominal supply voltage.
(7) This parameter is sample tested.
(8) MI in the A.C. timing diagram refers to the minimum incremental change in the VW output due to a change in the wiper position.
6
FN8176.0
March 15, 2005
X9312
APPLICATIONS INFORMATION
Electronic digitally controlled (XDCP) potentiometers provide three powerful application advantages; (1) the variability
and reliability of a solid-state potentiometer, (2) the flexibility of computer-based digital controls, and (3) the retentivity
of nonvolatile memory used for the storage of multiple potentiometer settings or data.
Basic Configurations of Electronic Potentiometers
VR
VR
VH
VW/RW
VL
I
Three terminal potentiometer;
variable voltage divider
Two terminal variable resistor;
variable current
Basic Circuits
Buffered Reference Voltage
Noninverting Amplifier
Cascading Techniques
R1
+V
+5V
+V
+V
VS
+5V
VW
VREF
VOUT
–
VO
–
OP-07
+
LM308A
+
–5V
X
VW/RW
R2
+V
-5V
R1
VW/RW
VOUT = VW/RW
(a)
Voltage Regulator
VIN
(b)
VO = (1+R2/R1)VS
Offset Voltage Adjustment
VO (REG)
317
R1
Comparator with Hysteresis
R2
VS
VS
R1
LT311A
100kΩ
–
+
VO
–
VO
+
Iadj
10kΩ
10kΩ
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
+12V
}
10kΩ
}
TL072
R2
R1
R2
VUL = {R1/(R1+R2)} VO(max)
VLL = {R1/(R1+R2)} VO(min)
-12V
(for additional circuits see AN115)
7
FN8176.0
March 15, 2005
X9312
PACKAGING INFORMATION
8-Lead Plastic Small Outline Gull Wing Package Type S
0.150 (3.80) 0.228 (5.80)
0.158 (4.00) 0.244 (6.20)
Pin 1 Index
Pin 1
0.014 (0.35)
0.019 (0.49)
0.188 (4.78)
0.197 (5.00)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.19)
0.010 (0.25)
0.050 (1.27)
0.010 (0.25)
X 45°
0.020 (0.50)
0.050"Typical
0.050"
Typical
0° - 8°
0.0075 (0.19)
0.010 (0.25)
0.250"
0.016 (0.410)
0.037 (0.937)
FOOTPRINT
0.030"
Typical
8 Places
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
8
FN8176.0
March 15, 2005
X9312
ORDERING INFORMATION
X9312X
X
X
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C
Package
P = 8-Lead Plastic DIP
S = 8-Lead SOIC
End to End Resistance
W=
10kΩ
Physical Characteristics
Marking Includes
Manufacturer’s Trademark
Resistance Value or Code
Date Code
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
9
FN8176.0
March 15, 2005
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