DATASHEET

DATASHEET
12-bit, +3.3V, 260+MSPS, High Speed D/A Converter
ISL5857
Features
The ISL5857 is a 12-bit, 260+MSPS (Mega Samples Per
Second), CMOS, high speed, low power, D/A (digital-to-analog)
converter designed specifically for use in high performance
communication systems such as base transceiver stations
utilizing 2.5G or 3G cellular protocols.
• Low power . . . . . . . . 103mW with 20mA output at 130MSPS
This device complements the ISL5x57 family of high speed
converters, which include 10, 12, and 14-bit devices.
• Excellent spurious free dynamic range
(73dBc to Nyquist, f S = 130MSPS, fOUT = 10MHz)
Applications
• UMTS adjacent channel power = 70dB at 19.2MHz
• Adjustable full scale output current. . . . . . . . . 2mA to 20mA
• +3.3V power supply
• 3V LVCMOS compatible inputs
• EDGE/GSM SFDR = 90dBc at 11MHz in 20MHz window
• Cellular Infrastructure - single or multicarrier: IS-136, IS-95,
GSM, EDGE, CDMA2000, WCDMA, TDS-CDMA
• Pin compatible, 3.3V, lower power replacement for the
AD9752 and HI5860
• BWA infrastructure
• Pb-free (RoHS compliant)
• Medical/test instrumentation
• Wireless communication systems
• High resolution imaging systems
• Arbitrary waveform generators
ISL5857
ONE CONNECTION
(25, 19) NC
D11
D11 (MSB) (1)
D10
D10 (2)
D9
D9 (3)
D8
D8 (4)
D7
D7 (5)
D6
D6 (6)
D5
D5 (7)
D4
D4 (8)
D3
D3 (9)
D2
D2 (10)
D1
D1 (11)
D0
D0 (LSB) (12)
(15) SLEEP
(16) REFLO
DCOM
(17) REFIO
0.1µF
(18) FSADJ
RSET
1:1, Z1:Z2
(22) IOUTA
(21) IOUTB
REPRESENTS
ANY 50Ω LOAD
(23) COMP
0.1µF
(20) ACOM
BEAD
+
10µF
10µH
DVDD (27)
1.91kΩ
(50Ω)
50Ω
CLK (28)
DCOM (26, 13, 14)
50Ω
ACOM
(24) AVDD
0.1µF
FERRITE
BEAD
+
10µH
0.1µF
10µF
+3.3V (VDD)
FIGURE 1. TYPICAL APPLICATIONS CIRCUIT
October 7, 2015
FN6079.3
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2004, 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL5857
Functional Block Diagram
IOUTA
IOUTB
CASCODE
(LSB) D0
D1
D2
CURRENT
SOURCE
INPUT
LATCH
D3
38
D4
D5
SWITCH
MATRIX
7 LSBs
38
+
31 MSB
SEGMENTS
D6
D7
D8
D9
D10
D11
UPPER
5-BIT
DECODER
COMP
CLK
INT/EXT
VOLTAGE
BIAS
GENERATION
REFERENCE
REFLO REFIO
FSADJ
SLEEP
FIGURE 2. FUNCTIONAL BLOCK DIAGRAM
Pin Configuration
ISL5857
28 LD SOIC/TSSOP
TOP VIEW
D11 (MSB) 1
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2
28 CLK
D10 2
27 DVDD
D9 3
26 DCOM
D8 4
25 NC
D7 5
24 AVDD
D6 6
23 COMP
D5 7
22 IOUTA
D4 8
21 IOUTB
D3 9
20 ACOM
D2 10
19 NC
D1 11
18 FSADJ
D0 (LSB) 12
17 REFIO
DCOM 13
16 REFLO
DCOM 14
15 SLEEP
FN6079.3
October 7, 2015
ISL5857
Pin Descriptions
PIN NO.
PIN NAME
DESCRIPTION
1 through 12
D11 (MSB) Through
D0 (LSB)
15
SLEEP
Control pin for power-down mode. Sleep Mode is active high; Connect to ground for Normal Mode. Sleep pin has
internal 20µA active pull-down current.
16
REFLO
Connect to analog ground to enable internal 1.2V reference or connect to AVDD to disable internal reference.
17
REFIO
Reference voltage input if internal reference is disabled. Reference voltage output if internal reference is enabled.
Use 0.1µF capacitor to ground when internal reference is enabled.
18
FSADJ
Full scale current adjust. Use a resistor to ground to adjust full scale output current. Full scale output current = 32
x VFSADJ/RSET.
19, 25
NC
21
IOUTB
The complementary current output of the device. Full scale output current is achieved when all input bits are set
to binary 0.
22
IOUTA
Current output of the device. Full scale output current is achieved when all input bits are set to binary 1.
23
COMP
Connect 0.1µF capacitor to ACOM.
24
AVDD
Analog supply (+3.0V to +3.6V).
20
ACOM
Connect to analog ground.
26, 13, 14
DCOM
Connect to digital ground.
27
DVDD
Digital supply (+3.0V to +3.6V).
28
CLK
Digital data Bit 11, (Most Significant Bit) through Digital Data Bit 0, (Least Significant Bit).
No Connect. These should be grounded, but can be left disconnected.
Clock input.
Ordering Information
PART NUMBER
(Notes 1, 2)
PART
MARKING
TEMP RANGE
(°C)
ISL5857IBZ No longer available
or supported, recommended
replacement part: ISL5857IAZ
ISL5857IBZ
-40 to +85
28 Ld SOIC
M28.3
260MHz
ISL5857IAZ
ISL 5857IAZ
-40 to +85
28 Ld TSSOP
M28.173
260MHz
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
CLOCK
SPEED
NOTES:
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. For Moisture Sensitivity Level (MSL), please see product information page for ISL5857. For more information on MSL, please see tech brief TB363.
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FN6079.3
October 7, 2015
ISL5857
Absolute Maximum Ratings
Thermal Information
Digital Supply Voltage DVDD to DCOM . . . . . . . . . . . . . . . . . . . . . . . . +3.6V
Analog Supply Voltage AVDD to ACOM. . . . . . . . . . . . . . . . . . . . . . . . . +3.6V
Grounds, ACOM TO DCOM . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
Digital Input Voltages (D9-D0, CLK, SLEEP) . . . . . . . . . . . . . . . DVDD + 0.3V
Reference Input Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . AVDD + 0.3V
Analog Output Current (IOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24mA
Thermal Resistance (Typical, Note 3)
JA(°C/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
110
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . . . -65°C to 150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTE:
3. JA is measured with the component mounted on an evaluation PC board in free air. See Tech Brief TB379.
Electrical Specifications AVDD = DVDD = +3.3V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = +25°C for all typical values. Boldface limits
apply across the operating temperature range, -40°C to +85°C.
TA = -40°C TO 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
12
-
-
Bits
-1.25
±0.5
+1.25
LSB
-1
±0.5
+1
LSB
+0.006
% FSR
SYSTEM PERFORMANCE
Resolution
Integral Linearity Error, INL
“Best fit” straight line (Note 10)
Differential Linearity Error, DNL
(Note 10)
Offset Error, IOS
IOUTA (Note 10)
Offset Drift Coefficient
(Note 10)
Full Scale Gain Error, FSE
Full Scale Gain Drift
-
0.1
-
ppm
FSR/°C
With external reference (Notes 4, 10)
-3
±0.5
+3
% FSR
With internal reference (Notes 4, 10)
-3
±0.5
+3
% FSR
With external reference (Note 10)
-
±50
-
ppm
FSR/°C
With internal reference (Note 10)
-
±100
-
ppm
FSR/°C
2
-
20
mA
-1.0
-
1.25
V
260
300
-
MHz
Full Scale Output Current, IFS
Output Voltage Compliance Range
-0.006
(Note 5)
DYNAMIC CHARACTERISTICS
Maximum Clock Rate, fCLK
Output Rise Time
Full scale step
-
1.5
-
ns
Output Fall Time
Full scale step
-
1.5
-
ns
-
10
-
pF
IOUTFS = 20mA
-
50
-
pA/Hz
IOUTFS = 2mA
-
30
-
pA/Hz
fCLK = 210MSPS, fOUT = 80.8MHz, 30MHz span (Notes 6, 10)
-
73
-
dBc
fCLK = 210MSPS, fOUT = 40.4MHz, 30MHz span (Notes 6, 10)
-
80
-
dBc
fCLK = 130MSPS, fOUT = 20.2MHz, 20MHz span (Notes 6, 10)
-
85
-
dBc
Output Capacitance
Output Noise
AC CHARACTERISTICS (Using Figure 15 with RDIFF = 50Ω and RLOAD = 50Ω, Full scale output = -2.5dBm
Spurious Free Dynamic Range,
SFDR Within a Window
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FN6079.3
October 7, 2015
ISL5857
Electrical Specifications AVDD = DVDD = +3.3V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = +25°C for all typical values. Boldface limits
apply across the operating temperature range, -40°C to +85°C. (Continued)
TA = -40°C TO 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
fCLK = 260MSPS, fOUT = 80.8MHz (Notes 6, 10)
-
47
-
dBc
fCLK = 260MSPS, fOUT = 40.4MHz (Notes 6, 10)
-
60
-
dBc
fCLK = 260MSPS, fOUT = 20.2MHz (Notes 6, 10)
-
62
-
dBc
fCLK = 210MSPS, fOUT = 80.8MHz (Notes 6, 10)
-
51
-
dBc
fCLK = 210MSPS, fOUT = 40.4MHz (Notes 6, 10, 12)
-
60
-
dBc
fCLK = 200MSPS, fOUT = 20.2MHz, T = 25°C (Notes 6, 10)
60
62
-
dBc
fCLK = 200MSPS, fOUT = 20.2MHz, T = -40°C to 85°C (Notes 6, 10)
58
-
-
dBc
fCLK = 130MSPS, fOUT = 50.5MHz (Notes 6, 10)
-
57
-
dBc
fCLK = 130MSPS, fOUT = 40.4MHz (Notes 6, 10)
-
62
-
dBc
fCLK = 130MSPS, fOUT = 20.2MHz (Notes 6, 10)
-
69
-
dBc
fCLK = 130MSPS, fOUT = 10.1MHz (Notes 6, 10)
-
73
-
dBc
fCLK = 130MSPS, fOUT = 5.05MHz, T = 25°C (Notes 6, 10)
70
77
-
dBc
fCLK = 130MSPS, fOUT = 5.05MHz, T = -40°C to 85°C (Notes 6, 10)
68
-
-
dBc
fCLK = 100MSPS, fOUT = 40.4MHz (Notes 6, 10)
-
60
-
dBc
fCLK = 80MSPS, fOUT = 30.3MHz (Notes 6, 10)
-
63
-
dBc
fCLK = 80MSPS, fOUT = 20.2MHz (Notes 6, 10)
-
69
-
dBc
fCLK = 80MSPS, fOUT = 10.1MHz (Notes 6, 10, 12)
-
70
-
dBc
fCLK = 80MSPS, fOUT = 5.05MHz (Notes 6, 10)
-
76
-
dBc
fCLK = 50MSPS, fOUT = 20.2MHz (Notes 6, 10)
-
68
-
dBc
fCLK = 50MSPS, fOUT = 10.1MHz (Notes 6, 10)
-
73
-
dBc
fCLK = 50MSPS, fOUT = 5.05MHz (Notes 6, 10)
-
77
-
dBc
fCLK = 210MSPS, fOUT = 28.3MHz to 45.2MHz, 2.1MHz spacing, 50MHz
Span (Notes 6, 10, 12)
-
65
-
dBc
fCLK = 130MSPS, fOUT = 17.5MHz to 27.9MHz, 1.3MHz spacing, 35MHz
Span (Notes 6, 10)
-
68
-
dBc
fCLK = 80MSPS, fOUT = 10.8MHz to 17.2MHz, 811kHz spacing, 15MHz
Span (Notes 6, 10)
-
75
-
dBc
fCLK = 50MSPS, fOUT = 6.7MHz to 10.8MHz, 490kHz spacing, 10MHz
Span (Notes 6, 10)
-
77
-
dBc
Spurious Free Dynamic Range,
SFDR in a Window with EDGE or GSM
fCLK = 78MSPS, fOUT = 11MHz, in a 20MHz window, RBW = 30kHz
(Notes 6, 10, 12)
-
90
-
dBc
Adjacent Channel Power Ratio,
ACPR with UMTS
fCLK = 76.8MSPS, fOUT = 19.2MHz, RBW = 30kHz (Notes 6, 10, 12)
-
70
-
dB
1.2
1.23
1.3
V
-
±40
-
ppm/°C
-
0
-
µA
-
1
-
MΩ
-
1.0
-
MHz
Spurious Free Dynamic Range,
SFDR to Nyquist (fCLK/2)
Spurious Free Dynamic Range,
SFDR in a Window with Eight Tones
VOLTAGE REFERENCE
Internal Reference Voltage, VFSADJ
Pin 18 voltage with internal reference
Internal Reference Voltage Drift
Internal Reference Output Current
Sink/Source Capability
Reference is not intended to be externally loaded
Reference Input Impedance
Reference Input Multiplying Bandwidth
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(Note 10)
FN6079.3
October 7, 2015
ISL5857
Electrical Specifications AVDD = DVDD = +3.3V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = +25°C for all typical values. Boldface limits
apply across the operating temperature range, -40°C to +85°C. (Continued)
TA = -40°C TO 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUTS D11-D0, CLK
Input Logic High Voltage with
3.3V Supply, VIH
(Note 5)
2.3
3.3
-
V
Input Logic Low Voltage with
3.3V Supply, VIL
(Note 5)
-
0
1.0
V
Sleep Input Current, IIH
-25
-
+25
µA
Input Logic Current, IIH, IIL
-20
-
+20
µA
Clock Input Current, IIH, IIL
-10
-
+10
µA
-
5
-
pF
Digital Input Capacitance, CIN
TIMING CHARACTERISTICS
Data Setup Time, tSU
See Figure 17
-
1.5
-
ns
Data Hold Time, tHLD
See Figure 17
-
1.5
-
ns
Propagation Delay Time, tPD
See Figure 17
-
1
-
Clock
Period
CLK Pulse Width, tPW1 , tPW2
See Figure 17 (Note 5)
0.9
-
-
ns
AVDD Power Supply
(Note 11)
2.7
3.3
3.6
V
DVDD Power Supply
(Note 11)
2.7
3.3
3.6
V
Analog Supply Current (IAVDD)
3.3V, IOUTFS = 20mA
-
27.5
28.5
mA
3.3V, IOUTFS = 2mA
-
10
-
mA
3.3V (Note 7)
-
3.7
5
mA
3.3V (Note 8)
-
6.5
8
mA
Supply Current (IAVDD) Sleep Mode
3.3V, IOUTFS = Don’t Care
-
1.5
-
mA
Power Dissipation
3.3V, IOUTFS = 20mA (Note 7)
-
103
111
mW
3.3V, IOUTFS = 20mA (Note 8)
-
110
120
mW
3.3V, IOUTFS = 20mA (Note 9)
-
157
-
mW
3.3V, IOUTFS = 2mA (Note 7)
-
45
-
mW
-0.125
-
+0.125
%FSR/V
POWER SUPPLY CHARACTERISTICS
Digital Supply Current (IDVDD)
Power Supply Rejection
Single supply (Note 10)
NOTES:
4. Gain Error measured as the error in the ratio between the full scale output current and the current through RSET (typically 625µA). Ideally the ratio
should be 32.
5. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
6. Spectral measurements made with differential transformer coupled output and no external filtering. For multitone testing, the same pattern was used
at different clock rates, producing different output frequencies but at the same ratio to the clock rate.
7. Measured with the clock at 130MSPS and the output frequency at 5MHz.
8. Measured with the clock at 200MSPS and the output frequency at 20MHz.
9. Measured with the clock at 260MSPS and the output frequency at 40MHz.
10. See “Definition of Specifications” on page 9.
11. Recommended operation is from 3.0V to 3.6V. Operation below 3.0V is possible with some degradation in spectral performance. Reduction in analog
output current may be necessary to maintain spectral performance.
12. See “Typical Performance Plots” on page 7.
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FN6079.3
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ISL5857
Typical Performance Plots
(+3.3V Supply, Using Figure 15 with RDIFF = 100Ω and RLOAD = 50Ω)
SPECTRAL MASK FOR
GSM900/DCS1800/PCS1900
P>43dBm NORMAL BTS
WITH 30kHz RBW
FIGURE 3. EDGE AT 11MHz, 78MSPS CLOCK
(91+dBc AT f = +6MHz)
FIGURE 4. EDGE AT 11MHz, 78MSPS CLOCK
(75dBc -NYQUIST, 6dB PAD)
SPECTRAL MASK FOR
GSM900/DCS1800/PCS1900
P>43dBm NORMAL BTS
WITH 30kHz RBW
FIGURE 5. GSM AT 11MHz, 78MSPS CLOCK
(90+dBc AT f = +6MHz, 3dB PAD)
FIGURE 6. GSM AT 11MHz, 78MSPS CLOCK
(75dBc - NYQUIST, 9dB PAD)
FIGURE 7. FOUR EDGE CARRIERS AT 12.4 to 15.6MHz, 800kHz
SPACING, 78MSPS (71dBc - 20MHz WINDOW)
FIGURE 8. FOUR GSM CARRIERS AT 12.4 to 15.6MHz, 78MSPS
(73dBc - 20MHz WINDOW, 6dB PAD)
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FN6079.3
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ISL5857
Typical Performance Plots
(+3.3V Supply, Using Figure 15 with RDIFF = 100Ω and RLOAD = 50Ω) (Continued)
SPECTRAL MASK
UMTS TDD
P>43dBm BTS
FIGURE 9. UMTS AT 19.2MHz, 76.8MSPS (70dB 1st ACPR, 70dB
2nd ACPR)
FIGURE 10. ONE TONE AT 10.1MHz, 80MSPS CLOCK
(71dBc - NYQUIST, 6dB PAD)
FIGURE 11. ONE TONE AT 40.4MHz, 210MSPS CLOCK
(61dBc - NYQUIST, 6dB PAD)
FIGURE 12. EIGHT TONES (CREST FACTOR = 8.9) AT 37MHz,
210MSPS CLOCK, 2.1MHz SPACING
(65dBc - NYQUIST)
FIGURE 13. TWO TONES (CF = 6) AT 8.5MHz, 50MSPS CLOCK,
500kHz SPACING (82dBc - 10MHz WINDOW, 6dB
PAD)
FIGURE 14. FOUR TONES (CF = 8.1) AT 14MHz, 80MSPS CLOCK,
800kHz SPACING (70dBc - NYQUIST, 6dB PAD)
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FN6079.3
October 7, 2015
ISL5857
Definition of Specifications
Adjacent Channel Power Ratio, ACPR, is the ratio of the
average power in the adjacent frequency channel (or offset) to
the average power in the transmitted frequency channel.
Differential Linearity Error, DNL, is the measure of the step size
output deviation from code to code. Ideally the step size should
be 1 LSB. A DNL specification of 1 LSB or less guarantees
monotonicity.
EDGE, Enhanced Data for Global Evolution, a TDMA standard
for cellular applications which uses 200kHz BW, 8-PSK
modulated carriers.
Full Scale Gain Drift, is measured by setting the data inputs to
be all logic high (all 1s) and measuring the output voltage
through a known resistance as the temperature is varied from
TMIN to TMAX . It is defined as the maximum deviation from the
value measured at room temperature to the value measured
at either TMIN or TMAX . The units are ppm of FSR (full scale
range) per °C.
Full Scale Gain Error, is the error from an ideal ratio of 32
between the output current and the full scale adjust current
(through RSET).
GSM, Global System for Mobile Communication, a TDMA
standard for cellular applications which uses 200kHz BW,
GMSK modulated carriers.
Integral Linearity Error, INL, is the measure of the worst case
point that deviates from a best fit straight line of data values
along the transfer curve.
Internal Reference Voltage Drift, is defined as the maximum
deviation from the value measured at room temperature to the
value measured at either TMIN or TMAX . The units are ppm
per °C.
Offset Drift, is measured by setting the data inputs to all logic
low (all 0s) and measuring the output voltage at IOUTA through
a known resistance as the temperature is varied from TMIN to
TMAX . It is defined as the maximum deviation from the value
measured at room temperature to the value measured at
either TMIN or TMAX . The units are ppm of FSR (full scale
range) per °C.
Offset Error, is measured by setting the data inputs to all logic
low (all 0s) and measuring the output voltage of IOUTA through
a known resistance. Offset error is defined as the maximum
deviation of the IOUTA output current from a value of 0mA.
Output Voltage Compliance Range, is the voltage limit
imposed on the output. The output impedance should be
chosen such that the voltage developed does not violate the
compliance range.
Power Supply Rejection, is measured using a single power
supply. The nominal supply voltage is varied ±10% and the
change in the DAC full scale output is noted.
Reference Input Multiplying Bandwidth, is defined as the 3dB
bandwidth of the voltage reference input. It is measured by
using a sinusoidal waveform as the external reference with the
digital inputs set to all 1s. The frequency is increased until the
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amplitude of the output waveform is 0.707 (-3dB) of its
original value.
Spurious Free Dynamic Range, SFDR, is the amplitude
difference from the fundamental signal to the largest
harmonically or non-harmonically related spur within the
specified frequency window.
Total Harmonic Distortion, THD, is the ratio of the RMS value of
the fundamental output signal to the RMS sum of the first five
harmonic components.
UMTS, Universal Mobile Telecommunications System, a
W-CDMA standard for cellular applications which uses
3.84MHz modulated carriers.
Detailed Description
The ISL5857 is a 12-bit, current out, CMOS, digital to analog
converter. The maximum update rate is at least 260+MSPS
and can be powered by a single power supply in the
recommended range of +3.0V to +3.6V. It consumes less than
120mW of power when using a +3.3V supply, the maximum
20mA of output current, and the data switching at 210MSPS.
The architecture is based on a segmented current source
arrangement that reduces glitch by reducing the amount of
current switching at any one time. In previous architectures
that contained all binary weighted current sources or a binary
weighted resistor ladder, the converter might have a
substantially larger amount of current turning on and off at
certain worst-case transition points, such as midscale and
quarter scale transitions. By greatly reducing the amount of
current switching at these major transitions, the overall glitch
of the converter is dramatically reduced, improving settling
time, transient problems and accuracy.
Digital Inputs and Termination
The ISL5857 digital inputs are guaranteed to 3V LVCMOS
levels. The internal register is updated on the rising edge of the
clock. To minimize reflections, proper termination should be
implemented. If the lines driving the clock and the digital
inputs are long 50Ω lines, then 50Ω termination resistors
should be placed as close to the converter inputs as possible
connected to the digital ground plane (if separate grounds are
used). These termination resistors are not likely needed as
long as the digital waveform source is within a few inches of
the DAC. For pattern drivers with very high speed edge rates, it
is recommended that the user consider series termination
(50Ω to 200Ωprior to the DAC’s inputs in order to reduce the
amount of noise.
Power Supply
Separate digital and analog power supplies are recommended.
The allowable supply range is +2.7V to +3.6V. The
recommended supply range is +3.0V to 3.6V (nominally +3.3V)
to maintain optimum SFDR. However, operation down to +2.7V
is possible with some degradation in SFDR. Reducing the
analog output current can help the SFDR at +2.7V. The SFDR
values stated in the table of specifications were obtained with
a +3.3V supply.
FN6079.3
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ISL5857
Ground Planes
Separate digital and analog ground planes should be used. All
of the digital functions of the device and their corresponding
components should be located over the digital ground plane
and terminated to the digital ground plane. The same is true
for the analog components and the analog ground plane.
Noise Reduction
To minimize power supply noise, 0.1µF capacitors should be
placed as close as possible to the converter’s power supply
pins, AVDD and DVDD . Also, the layout should be designed
using separate digital and analog ground planes and these
capacitors should be terminated to the digital ground for DVDD
and to the analog ground for AVDD . Additional filtering of the
power supplies on the board is recommended.
Voltage Reference
The internal voltage reference of the device has a nominal value
of +1.23V with a ±40ppm/°C drift coefficient over the full
temperature range of the converter. It is recommended that a
0.1µF capacitor be placed as close as possible to the REFIO
pin, connected to the analog ground. The REFLO pin (16)
selects the reference. The internal reference can be selected if
pin 16 is tied low (ground). If an external reference is desired,
then pin 16 should be tied high (the analog supply voltage) and
the external reference driven into REFIO, pin 17. The full scale
output current of the converter is a function of the voltage
reference used and the value of RSET . IOUT should be within
the 2mA to 20mA range, though operation below 2mA is
possible with performance degradation.
If the internal reference is used, VFSADJ will equal
approximately 1.2V (pin 18). If an external reference is used,
VFSADJ will equal the external reference. The calculation for
IOUT (Full Scale) is:
should be chosen so that the desired output voltage is
produced in conjunction with the output full scale current. If a
known line impedance is to be driven, then the output load
resistor should be chosen to match this impedance. The output
voltage equation is:
VOUT = IOUT x ROUT.
The most effective method for reducing the power
consumption is to reduce the analog output current, which
dominates the supply current. The maximum recommended
output current is 20mA.
Differential Output
IOUTA and IOUTB can be used in a differential-to-single-ended
arrangement to achieve better harmonic rejection. With
RDIFF = 50Ωand RLOAD = 50Ω, the circuit in Figure 15 will
provide a 500mV signal at the output of the transformer if the
full scale output current of the DAC is set to 20mA (used for
the electrical specifications table). Values of RDIFF = 100Ωand
RLOAD = 50Ω were used for the typical performance curves.
The center tap in Figure 15 must be grounded.
In the circuit in Figure 16, the user is left with the option to
ground or float the center tap. The DC voltage that will exist at
either IOUTA or IOUTB if the center tap is floating is IOUTDC x
(RA//RB) V because RDIFF is DC shorted by the transformer. If
the center tap is grounded, the DC voltage is 0V.
Recommended values for the circuit in Figure 16 are
RA = RB = 50Ω, RDIFF = 100Ω, assuming RLOAD = 50Ω. The
performance of Figures 15 and 16 is basically the same,
however leaving the center tap of Figure 16 floating allows the
circuit to find a more balanced virtual ground, theoretically
improving the even order harmonic rejection, but likely
reducing the signal swing available due to the output voltage
compliance range limitations.
IOUT(Full Scale) = (VFSADJ/RSET) x 32
If the full scale output current is set to 20mA by using the
internal voltage reference (1.2V) and a 1.91kΩ RSET resistor,
then the input coding to output current will resemble the
following:
TABLE 1. INPUT CODING vs OUTPUT CURRENT WITH INTERNAL
REFERENCE AND RSET = 1.91kΩ
INPUT CODE (D11-D0)
IOUTA (mA)
IOUTB (mA)
11 11111 11111
20
0
10 00000 00000
10
10
00 00000 00000
0
20
Analog Output
IOUTA and IOUTB are complementary current outputs. The sum
of the two currents is always equal to the full scale output
current minus one LSB. If single-ended use is desired, a load
resistor can be used to convert the output current to a voltage.
It is recommended that the unused output be either grounded
or equally terminated. The voltage developed at the output
must not violate the output voltage compliance range of -1.0V
to 1.25V. ROUT (the impedance loading each current output)
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FN6079.3
October 7, 2015
ISL5857
Propagation Delay
REQ = 0.5 x (RLOAD//RDIFF)
AT EACH OUTPUT
PIN 21
PIN 22
ISL5857
The converter requires two clock rising edges for data to be
represented at the output. Each rising edge of the clock
captures the present data word and outputs the previous data.
The propagation delay is therefore 1/CLK, plus <2ns of
processing. See Figure 17.
VOUT = (2 x IOUTA x REQ)V
1:1
IOUTB
RDIFF
RLOAD
IOUTA
Test Service
RLOAD REPRESENTS THE
LOAD SEEN BY THE TRANSFORMER
FIGURE 15. OUTPUT LOADING FOR DATASHEET MEASUREMENTS
Intersil offers customer-specific testing of converters with a
service called Testdrive. To submit a request, fill out the
Testdrive form. The form can be found by doing an ‘entire site
search’ at www.intersil.com on the words ‘DAC Testdrive’. Or,
send a request to the technical support center.
REQ = 0.5 x (RLOAD//RDIFF//RA), WHERE RA = RB
AT EACH OUTPUT
RA
PIN 21
PIN 22
ISL5857
IOUTB
VOUT = (2 x IOUTA x REQ)V
RDIFF
IOUTA
RLOAD
RB
RLOAD REPRESENTS THE
LOAD SEEN BY THE TRANSFORMER
FIGURE 16. ALTERNATIVE OUTPUT LOADING
Timing Diagram
tPW2
tPW1
50%
CLK
tSU
tSU
tHLD
D11-D0
W0
tSU
tHLD
tHLD
W1
W2
W3
tPD
tPD
OUTPUT = W0
IOUT
OUTPUT = W-1
OUTPUT = W1
FIGURE 17. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM
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FN6079.3
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ISL5857
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE
REVISION
CHANGE
October 7, 2015
FN6079.3
Updated Ordering Information on page 3.
May 14, 2015
FN6079.2
Updated entire datasheet applying Intersil’s new standards.
Moved the Typical Application Circuit to page 1, Pin Configuration to page 2, and Ordering Information Table to
page 3.
Removed obsolete products from the ordering information table on page 3.
Added Notes 2 and 3 to the Ordering Information Table.
Added the Part Marking column to the Ordering Information Table.
Removed (-2.5dBm) from the following sentence under “Differential Output” on page 10: “With RDIFF = 50Ω and
RLOAD = 50Ω, the circuit in Figure 13 will provide a 500mV (-2.5dBm) signal at the output of the transformer if the
full scale output current of the DAC is set to 20mA (used for the electrical specifications table).”
Added Revision History and About Intersil Verbiage
Updated POD M28.3 to latest revision.
-Change made from Rev 0 to Rev 1 was adding land pattern
Updated POD M28.173 to latest revision.
-Changes made from Rev 0 to Rev 1 was converting to new POD format by moving dimensions from table onto
drawing and adding land pattern. No dimension changes.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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FN6079.3
October 7, 2015
ISL5857
Small Outline Plastic Packages (SOIC)
M28.3 (JEDEC MS-013-AE ISSUE C)
N
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
H
0.25(0.010) M
B M
INCHES
E
SYMBOL
-B-
1
2
3
L
SEATING PLANE
-A-
A
D
h x 45o
a
e
A1
B
C
0.10(0.004)
0.25(0.010) M
C A M
B S
MAX
MILLIMETERS
MIN
MAX
NOTES
A
0.0926
0.1043
2.35
2.65
-
A1
0.0040
0.0118
0.10
0.30
-
B
0.013
0.0200
0.33
0.51
9
C
0.0091
0.0125
0.23
0.32
-
D
0.6969
0.7125
17.70
18.10
3
E
0.2914
0.2992
7.40
7.60
4
e
-C-
MIN
0.05 BSC
h
0.01
0.029
0.25
0.75
5
L
0.016
0.050
0.40
1.27
6

10.00
-
0.394
N
0.419
1.27 BSC
H
28
0o
10.65
-
28
8o
0o
7
8o
Rev. 1, 1/13
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
TYPICAL RECOMMENDED LAND PATTERN
(1.50mm)
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
(9.38mm)
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch)
(1.27mm TYP)
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(0.51mm TYP)
13
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
FN6079.3
October 7, 2015
ISL5857
Package Outline Drawing
M28.173
28 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Rev 1, 5/10
A
9.70± 0.10
1
3
SEE DETAIL "X"
15
28
6.40
PIN #1
I.D. MARK
4.40 ± 0.10
2
3
0.20 C B A
1
14
0.15 +0.05
-0.06
B
0.65
TOP VIEW
END VIEW
1.00 REF
H
- 0.05
0.90 +0.15
-0.10
C
GAUGE
PLANE
1.20 MAX
SEATING PLANE
+0.05
0.25
5
-0.06
0.10 M C B A
0.10 C
0.25
0°-8°
0.05 MIN
0.15 MAX
0.60 ±0.15
SIDE VIEW
DETAIL "X"
(1.45)
NOTES:
1. Dimension does not include mold flash, protrusions or gate burrs.
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
(5.65)
2. Dimension does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.25 per side.
3. Dimensions are measured at datum plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Dimension does not include dambar protrusion. Allowable protrusion
shall be 0.08mm total in excess of dimension at maximum material
condition. Minimum space between protrusion and adjacent lead
(0.35 TYP)
(0.65 TYP)
TYPICAL RECOMMENDED LAND PATTERN
is 0.07mm.
6. Dimension in ( ) are for reference only.
7. Conforms to JEDEC MO-153.
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FN6079.3
October 7, 2015
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