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conData
February 2002
ERS
TSheet
8
1-8 8-IN
Dual 14-Bit, +3.3V, 130/210+MSPS, High
Speed D/A Converter
• Speed Grades . . . . . . . . . . . . . . . . 130M and 210+MSPS
This device complements the ISL5x61 and ISL5x29 families
of high speed converters, which include 8-, 10-, 12-, and 14bit devices.
Ordering Information
PACKAGE
ISL5929IN
-40 to 85
48 Ld LQFP
Q48.7x7A 130MHz
ISL5929/2IN
-40 to 85
48 Ld LQFP
Q48.7x7A 210MHz
25
PKG.
DWG. #
CLOCK
SPEED
Evaluation Platform
210MHz
• +3.3V Power Supply
• 3V LVCMOS Compatible Inputs
• Excellent Spurious Free Dynamic Range
(75dBc to Nyquist, f S = 130MSPS, fOUT = 10MHz)
• EDGE/GSM SFDR = 94dBc at 11MHz in 20MHz Window
• Dual, 3.3V, Lower Power Replacement for AD9767
Applications
• Cellular Infrastructure - Single or Multi-Carrier: IS-136,
IS-95, GSM, EDGE, CDMA2000, WCDMA, TDS-CDMA
• Medical/Test Instrumentation and Equipment
QD5
QD2
• Wireless Communication Systems
ID7
1
48 47 46 45 44 43 42 41 40 39 38 37
36
QD6
ID6
2
35
QD7
ID5
ID4
3
34
QD8
4
33
ID3
5
32
ID2
31
ID1
6
7
QD9
QD10
QD11
30
QD12
(LSB) ID0
8
29
9
28
QD13 (MSB)
CLK
10
27
DGND
11
12
26
AGND
NC
QCOMP
AVDD
QOUTB
QOUTA
AGND
FSADJ
REFIO
1
REFLO
IOUTA
IOUTB
NC
25
13 14 15 16 17 18 19 20 21 22 23 24
AVDD
ICOMP
• Guaranteed Gain Matching < 0.14dB
• Quadrature Transmit with IF Range 0–80MHz
QD3
QD4
QD0 (LSB)
QD1
ID13(MSB)
ID10
ID11
ID12
ID9
ID8
ISL5929
(LQFP)
TOP VIEW
AGND
• Adjustable Full Scale Output Current . . . . . 2mA to 20mA
• BWA Infrastructure
Pinout
SLEEP
DVDD
• Low Power . . . . . 233mW with 20mA Output at 130MSPS
• UMTS Adjacent Channel Power = 71dB at 19.2MHz
TEMP.
RANGE
(oC)
ISL5929EVAL1
FN6021.1
Features
The ISL5929 is a dual 14-bit, 130/210+MSPS (Mega
Samples Per Second), CMOS, high speed, low power, D/A
(digital to analog) converter, designed specifically for use in
high performance communication systems such as base
transceiver stations utilizing 2.5G or 3G cellular protocols.
PART
NUMBER
ISL5929
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
ISL5929
ID8
ID9
ID10
ID11
ID12
ID13 (MSB)
QD0 (LSB)
QD1
QD2
QD3
QD4
QD5
Typical Applications Circuit
SLEEP
DVPP
C1
0.1F
ICOMP
C2
0.1F
AVPP
48 47 46 45 44 43 42 41 40 39 38 37
36
1
35
2
34
3
33
4
32
5
31
6
30
7
29
8
CLK 28
9
DGND 27
10 DVDD
AGND 26
11 AGND
25
12
13 14 15 16 17 18 19 20 21 22 23 24
REFIO
REFLO
AGND
FSADJ
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0 (LSB)
AVDD
AVDD
C4
0.1F
QD6
QD7
QD8
QD9
QD10
QD11
QD12
QD13 (MSB)
R1
50
QCOMP
C3
0.1F
AVPP
C5
0.1F
C6
0.1F
RSET
1.91k
50
R3
R2
50
1:1 TRANSFORMER
(50)
REPRESENTS
ANY 50 LOAD
(50)
QOUT
IOUT
BEAD
FERRITE
+ C11
10F
L1
10H
C9
0.1F
C10
1F
C12
0.1F
C13
1F
DVPP (DIGITAL POWER PLANE) = +3.3V
+3.3V POWER SOURCE
FERRITE
BEAD
+C
14
10F
2
L2
10H
AVPP (ANALOG POWER PLANE) = +3.3V
ISL5929
Functional Block Diagram
(LSB) QD0
QOUTA
QD1
QOUTB
QD2
QD3
QD4
INPUT
LATCH
CASCODE
QD5
40
QD6
SWITCH
MATRIX
40
CURRENT
SOURCE
QD7
QD8
9 LSBs
QD9
QD10
QD11
QD12
+
31 MSB
SEGMENTS
UPPER
5-BIT
DECODER
(MSB) QD13
QCOMP
SLEEP
INT/EXT
VOLTAGE
CLK
BIAS
GENERATION
REFERENCE
FSADJ
REFIO
REFLO
ICOMP
(LSB) ID0
ID1
IOUTA
ID2
ID3
ID4
IOUTB
INPUT
LATCH
CASCODE
ID5
40
ID6
SWITCH
MATRIX
40
CURRENT
SOURCE
ID7
ID8
9 LSBs
ID9
ID10
ID11
ID12
(MSB) ID13
3
UPPER
5-BIT
DECODER
+
31 MSB
SEGMENTS
ISL5929
Pin Descriptions
PIN NO.
PIN NAME
11, 19, 26
AGND
Analog ground.
13, 24
AVDD
Analog supply (+2.7V to +3.6V).
28
CLK
Clock Iinput.
27
DGND
Connect to digital ground.
10
DVDD
Digital supply (+2.7V to +3.6V).
20
FSADJ
Full scale current adjust. Use a resistor to ground to adjust full scale output current. Full scale output
current = 32 x VFSADJ/RSET.
14, 23
NC
12, 25
ICOMP, QCOMP
1-8, 29-48
PIN DESCRIPTION
Not internally connected. Recommend no connect.
Compensation pin for internal bias generation. Each pin should be individually decoupled to AGND with
a 0.1F capacitor.
ID13-ID0, QD13-QD0 Digital data input ports. Bit 13 is most significant bit (MSB) and bit 0 is the least significant bit (LSB).
15, 22
IOUTA, QOUTA
Current outputs of the device. Full scale output current is achieved when all input bits are set to binary 1.
16, 21
IOUTB, QOUTB
Complementary current outputs of the device. Full scale output current is achieved on the complementary
outputs when all input bits are set to binary 0.
17
REFIO
Reference voltage input if Internal reference is disabled. The internal reference is not intended to drive an
external load. Use 0.1F cap to ground when internal reference is enabled.
18
REFLO
Connect to analog ground to enable internal 1.2V reference or connect to AVDD to disable internal reference.
9
SLEEP
Connect to digital ground or leave floating for normal operation. Connect to DVDD for sleep mode.
4
ISL5929
Absolute Maximum Ratings
Thermal Information
Digital Supply Voltage DVDD to DGND . . . . . . . . . . . . . . . . . . +3.6V
Analog Supply Voltage AVDD to AGND . . . . . . . . . . . . . . . . . . +3.6V
Grounds, AGND TO DGND . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
Digital Input Voltages (DATA, CLK, SLEEP) . . . . . . . . DVDD + 0.3V
Reference Input Voltage Range. . . . . . . . . . . . . . . . . . AVDD + 0.3V
Analog Output Current (IOUT) . . . . . . . . . . . . . . . . . . . . . . . . . 24mA
Thermal Resistance (Typical, Note 1)
JA(°C/W)
LQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
AVDD = DVDD = +3.3V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25°C for All Typical Values
TA = -40°C TO 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
14
-
-
Bits
SYSTEM PERFORMANCE
Resolution
Integral Linearity Error, INL
“Best Fit” Straight Line (Note 7)
-5
2.5
+5
LSB
Differential Linearity Error, DNL
(Note 7)
-3
1.5
+3
LSB
Offset Error, IOS
IOUTA (Note 7)
+0.006
% FSR
Offset Drift Coefficient
(Note 7)
-
0.1
-
ppm
FSR/°C
Full Scale Gain Error, FSE
With External Reference (Notes 2, 7)
-3
0.5
+3
% FSR
With Internal Reference (Notes 2, 7)
-3
0.5
+3
% FSR
With External Reference (Note 7)
-
50
-
ppm
FSR/°C
With Internal Reference (Note 7)
-
100
-
ppm
FSR/°C
fCLK = 100MSPS, fOUT = 10MHz
-
83
-
dB
Full Scale Gain Drift
Crosstalk
fCLK = 100MSPS, fOUT = 40MHz
-0.006
-
74
-
dB
As a percentage of Full Scale Range
-1.6
0.6
+1.6
% FSR
In dB Full Scale Range
-0.14
0.05
+0.14
dB FSR
2
20
22
mA
(Note 3)
-1.0
-
1.25
V
Maximum Clock Rate, fCLK
ISL5929/2IN
210
250
-
MHz
Maximum Clock Rate, fCLK
ISL5929IN
130
150
-
MHz
Gain Matching Between Channels
(DC Measurement)
Full Scale Output Current, IFS
Output Voltage Compliance Range
DYNAMIC CHARACTERISTICS
Output Rise Time
Full Scale Step
-
1
-
ns
Output Fall Time
Full Scale Step
-
1
-
ns
-
5
-
pF
IOUTFS = 20mA
-
50
-
pA/Hz
IOUTFS = 2mA
-
30
-
pA/Hz
Output Capacitance
Output Noise
5
ISL5929
Electrical Specifications
AVDD = DVDD = +3.3V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25°C for All Typical Values (Continued)
TA = -40°C TO 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
AC CHARACTERISTICS (Using Figure 13 with RDIFF = 50 and RLOAD = 50, Full Scale Output = -2.5dBm
Spurious Free Dynamic Range,
SFDR Within a Window
Spurious Free Dynamic Range,
SFDR to Nyquist (fCLK/2)
fCLK = 210MSPS, fOUT = 80.8MHz, 30MHz Span (Notes 4, 7)
-
73
-
dBc
fCLK = 210MSPS, fOUT = 40.4MHz, 30MHz Span (Notes 4, 7)
-
80
-
dBc
fCLK = 130MSPS, fOUT = 20.2MHz, 20MHz Span (Notes 4, 7)
-
86
-
dBc
fCLK = 210MSPS, fOUT = 80.8MHz (Notes 4, 7)
-
56
-
dBc
fCLK = 210MSPS, fOUT = 40.4MHz (Notes 4, 7, 9)
-
67
-
dBc
fCLK = 200MSPS, fOUT = 20.2MHz, T = 25°C (Notes 4, 7)
62
68
-
dBc
fCLK = 200MSPS, fOUT = 20.2MHz, T = -40°C to 85°C (Notes 4, 7)
60
-
-
dBc
fCLK = 130MSPS, fOUT = 50.5MHz (Notes 4, 7)
-
59
-
dBc
fCLK = 130MSPS, fOUT = 40.4MHz (Notes 4, 7)
-
63
-
dBc
fCLK = 130MSPS, fOUT = 20.2MHz (Notes 4, 7)
-
70
-
dBc
70
75
-
dBc
fCLK = 130MSPS, fOUT = 5.05MHz, (Notes 4, 7)
-
79
-
dBc
fCLK = 100MSPS, fOUT = 40.4MHz (Notes 4, 7)
-
61
-
dBc
fCLK = 80MSPS, fOUT = 30.3MHz (Notes 4, 7)
-
64
-
dBc
fCLK = 130MSPS, fOUT = 10.1MHz , T = -40°C to 85°C (Notes 4, 7)
fCLK = 80MSPS, fOUT = 20.2MHz (Notes 4, 7)
-
71
-
dBc
fCLK = 80MSPS, fOUT = 10.1MHz (Notes 4, 7, 9)
-
75
-
dBc
fCLK = 80MSPS, fOUT = 5.05MHz (Notes 4, 7)
-
78
-
dBc
fCLK = 50MSPS, fOUT = 20.2MHz (Notes 4, 7)
-
68
-
dBc
fCLK = 50MSPS, fOUT = 10.1MHz (Notes 4, 7)
-
75
-
dBc
fCLK = 50MSPS, fOUT = 5.05MHz (Notes 4, 7)
-
79
-
dBc
fCLK = 210MSPS, fOUT = 28.3MHz to 45.2MHz, 2.1MHz Spacing,
50MHz Span (Notes 4, 7, 9)
-
65
-
dBc
fCLK = 130MSPS, fOUT =17.5MHz to 27.9MHz, 1.3MHz Spacing,
35MHz Span (Notes 4, 7)
-
69
-
dBc
fCLK = 80MSPS, fOUT = 10.8MHz to 17.2MHz, 811kHz Spacing,
15MHz Span (Notes 4, 7)
-
76
-
dBc
fCLK = 50MSPS, fOUT = 6.7MHz to 10.8MHz, 490kHz Spacing,
10MHz Span (Notes 4, 7)
-
77
-
dBc
-
94
-
dBc
-
71
-
dB
1.2
1.23
1.3
V
-
40
-
ppm/°C
-
0
-
A
Reference Input Impedance
-
1
-
M
Reference Input Multiplying Bandwidth (Note 7)
-
1.0
-
MHz
2.3
3.3
-
V
Spurious Free Dynamic Range,
SFDR in a Window with Eight Tones
Spurious Free Dynamic Range,
fCLK = 78MSPS, fOUT = 11MHz, in a 20MHz Window, RBW=30kHz
SFDR in a Window with EDGE or GSM (Notes 4, 7, 9)
fCLK = 76.8MSPS, fOUT = 19.2MHz, RBW=30kHz (Notes 4, 7, 9)
Adjacent Channel Power Ratio,
ACPR with UMTS
VOLTAGE REFERENCE
Internal Reference Voltage, VFSADJ
Pin 20 Voltage with Internal Reference
Internal Reference Voltage Drift
Internal Reference Output Current
Sink/Source Capability
DIGITAL INPUTS
Reference is not intended to drive an external load
D13-D0, CLK
(Note 3)
Input Logic High Voltage with
3.3V Supply, VIH
6
ISL5929
AVDD = DVDD = +3.3V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25°C for All Typical Values (Continued)
Electrical Specifications
TA = -40°C TO 85°C
MIN
TYP
MAX
UNITS
-
0
1.0
V
Sleep Input Current, IIH
-25
-
+25
A
Input Logic Current, IIH, IL
-20
-
+20
A
Clock Input Current, IIH, IL
-10
-
+10
A
-
3
-
pF
PARAMETER
TEST CONDITIONS
Input Logic Low Voltage with
3.3V Supply, VIL
(Note 3)
Digital Input Capacitance, CIN
TIMING CHARACTERISTICS
Data Setup Time, tSU
See Figure 15
-
1.5
-
ns
Data Hold Time, tHLD
See Figure 15
-
1.5
-
ns
Propagation Delay Time, tPD
See Figure 15
-
1
-
Clock
Period
CLK Pulse Width, tPW1 , tPW2
See Figure 15 (Note 3)
2
-
-
ns
POWER SUPPLY CHARACTERISTICS
AVDD Power Supply
(Note 8)
2.7
3.3
3.6
V
DVDD Power Supply
(Note 8)
2.7
3.3
3.6
V
Analog Supply Current (IAVDD)
3.3V, IOUTFS = 20mA
-
60
62
mA
3.3V, IOUTFS = 2mA
-
24
-
mA
Digital Supply Current (IDVDD)
3.3V (Note 5)
-
11
15
mA
3.3V (Note 6)
-
17
21
mA
Supply Current (IAVDD) Sleep Mode
3.3V, IOUTFS = Don’t Care
-
5
-
mA
Power Dissipation
3.3V, IOUTFS = 20mA (Note 5)
-
233
255
mW
3.3V, IOUTFS = 20mA (Note 6)
-
253
274
mW
3.3V, IOUTFS = 2mA (Note 5)
-
115
-
mW
-0.125
-
+0.125
%FSR/V
Power Supply Rejection
Single Supply (Note 7)
NOTES:
2. Gain Error measured as the error in the ratio between the full scale output current and the current through RSET (typically 625A). Ideally the
ratio should be 32.
3. Parameter guaranteed by design or characterization and not production tested.
4. Spectral measurements made with differential transformer coupled output and no external filtering. For multitone testing, the same pattern was
used at different clock rates, producing different output frequencies but at the same ratio to the clock rate.
5. Measured with the clock at 130MSPS and the output frequency at 10MHz.
6. Measured with the clock at 200MSPS and the output frequency at 20MHz.
7. See “Definition of Specifications.”
8. Recommended operation is from 3.0V to 3.6V. Operation below 3.0V is possible with some degradation in spectral performance. Reduction in
analog output current may be necessary to maintain spectral performance.
9. See Typical Performance Plots.
7
ISL5929
Typical Performance (+3.3V Supply, Using Figure 13 with RDIFF = 100 and RLOAD = 50)
SPECTRAL MASK FOR
GSM900/DCS1800/PCS1900
P>43dBm NORMAL BTS
WITH 30kHz RBW
FIGURE 1. EDGE AT 11MHz, 78MSPS CLOCK
(94+dBc @ f = +6MHz)
FIGURE 2. EDGE AT 11MHz, 78MSPS CLOCK
(77dBc -NYQUIST, 6dB PAD)
SPECTRAL MASK FOR
GSM900/DCS1800/PCS1900
P>43dBm NORMAL BTS
WITH 30kHz RBW
FIGURE 3. GSM AT 11MHz, 78MSPS CLOCK
(94+dBc @ f = +6MHz, 3dB PAD)
FIGURE 4. GSM AT 11MHz, 78MSPS CLOCK
(79dBc - NYQUIST, 9dB PAD)
FIGURE 5. FOUR EDGE CARRIERS AT 12.4–15.6MHz,
800kHz SPACING, 78MSPS (75+dBc - 20MHz
WINDOW)
FIGURE 6. FOUR GSM CARRIERS AT 12.4–15.6MHz,
78MSPS (75+dBc - 20MHz WINDOW, 6dB PAD)
8
ISL5929
Typical Performance (+3.3V Supply, Using Figure 13 with RDIFF = 100 and RLOAD = 50)
(Continued)
SPECTRAL MASK
UMTS TDD
P>43dBm BTS
FIGURE 7. UMTS AT 19.2MHz, 76.8MSPS (71dB 1stACPR,
75dB 2ndACPR)
FIGURE 9. ONE TONE AT 40.4MHz, 210MSPS CLOCK
(61dBc - NYQUIST, 6dB PAD)
FIGURE 11. TWO TONES (CF=6) AT 8.5MHz, 50MSPS CLOCK,
500kHz SPACING (83dBc - 10MHz WINDOW,
6dB PAD)
9
FIGURE 8. ONE TONE AT 10.1MHz, 80MSPS CLOCK
(71dBc - NYQUIST, 6dB PAD)
FIGURE 10. EIGHT TONES (CREST FACTOR=8.9) AT 37MHz,
210MSPS CLOCK, 2.1MHz SPACING
(65dBc - NYQUIST)
FIGURE 12. FOUR TONES (CF=8.1) AT 14MHz, 80MSPS
CLOCK, 800kHz SPACING (70dBc - NYQUIST,
6dB PAD)
ISL5929
Definition of Specifications
Adjacent Channel Power Ratio, ACPR, is the ratio of the
average power in the adjacent frequency channel (or offset)
to the average power in the transmitted frequency channel.
Crosstalk, is the measure of the channel isolation from one
DAC to the other. It is measured by generating a sinewave in
one DAC while the other DAC is clocked with a static input,
and comparing the output power of each DAC at the
frequency generated.
Differential Linearity Error, DNL, is the measure of the
step size output deviation from code to code. Ideally the step
size should be one LSB. A DNL specification of one LSB or
less guarantees monotonicity.
EDGE, Enhanced Data for Global Evolution, a TDMA
standard for cellular applications which uses 200kHz BW,
8-PSK modulated carriers.
Full Scale Gain Drift, is measured by setting the data inputs
to be all logic high (all 1s) and measuring the output voltage
through a known resistance as the temperature is varied
from TMIN to TMAX . It is defined as the maximum deviation
from the value measured at room temperature to the value
measured at either TMIN or TMAX . The units are ppm of FSR
(full scale range) per °C.
Full Scale Gain Error, is the error from an ideal ratio of 32
between the output current and the full scale adjust current
(through RSET).
Gain Matching, is a measure of the full scale amplitude
match between the I and Q channels given the same input
pattern. It is typically measured with all 1s at the input to both
channels, and the full scale output voltage developed into
matching loads is compared for the I and Q outputs.
GSM, Global System for Mobile Communication, a TDMA
standard for cellular applications which uses 200kHz BW,
GMSK modulated carriers.
Integral Linearity Error, INL, is the measure of the worst
case point that deviates from a best fit straight line of data
values along the transfer curve.
Internal Reference Voltage Drift, is defined as the
maximum deviation from the value measured at room
temperature to the value measured at either TMIN or TMAX .
The units are ppm per °C.
Offset Drift, is measured by setting the data inputs to all
logic low (all 0s) and measuring the output voltage at IOUTA
through a known resistance as the temperature is varied
from TMIN to TMAX . It is defined as the maximum deviation
from the value measured at room temperature to the value
measured at either TMIN or TMAX . The units are ppm of FSR
(full scale range) per degree °C.
Offset Error, is measured by setting the data inputs to all
logic low (all 0s) and measuring the output voltage of IOUTA
10
through a known resistance. Offset error is defined as the
maximum deviation of the IOUTA output current from a value
of 0mA.
Output Voltage Compliance Range, is the voltage limit
imposed on the output. The output impedance should be
chosen such that the voltage developed does not violate the
compliance range.
Power Supply Rejection, is measured using a single power
supply. The nominal supply voltage is varied 10% and the
change in the DAC full scale output is noted.
Reference Input Multiplying Bandwidth, is defined as the
3dB bandwidth of the voltage reference input. It is measured
by using a sinusoidal waveform as the external reference
with the digital inputs set to all 1s. The frequency is
increased until the amplitude of the output waveform is
0.707 (-3dB) of its original value.
Spurious Free Dynamic Range, SFDR, is the amplitude
difference from the fundamental signal to the largest
harmonically or non-harmonically related spur within the
specified frequency window.
Total Harmonic Distortion, THD, is the ratio of the RMS
value of the fundamental output signal to the RMS sum of
the first five harmonic components.
UMTS, Universal Mobile Telecommunications System, a
W-CDMA standard for cellular applications which uses
3.84MHz modulated carriers.
Detailed Description
The ISL5929 is a dual 14-bit, current out, CMOS, digital to
analog converter. The core of each DAC is based on the
ISL5961. The maximum update rate is at least 210+MSPS
and can be powered by a single power supply in the
recommended range of +3.0V to +3.6V. Operation with clock
rates higher than 210MSPS is possible; please contact the
factory for more information. It consumes less than 125mW
of power per channel when using a +3.3V supply, the
maximum 20mA of output current, and the data switching at
210MSPS. The architecture is based on a segmented
current source arrangement that reduces glitch by reducing
the amount of current switching at any one time. In previous
architectures that contained all binary weighted current
sources or a binary weighted resistor ladder, the converter
might have a substantially larger amount of current turning
on and off at certain, worst-case transition points such as
midscale and quarter scale transitions. By greatly reducing
the amount of current switching at these major transitions,
the overall glitch of the converter is dramatically reduced,
improving settling time, transient problems, and accuracy.
Digital Inputs and Termination
The ISL5929 digital inputs are formatted as offset binary and
guaranteed to 3V LVCMOS levels. The internal register is
updated on the rising edge of the clock. To minimize
ISL5929
reflections, proper termination should be implemented. If the
lines driving the clock and the digital inputs are long 50
lines, then 50 termination resistors should be placed as
close to the converter inputs as possible connected to the
digital ground plane (if separate grounds are used). These
termination resistors are not likely needed as long as the
digital waveform source is within a few inches of the DAC.
For pattern drivers with very high speed edge rates, it is
recommended that the user consider series termination (50200prior to the DAC’s inputs in order to reduce the
amount of noise.
Power Supply
Separate digital and analog power supplies are
recommended. The allowable supply range is +2.7V to
+3.6V. The recommended supply range is +3.0 to 3.6V
(nominally +3.3V) to maintain optimum SFDR. However,
operation down to +2.7V is possible with some degradation
in SFDR. Reducing the analog output current can help the
SFDR at +2.7V. The SFDR values stated in the table of
specifications were obtained with a +3.3V supply.
Ground Planes
Separate digital and analog ground planes should be used.
All of the digital functions of the device and their
corresponding components should be located over the
digital ground plane and terminated to the digital ground
plane. The same is true for the analog components and the
analog ground plane.
Noise Reduction
To minimize power supply noise, 0.1F capacitors should be
placed as close as possible to the converter’s power supply
pins, AVDD and DVDD . Also, the layout should be designed
using separate digital and analog ground planes and these
capacitors should be terminated to the digital ground for
DVDD and to the analog ground for AVDD . Additional filtering
of the power supplies on the board is recommended.
Voltage Reference
The internal voltage reference of the device has a nominal
value of +1.23V with a 40ppm/°C drift coefficient over the
full temperature range of the converter. It is recommended
that a 0.1F capacitor be placed as close as possible to the
REFIO pin, connected to the analog ground. The REFLO pin
selects the reference. The internal reference can be selected
if REFLO is tied low (ground). If an external reference is
desired, then REFLO should be tied high (the analog supply
voltage) and the external reference driven into REFIO. The
full scale output current of the converter is a function of the
voltage reference used and the value of RSET. IOUT should
be within the 2mA to 22mA range, though operation below
2mA is possible, with performance degradation.
If the internal reference is used, VFSADJ will equal
approximately 1.2V. If an external reference is used, VFSADJ
11
will equal the external reference. The calculation for IOUT
(Full Scale) is:
IOUT(Full Scale) = (VFSADJ/RSET) X 32.
If the full scale output current is set to 20mA by using the
internal voltage reference (1.23V) and a 1.91k RSET
resistor, then the input coding to output current will resemble
the following:
TABLE 1. INPUT CODING vs OUTPUT CURRENT WITH
INTERNAL REFERENCE (1.23V TYP) AND
RSET=1.91K
INPUT CODE (D13-D0)
IOUTA (mA)
IOUTB (mA)
11 1111 1111 1111
20.6
0
10 0000 0000 0000
10.3
10.3
00 0000 0000 0000
0
20.6
Analog Output
IOUTA and IOUTB are complementary current outputs. The
sum of the two currents is always equal to the full scale
output current minus one LSB. If single ended use is
desired, a load resistor can be used to convert the output
current to a voltage. It is recommended that the unused
output be either grounded or equally terminated. The voltage
developed at the output must not violate the output voltage
compliance range of -1.0V to 1.25V. ROUT (the impedance
loading each current output) should be chosen so that the
desired output voltage is produced in conjunction with the
output full scale current. If a known line impedance is to be
driven, then the output load resistor should be chosen to
match this impedance. The output voltage equation is:
VOUT = IOUT X ROUT.
The most effective method for reducing the power
consumption is to reduce the analog output current, which
dominates the supply current. The maximum recommended
output current is 20mA.
Differential Output
IOUTA and IOUTB can be used in a differential-to-singleended arrangement to achieve better harmonic rejection.
With RDIFF= 50and RLOAD=50, the circuit in Figure 13
will provide a 500mV (-2.5dBm) signal at the output of the
transformer if the full scale output current of the DAC is set
to 20mA (used for the electrical specifications table). Values
of RDIFF= 100and RLOAD=50 were used for the typical
performance curves to increase the output power and the
dynamic range. The center tap in Figure 13 must be
grounded.
In the circuit in Figure 14, the user is left with the option to
ground or float the center tap. The DC voltage that will exist
at either IOUTA or IOUTB if the center tap is floating is
IOUTDC x (RA//RB) V because RDIFF is DC shorted by the
transformer. If the center tap is grounded, the DC voltage is
0V. Recommended values for the circuit in Figure 14 are
ISL5929
RA=RB=50, RDIFF=100, assuming RLOAD=50. The
performance of Figure 13 and Figure 14 is basically the
same, however leaving the center tap of Figure 14 floating
allows the circuit to find a more balanced virtual ground,
theoretically improving the even order harmonic rejection,
but likely reducing the signal swing available due to the
output voltage compliance range limitations.
REQ = 0.5 x (RLOAD // RDIFF// RA), WHERE RA=RB
AT EACH OUTPUT
RA
OUTA
RDIFF
OUTB
ISL5929
REQ = 0.5 x (RLOAD // RDIFF)
AT EACH OUTPUT
RDIFF
ISL5929
RLOAD
RB
RLOAD REPRESENTS THE
LOAD SEEN BY THE TRANSFORMER
VOUT = (2 x OUTA x REQ)V
1:1
OUTA
VOUT = (2 x OUTA x REQ)V
FIGURE 14. ALTERNATIVE OUTPUT LOADING
Propagation Delay
RLOAD
OUTB
The converter requires two clock rising edges for data to be
represented at the output. Each rising edge of the clock
captures the present data word and outputs the previous
data. The propagation delay is therefore 1/CLK, plus <2ns of
processing. See Figure 15.
RLOAD REPRESENTS THE
LOAD SEEN BY THE TRANSFORMER
FIGURE 13. OUTPUT LOADING FOR DATASHEET
MEASUREMENTS
Test Service
Intersil offers customer-specific testing of converters with a
service called Testdrive. To submit a request, fill out the
Testdrive form at www.intersil.com/testdrive. Or, send a
request to the technical support center.
Timing Diagram
tPW2
tPW1
50%
CLK
tSU
tSU
tHLD
D13-D0
W0
tSU
tHLD
tHLD
W1
W2
W3
tPD
tPD
OUTPUT=W0
IOUT
OUTPUT=W-1
OUTPUT=W1
FIGURE 15. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM
12
ISL5929
Thin Plastic Quad Flatpack Packages (LQFP)
Q48.7x7A (JEDEC MS-026BBC ISSUE B)
48 LEAD THIN PLASTIC QUAD FLATPACK PACKAGE
D
D1
-D-
INCHES
-A-
-B-
E E1
e
PIN 1
SEATING
A PLANE
-H-
0.08
0.003
-C-
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.062
-
1.60
-
A1
0.002
0.005
0.05
0.15
-
A2
0.054
0.057
1.35
1.45
-
b
0.007
0.010
0.17
0.27
6
b1
0.007
0.009
0.17
0.23
-
D
0.350
0.358
8.90
9.10
3
D1
0.272
0.280
6.90
7.10
4, 5
E
0.350
0.358
8.90
9.10
3
E1
0.272
0.280
6.90
7.10
4, 5
L
0.018
0.029
0.45
0.75
N
48
48
e
0.020 BSC
0.50 BSC
7
Rev. 2 1/99
NOTES:
1. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.
2. All dimensions and tolerances per ANSI Y14.5M-1982.
3. Dimensions D and E to be determined at seating plane -C- .
0.08
0.003 M
D S
C A-B S
b
11o-13o
0.020
0.008 MIN
b1
0o MIN
A2 A1
GAGE
PLANE
0o-7o
0.25
0.010
11o-13o
5. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is 0.25mm (0.010 inch) per side.
6. Dimension b does not include dambar protrusion. Allowable
dambar protrusion shall not cause the lead width to exceed
the maximum b dimension by more than 0.08mm (0.003
inch).
0.09/0.16
0.004/0.006
BASE METAL
WITH PLATING
L
4. Dimensions D1 and E1 to be determined at datum plane
-H- .
7. “N” is the number of terminal positions.
0.09/0.20
0.004/0.008
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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