DATASHEET

ESIGNS
R NE W D NT
O
F
D
E
E
ND
COMME
PL A CEM r a t
N OT R E
DED RE
N
te
E
n
e
M
C
M
rt
O
NO REC
al Suppo il.com/tsc
ic
n
h
c
e
T
s
r
te
t our
ontacSheet
r www.in
cData
July 2004
ERSIL o
T
N
-I
8
8
1-8
HI5746
FN4129.5
10-Bit, 40MSPS A/D Converter
Features
The HI5746 is a monolithic, 10-bit, analog-to-digital
converter fabricated in a CMOS process. It is designed for
high speed applications where wide bandwidth and low
power consumption are essential. Its 40MSPS speed is
made possible by a fully differential pipelined architecture
with an internal sample and hold.
• Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . 40MSPS
The HI5746 has excellent dynamic performance while
consuming only 225mW power at 40MSPS. Data output
latches are provided which present valid data to the output
bus with a latency of 7 clock cycles. It is pin-for-pin
functionally compatible with the HI5702 and the HI5703.
For internal voltage reference, please refer to the HI5767
data sheet.
TEMP.
RANGE (°C)
• Low Power at 40MSPS . . . . . . . . . . . . . . . . . . . . 225mW
• Wide Full Power Input Bandwidth . . . . . . . . . . . . 250MHz
• On-Chip Sample and Hold
• Fully Differential or Single-Ended Analog Input
• Single Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . +5V
• TTL/CMOS Compatible Digital Inputs
• CMOS Compatible Digital Outputs. . . . . . . . . . . . 3.0/5.0V
• Offset Binary or Two’s Complement Output Format
• Pb-free Available
Ordering Information
PART
NUMBER
• 8.8 Bits at fIN = 10MHz
PACKAGE
PKG.
DWG. #
Applications
• Professional Video Digitizing
HI5746KCB
0 to 70
28 Ld SOIC (W)
M28.3
• Medical Imaging
HI5746KCBZ
(Note)
0 to 70
28 Ld SOIC (W)
(Pb-free)
M28.3
• Digital Communication Systems
28 Ld SOIC (W) Tape and Reel
(Pb-free)
M28.3
HI5746KCBZ-T
(Note)
• High Speed Data Acquisition
HI5746KCA
0 to 70
28 Ld SSOP
M28.15
HI5746KCAZ
(Note)
0 to 70
28 Ld SSOP
(Pb-free)
M28.15
HI5746EVAL1
25
Evaluation Board
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J Std-020B.
Pinout
HI5746
(SOIC, SSOP)
TOP VIEW
DVCC1 1
28 D0
DGND1 2
27 D1
DVCC1 3
26 D2
DGND1 4
25 D3
AVCC 5
24 D4
AGND 6
VREF + 7
23 DVCC2
22 CLK
VREF - 8
21 DGND2
VIN+ 9
20 D5
VIN- 10
19 D6
VDC 11
18 D7
AGND 12
17 D8
AVCC 13
16 D9
OE 14
1
15 DFS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 1999, 2004. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HI5746
Functional Block Diagram
VDC
CLOCK
BIAS
CLK
VINVIN+
S/H
STAGE 1
DFS
2-BIT
FLASH
2-BIT
DAC
OE
+

DVCC2
X2
D9 (MSB)
D8
D7
D6
DIGITAL DELAY
AND
DIGITAL ERROR
CORRECTION
STAGE 8
D5
D4
D3
2-BIT
FLASH
2-BIT
DAC
D2
D1
+

D0 (LSB)
-
X2
DGND2
STAGE 9
2-BIT
FLASH
AVCC
2
AGND
DVCC1
DGND1
VREF +
VREF - (OPTIONAL)
HI5746
Typical Application Schematic
HI5746
2.5V
2.0V
(OPTIONAL)
VREF+ (7)
VREF - (8)
(LSB) (28) D0
D0
(27) D1
D1
(26) D2
D2
(25) D3
D3
(24) D4
D4
DGND1 (2)
(20) D5
D5
DGND1 (4)
(19) D6
D6
DGND2 (21)
(18) D7
D7
(17) D8
D8
(MSB) (16) D9
D9
AGND (12)
AGND (6)
VIN +
CLOCK
VDC (11)
(3) DVCC1
VIN - (10)
(23) DVCC2
CLK (22)
(13) AVCC
DFS (15)
(5) AVCC
AGND
BNC
10F AND 0.1F CAPS
ARE PLACED AS CLOSE
TO PART AS POSSIBLE
(1) DVCC1
VIN + (9)
VIN -
DGND
OE (14)
0.1F
+
10F
0.1F
+
10F
+5V
+5V
Pin Descriptions
PIN NO.
NAME
Digital Supply (+5.0V).
16
D9
Data Bit 9 Output (MSB).
DGND1
Digital Ground.
17
D8
Data Bit 8 Output.
3
DVCC1
Digital Supply (+5.0V).
18
D7
Data Bit 7 Output.
4
DGND1
Digital Ground.
19
D6
Data Bit 6 Output.
5
AVCC
Analog Supply (+5.0V).
20
D5
Data Bit 5 Output.
6
AGND
Analog Ground.
21
DGND2
7
VREF+
+2.5V Positive Reference Voltage
Input.
22
CLK
Sample Clock Input.
23
8
VREF -
+2.0V Negative Reference Voltage
Input (Optional).
DVCC2
Digital Output Supply
(+3.0V or +5.0V).
24
D4
Data Bit 4 Output.
9
VIN+
Positive Analog Input.
25
D3
Data Bit 3 Output.
10
VIN-
Negative Analog Input.
26
D2
Data Bit 2 Output.
11
VDC
DC Bias Voltage Output.
27
D1
Data Bit 1 Output.
12
AGND
Analog Ground.
28
D0
Data Bit 0 Output (LSB).
13
AVCC
Analog Supply (+5.0V).
14
OE
Digital Output Enable Control Input.
15
DFS
Data Format Select Input.
PIN NO.
NAME
1
DVCC1
2
DESCRIPTION
3
DESCRIPTION
Digital Ground.
HI5746
Absolute Maximum Ratings TA = 25oC
Thermal Information
Supply Voltage, AVCC or DVCC to AGND or DGND . . . . . . . . . . .6V
DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V
Digital I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND to DVCC
Analog I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND to AVCC
Thermal Resistance (Typical, Note 1)
JA (oC/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(SOIC, SSOP - Lead Tips Only)
Operating Conditions
Temperature Range
HI5746KCB (Typ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
AVCC = DVCC1 = 5.0V; DVCC2 = 3.0V, VREF+ = 2.5V; VREF - = 2.0V; fS = 40 MSPS at 50% Duty Cycle;
CL = 10pF; TA = 25oC; Differential Analog Input; Typical Values are Test Results at 25oC,
Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
10
-
-
Bits
ACCURACY
Resolution
Integral Linearity Error, INL
fIN = DC
-
1.0
2.0
LSB
Differential Linearity Error, DNL
(Guaranteed No Missing Codes)
fIN = DC
-
0.5
1.0
LSB
Offset Error, VOS
fIN = DC
-40
12
40
LSB
Full Scale Error, FSE
fIN = DC
-
4
-
LSB
Minimum Conversion Rate
No Missing Codes
-
0.5
1
MSPS
Maximum Conversion Rate
No Missing Codes
40
-
-
MSPS
Effective Number of Bits, ENOB
fIN = 10MHz
8.55
8.8
-
Bits
Signal to Noise and Distortion Ratio, SINAD
RMS Signal
= -------------------------------------------------------------RMS Noise + Distortion
fIN = 10MHz
53.2
54.9
-
dB
Signal to Noise Ratio, SNR
RMS Signal
= ------------------------------RMS Noise
fIN = 10MHz
53.2
55.4
-
dB
Total Harmonic Distortion, THD
fIN = 10MHz
-
-64.6
-
dBc
2nd Harmonic Distortion
fIN = 10MHz
-
-67.8
-
dBc
3rd Harmonic Distortion
fIN = 10MHz
-
-68.3
-
dBc
Spurious Free Dynamic Range, SFDR
fIN = 10MHz
-
67.8
-
dBc
Intermodulation Distortion, IMD
f1 = 1MHz, f2 = 1.02MHz
-
64
-
dBc
Differential Gain Error
fS = 17.72 MSPS, 6 Step, Mod Ramp
-
0.8
-
%
Differential Phase Error
fS = 17.72 MSPS, 6 Step, Mod Ramp
-
0.1
-
Degree
Transient Response
(Note 2)
-
1
-
Cycle
Over-Voltage Recovery
0.2V Overdrive (Note 2)
-
1
-
Cycle
DYNAMIC CHARACTERISTICS
4
HI5746
Electrical Specifications
AVCC = DVCC1 = 5.0V; DVCC2 = 3.0V, VREF+ = 2.5V; VREF - = 2.0V; fS = 40 MSPS at 50% Duty Cycle;
CL = 10pF; TA = 25oC; Differential Analog Input; Typical Values are Test Results at 25oC,
Unless Otherwise Specified (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Maximum Peak-to-Peak Differential Analog Input
Range (VIN+ - VIN-)
-
0.5
-
V
Maximum Peak-to-Peak Single-Ended
Analog Input Range
-
1.0
-
V
-
1
-
M
-
10
-
pF
ANALOG INPUT
(Note 3)
Analog Input Resistance, RIN
Analog Input Capacitance, CIN
Analog Input Bias Current, IB+ or IB-
(Note 3)
-10
-
+10
A
Differential Analog Input Bias Current
IBDIFF = (IB+ - IB-)
(Note 3)
-
0.5
-
A
-
250
-
MHz
0.25
-
4.75
V
-
2.5K
-

Positive Reference Current, IREF +
-
1.07
-
mA
Negative Reference Current, IREF -
-
21
-
A
Full Power Input Bandwidth, FPBW
Analog Input Common Mode Voltage Range
(VIN+ + VIN-)/2
Differential Mode (Note 2)
REFERENCE INPUT
VREF + to AGND
Total Reference Resistance, RL
Positive Reference Voltage Input, VREF+
(Note 2)
-
2.5
-
V
Negative Reference Voltage Input, VREF -
(Note 2)
-
2.0
-
V
Reference Common Mode Voltage
(VREF+ + VREF -)/2
(Note 2)
-
2.25
-
V
DC Bias Voltage Output, VDC
-
3.2
-
V
Maximum Output Current
-
-
0.4
mA
DC BIAS VOLTAGE
DIGITAL INPUTS
Input Logic High Voltage, VIH
CLK, DFS, OE
2.0
-
-
V
Input Logic Low Voltage, VIL
CLK, DFS, OE
-
-
0.8
V
Input Logic High Current, IIH
CLK, DFS, OE, VIH = 5V
-10.0
-
+10.0
A
Input Logic Low Current, IIL
CLK, DFS, OE, VIL = 0V
-10.0
-
+10.0
A
-
7
-
pF
Input Capacitance, CIN
DIGITAL OUTPUTS
Output Logic High Voltage, VOH
IOH = 100A; DVCC2 = 5V
4.0
-
-
V
Output Logic Low Voltage, VOL
IOL = 100A; DVCC2 = 5V
-
-
0.5
V
Output Three-State Leakage Current, IOZ
VO = 0/5V; DVCC2 = 5V
-
1
10
A
Output Logic High Voltage, VOH
IOH = 100A; DVCC2 = 3V
2.4
-
-
V
Output Logic Low Voltage, VOL
IOL = 100A; DVCC2 = 3V
-
-
0.5
V
5
HI5746
Electrical Specifications
AVCC = DVCC1 = 5.0V; DVCC2 = 3.0V, VREF+ = 2.5V; VREF - = 2.0V; fS = 40 MSPS at 50% Duty Cycle;
CL = 10pF; TA = 25oC; Differential Analog Input; Typical Values are Test Results at 25oC,
Unless Otherwise Specified (Continued)
PARAMETER
MIN
TYP
MAX
UNITS
-
1
10
A
-
10
-
pF
Aperture Delay, tAP
-
5
-
ns
Aperture Jitter, tAJ
-
5
-
psRMS
Data Output Hold, tH
-
7
-
ns
Data Output Delay, tOD
-
8
-
ns
Data Output Enable Time, tEN
-
5
-
ns
Data Output Enable Time tDIS
-
5
-
ns
Output Three-State Leakage Current, IOZ
TEST CONDITIONS
VO = 0/5V; DVCC2 = 3V
Output Capacitance, COUT
TIMING CHARACTERISTICS
Data Latency, tLAT
For a Valid Sample (Note 2)
-
-
7
Cycles
Power-Up Initialization
Data Invalid Time (Note 2)
-
-
20
Cycles
Analog Supply Voltage, AVCC
4.75
5.0
5.25
V
Digital Supply Voltage DVCC1
4.75
5.0
5.25
V
At 3.0V
2.7
3.0
3.3
V
At 5.0V
4.75
5.0
5.25
V
POWER SUPPLY CHARACTERISTICS
Digital Output Supply Voltage, DVCC2
Total Supply Current, ICC
fIN = 10MHz and DFS = “0”
-
46
-
mA
Analog Supply Current, AICC
fIN = 10MHz and DFS = “0”
-
30
-
mA
Digital Supply Current, DICC1
fIN = 10MHz and DFS = “0”
-
13
-
mA
Output Supply Current, DICC2
fIN = 10MHz and DFS = “0”
-
3
-
mA
Power Dissipation
fIN = 10MHz and DFS = “0”
-
225
275
mW
Offset Error SensitivityVOS
AVCC or DVCC = 5V 5%
-
0.4
-
LSB
Gain Error SensitivityFSE
AVCC or DVCC = 5V 5%
-
0.8
-
LSB
NOTES:
2. Parameter guaranteed by design or characterization and not production tested.
3. With the clock low and DC input.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
6
HI5746
Timing Waveforms
ANALOG
INPUT
CLOCK
INPUT
SN - 1
HN - 1
SN
HN
S N + 1 HN + 1
SN + 2
S N + 5 HN + 5
SN + 6 HN + 6 SN + 7 HN + 7
S N + 8 HN + 8
INPUT
S/H
1ST
STAGE
2ND
STAGE
B1, N - 1
B2, N - 2
9TH
STAGE
DATA
OUTPUT
B1, N
B1, N + 1
B1, N + 4
B1, N + 5
B2, N - 1
B2, N
B2, N + 4
B2, N + 5
B2, N + 6
B9, N - 5
B9, N - 4
B9, N
B9, N + 1
B9, N + 2
DN - 7
DN - 6
DN - 2
DN - 1
tLAT
NOTES:
4. SN : N-th sampling period.
5. HN : N-th holding period.
6. BM, N : M-th stage digital output corresponding to N-th sampled input.
7. DN : Final data output corresponding to N-th sampled input.
FIGURE 1. HI5746 INTERNAL CIRCUIT TIMING
ANALOG
INPUT
tAP
tAJ
CLOCK
INPUT
1.5V
1.5V
tOD
tH
DATA
OUTPUT
2.4V
DATA N - 1
0.5V
FIGURE 2. INPUT-TO OUTPUT TIMING
7
B1, N + 6
DATA N
DN
B1, N + 7
B9, N + 3
DN + 1
HI5746
Typical Performance Curves
9
57
SNR
dB
ENOB (BITS)
52
SINAD
8
47
7
42
fS = 40 MSPS, TA = 25oC
fS = 40 MSPS, TA = 25oC
6
1
10
37
100
1
10
FIGURE 3. EFFECTIVE NUMBER OF BITS (ENOB) vs INPUT
FREQUENCY
85
FIGURE 4. SINAD AND SNR vs INPUT FREQUENCY
fS = 40 MSPS, TA = 25oC
9
80
8
dBc
ENOB (BITS)
SFDR
70
-3HD
65
60
-THD
55
50
45
fS = 40 MSPS, fIN = 10MHz, TA = 25oC
-2HD
75
7
6
5
1
10
100
4
INPUT FREQUENCY (MHz)
0
-5
-10
FIGURE 5. -2HD, -3HD, -THD AND SFDR vs INPUT
FREQUENCY
10
-15
-20
-25
-30
-35
INPUT LEVEL (dBFS)
NOTE: SFDR depicted here does not include any harmonic distortion.
FIGURE 6. EFFECTIVE NUMBER OF BITS (ENOB) vs
ANALOG INPUT LEVEL
9
fS = 40 MSPS, fIN = 10MHz, TA = 25oC
fS = 40 MSPS, fIN = 10MHz, TA = 25oC
VREF + - VREF - = 0.5V
9.5
8.8
ENOB (BITS)
9
ENOB (BITS)
100
INPUT FREQUENCY (MHz)
INPUT FREQUENCY (MHz)
8.5
8
7.5
8.6
8.4
7
6.5
6
30
35
40
45
50
55
60
65
DUTY CYCLE (%, TH /TCLK)
FIGURE 7. EFFECTIVE NUMBER OF BITS (ENOB) vs
SAMPLE CLOCK DUTY CYCLE
8
70
8.2
2.25
2.3
2.35
2.4
2.45 2.5 2.55
VREF + (V)
2.6
2.65
2.7
2.75
FIGURE 8. EFFECTIVE NUMBER OF BITS (ENOB) vs VREF +
HI5746
Typical Performance Curves
(Continued)
55
80
SNR
-2HD
75
54
SFDR
70
dBc
dB
SINAD
53
-3HD
65
-THD
52
60
fS = 40 MSPS, fIN = 10MHz
fS = 40 MSPS, fIN = 10MHz
VREF + - VREF - = 0.5V, TA = 25oC
51
2.25
2.3
2.35
2.4
2.45 2.5 2.55
VREF + (V)
2.6
2.65
2.7
55
2.25
2.75
2.3
2.35
2.4
2.45 2.5 2.55
VREF + (V)
2.6
2.65
2.7
2.75
NOTE: SFDR depicted here does not include any harmonic
distortion.
FIGURE 9. SINAD AND SNR vs VREF +
FIGURE 10. -2HD, -3HD, -THD AND SFDR vs VREF +
8.8
53
fS = 40 MSPS, fIN = 10MHz
TA = 25oC
fS = 40 MSPS, fIN = 10MHz
TA = 25oC
8.6
SNR
52
SINAD
dB
ENOB (BITS)
VREF + - VREF - = 0.5V, TA = 25oC
8.4
8.2
8
2.25
51
50
2.3
2.35
2.4
2.45 2.5 2.55
VREF + (V)
2.6
2.65
2.7
49
2.25
2.75
FIGURE 11. EFFECTIVE NUMBER OF BITS (ENOB) vs VREF +
(VREF - NOT DRIVEN)
2.3
2.35
2.4
2.45 2.5 2.55
VREF + (V)
2.6
2.65
2.7
2.75
FIGURE 12. SINAD AND SNR vs VREF + (VREF - NOT DRIVEN)
9.0
80
fIN = 1MHz
fS = 40 MSPS, fIN = 10MHz
TA = 25oC
-2HD
8.8
ENOB (BITS)
75
70
dBc
-3HD
65
fIN = 10MHz
8.6
8.4
-THD
60
55
2.25
8.2
SFDR
2.3
2.35
2.4
2.45 2.5 2.55
VREF + (V)
fS = 40 MSPS, TA = 25oC
DIFFERENTIAL ANALOG INPUT
2.6
2.65
FIGURE 13. -2HD, -3HD, -THD AND SFDR vs VREF +
(VREF - NOT DRIVEN)
9
2.7
2.75
8.0
0.25
0.75
1.25
1.75
2.25 2.75
VCM (V)
3.25
3.75
4.25
FIGURE 14. EFFECTIVE NUMBER OF BITS (ENOB) vs
ANALOG INPUT COMMON MODE VOLTAGE
4.75
HI5746
Typical Performance Curves
(Continued)
50
45.0
44.5
SUPPLY CURRENT (mA)
44.0
43.5
ICC (mA)
1MHz  fIN  15MHz, TA = 25oC
fS = 40 MSPS, VIN + = VIN -
43.0
42.5
42.0
41.5
ICC (TOTAL)
40
AICC
30
20
DICC1
10
41.0
DICC2
40.5
-40
0
-20
0
20
40
TEMPERATURE (oC)
60
10
80
30
40
fS (MSPS)
FIGURE 15. TOTAL SUPPLY CURRENT vs TEMPERATURE
FIGURE 16. SUPPLY CURRENT vs SAMPLE CLOCK
FREQUENCY
1200
9.5
1000
9.0
IREF +
8.5
800
tOD
tOD (ns)
IREF (A)
20
600
400
8.0
7.5
7.0
200
6.5
IREF -20
0
20
40
TEMPERATURE (oC)
60
6.0
-40
80
FIGURE 17. REFERENCE CURRENT vs TEMPERATURE
DG
DG (%)
0.75
0.15
0.70
DP
0.65
0.65
0.2
0.1
0.60
0.55
0.05
0.50
0.45
0.40
-40
-20
0
20
40
TEMPERATURE (oC)
60
80
0
FIGURE 19. DIFFERENTIAL GAIN/PHASE vs TEMPERATURE
10
0.60
DG (%)
0.80
20
40
TEMPERATURE (oC)
60
80
0.3
0.70
fS = 17.72 MSPS
DP (DEGREES)
0.85
0
FIGURE 18. DATA OUTPUT DELAY vs TEMPERATURE
0.25
0.90
-20
DP
0.25
DG
0.2
DP
0.15
0.55
DG
0.50
0.45
fS = 17.72 MSPS
AVCC/DVCC1 = 5V 5%, TA = 25oC
0.1
0.05
0
0.40
2.75 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25
DVCC2 (V)
FIGURE 20. DIFFERENTIAL GAIN/PHASE vs SUPPLY
VOLTAGE
DP (DEGREES)
0
-40
HI5746
Typical Performance Curves
(Continued)
3.30
9.0
8.8
ENOB (BITS)
VDC (V)
3.20
3.10
8.6
8.4
3.00
-40
-20
0
20
40
TEMPERATURE (oC)
60
80
8.2
-40
-20
0
20
40
60
80
TEMPERATURE (oC)
FIGURE 21. DC BIAS VOLTAGE (VDC) vs TEMPERATURE
FIGURE 22. EFFECTIVE NUMBER OF BITS F(ENOB) vs
TEMPERATURE
OUTPUT LEVEL (dB)
0
-10
fIN = 10MHz
fS = 40 MSPS
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
FIGURE 23. 2048 POINT FFT PLOT
512
FREQUENCY BIN
1023
FIGURE 24. 2048 POINT FFT SPECTRAL PLOT
Detailed Description
Theory of Operation
The HI5746 is a 10-bit fully differential sampling pipeline A/D
converter with digital error correction logic. Figure 25 depicts
the circuit for the front end differential-in-differential-out sampleand-hold (S/H). The switches are controlled by an internal
sampling clock which is a non-overlapping two phase signal1
and 2 , derived from the master sampling clock. During the
sampling phase, 1 , the input signal is applied to the sampling
capacitors, CS . At the same time the holding capacitors, CH ,
are discharged to analog ground. At the falling edge of 1 the
input signal is sampled on the bottom plates of the sampling
capacitors. In the next clock phase,2 , the two bottom plates of
the sampling capacitors are connected together and the
holding capacitors are switched to the op amp output nodes.
The charge then redistributes between CS and CH completing
one sample-and-hold cycle. The front end sample-and-hold
11
output is a fully-differential, sampled-data representation of the
analog input. The circuit not only performs the sample-and-hold
function but will also convert a single-ended input to a fullydifferential output for the converter core. During the sampling
phase, the VIN pins see only the on-resistance of a switch and
CS . The relatively small values of these components result in a
typical full power input bandwidth of 250MHz for the converter.
HI5746
-+
VOUT+
+-
VOUT-
structure of the VREF+ and VREF - input pins consists of a
resistive voltage divider with one resistor of the divider
(nominally 500) connected between VREF+ and VREF - and
the other resistor of the divider (nominally 2000) connected
between VREF - and analog ground. This allows the user the
option of supplying only the +2.5V VREF+ voltage reference
with the +2.0V VREF - being generated internally by the
voltage division action of the input structure.
FIGURE 25. ANALOG INPUT SAMPLE-AND-HOLD
The HI5746 is tested with VREF - equal to +2.0V and VREF+
equal to +2.5V yielding a fully differential analog input voltage
range of 0.5V. VREF+ and VREF - can differ from the above
voltages (see the Typical Performance Curves, Figure 8
through Figure 13).
1
VIN+
1
1
1
CS
2
VIN-
CH
CS
1
CH
1
As illustrated in the functional block diagram and the timing
diagram in Figure 1, eight identical pipeline subconverter
stages, each containing a two-bit flash converter and a
two-bit multiplying digital-to-analog converter, follow the S/H
circuit with the ninth stage being a two bit flash converter.
Each converter stage in the pipeline will be sampling in one
phase and amplifying in the other clock phase. Each
individual subconverter clock signal is offset by 180 degrees
from the previous stage clock signal resulting in alternate
stages in the pipeline performing the same operation.
The output of each of the eight identical two-bit subconverter
stages is a two-bit digital word containing a supplementary bit
to be used by the digital error correction logic. The output of
each subconverter stage is input to a digital delay line which is
controlled by the internal sampling clock. The function of the
digital delay line is to time align the digital outputs of the eight
identical two-bit subconverter stages with the corresponding
output of the ninth stage flash converter before applying the
eighteen bit result to the digital error correction logic. The
digital error correction logic uses the supplementary bits to
correct any error that may exist before generating the final ten
bit digital data output of the converter.
Because of the pipeline nature of this converter, the digital
data representing an analog input sample is output to the
digital data bus on the 7th cycle of the clock after the analog
sample is taken. This time delay is specified as the data
latency. After the data latency time, the digital data
representing each succeeding analog sample is output
during the following clock cycle. The digital output data is
synchronized to the external sampling clock by a double
buffered latching technique. The output of the digital error
correction circuit is available in two’s complement or offset
binary format depending on the state of the Data Format
Select (DFS) control input (see Table 1, A/D Code Table).
Reference Voltage Inputs, VREF - and VREF+
The HI5746 is designed to accept two external reference
voltage sources at the VREF input pins. Typical operation of
the converter requires VREF+ to be set at +2.5V and VREF - to
be set at 2.0V. However, it should be noted that the input
12
In order to minimize overall converter noise it is recommended
that adequate high frequency decoupling be provided at both
of the reference voltage input pins, VREF+ and VREF -.
Analog Input, Differential Connection
The analog input to the HI5746 is a differential input that can
be configured in various ways depending on the signal
source and the required level of performance. A fully
differential connection (Figure 26 and Figure 27) will give the
best performance for the converter.
VIN+
VIN
R
HI5746
VDC
R
-VIN
VIN-
FIGURE 26. AC COUPLED DIFFERENTIAL INPUT
Since the HI5746 is powered by a single +5V analog supply,
the analog input is limited to be between ground and +5V.
For the differential input connection this implies the analog
input common mode voltage can range from 0.25V to 4.75V.
The performance of the ADC does not change significantly
with the value of the analog input common mode voltage.
A DC voltage source, VDC , equal to 3.2V (typical), is made
available to the user to help simplify circuit design when using
an AC coupled differential input. This low output impedance
voltage source is not designed to be a reference but makes
an excellent DC bias source and stays well within the analog
input common mode voltage range over temperature (see the
Typical Performance Curves, Figure 21).
For the AC coupled differential input (Figure 26) assume
the difference between VREF+, typically 2.5V, and VREF-,
typically 2.0V, is 0.5V. Full scale is achieved when the VIN
and -VIN input signals are 0.5VP-P, with -VIN being
180 degrees out of phase with VIN . The converter will be
HI5746
at positive full scale when the VIN+ input is at
VDC + 0.25V and the VIN- input is at VDC - 0.25V (VIN+ VIN- = +0.5V). Conversely, the converter will be at
negative fullscale when the VIN+ input is equal to VDC 0.25V and VIN- is at VDC + 0.25V (VIN+ - VIN- = -0.5V).
The analog input can be DC coupled (Figure 27) as long as
the inputs are within the analog input common mode voltage
range (0.25V  VDC  4.75V).
The single ended analog input can be DC coupled
(Figure 27) as long as the input is within the analog input
common mode voltage range.
VIN
VIN+
VDC
R
C
HI5746
VIN
VIN+
VDC
R
C
R
VDC
VIN-
FIGURE 27. DC COUPLED DIFFERENTIAL INPUT
The resistors, R, in Figure 27 are not absolutely necessary
but may be used as load setting resistors. A capacitor, C,
connected from VIN+ to VIN- will help filter any high
frequency noise on the inputs, also improving performance.
Values around 20pF are sufficient and can be used on AC
coupled inputs as well. Note, however, that the value of
capacitor C chosen must take into account the highest
frequency component of the analog input signal.
Analog Input, Single-Ended Connection
The configuration shown in Figure 28 may be used with a
single ended AC coupled input.
VIN+
VIN
R
HI5746
VDC
VIN-
FIGURE 28. AC COUPLED SINGLE ENDED INPUT
Again, assume the difference between VREF+, typically
2.5V, and VREF-, typically 2V, is 0.5V. If VIN is a 1VP-P
sinewave, then VIN+ is a 1VP-P sinewave riding on a
positive voltage equal to VDC. The converter will be at
positive full scale when VIN+ is at VDC + 0.5V (VIN+ - VIN= +0.5V) and will be at negative full scale when VIN+ is
equal to VDC - 0.5V (VIN+ - VIN- = -0.5V). Sufficient
headroom must be provided such that the input voltage
never goes above +5V or below AGND. In this case, VDC
could range between 0.5V and 4.5V without a significant
change in ADC performance. The simplest way to produce
VDC is to use the DC bias source, VDC , output of the
HI5746.
13
VIN-
HI5746
VDC
-VIN
VDC
FIGURE 29. DC COUPLED SINGLE ENDED INPUT
The resistor, R, in Figure 29 is not absolutely necessary but
may be used as a load setting resistor. A capacitor, C,
connected from VIN+ to VIN- will help filter any high
frequency noise on the inputs, also improving performance.
Values around 20pF are sufficient and can be used on AC
coupled inputs as well. Note, however, that the value of
capacitor C chosen must take into account the highest
frequency component of the analog input signal.
A single ended source may give better overall system
performance if it is first converted to differential before
driving the HI5746.
Digital Output Control and Clock Requirements
The HI5746 provides a standard high-speed interface to
external TTL logic families.
In order to ensure rated performance of the HI5746, the duty
cycle of the clock should be held at 50% 5%. It must also
have low jitter and operate at standard TTL levels.
Performance of the HI5746 will only be guaranteed at
conversion rates above 1 MSPS. This ensures proper
performance of the internal dynamic circuits. Similarly, when
power is first applied to the converter, a maximum of 20
cycles at a sample rate above 1 MSPS will have to be
performed before valid data is available.
A Data Format Select (DFS) pin is provided which will
determine the format of the digital data outputs. When at
logic low, the data will be output in offset binary format.
When at logic high, the data will be output in two’s
complement format. Refer to Table 1 for further information.
HI5746
TABLE 1. A/D CODE TABLE
OFFSET BINARY OUTPUT CODE
(DFS LOW)
M
S
B
TWO’S COMPLEMENT OUTPUT CODE
(DFS HIGH)
L
S
B
M
S
B
L
S
B
DIFFERENTIAL
INPUT VOLTAGE
(VIN+ - VIN-)
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
+Full Scale (+FS) 1/ LSB
4
0.499756V
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
+FS - 11/4 LSB
0.498779V
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
0
+3/4 LSB
732.422V
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-1/4 LSB
-244.141V
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
-FS + 13/4 LSB
-0.498291V
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
-Full Scale (-FS) +
3/ LSB
4
-0.499268V
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
CODE CENTER
DESCRIPTION
NOTES:
8. The voltages listed above represent the ideal center of each output code shown as a function of the reference differential voltage,
(VREF + - VREF -) = 0.5V.
9. VREF+ = 2.5V and VREF - = 2V.
The output enable pin, OE, when pulled high will three-state
the digital outputs to a high impedance state. Set the OE
input to logic low for normal operation.
OE INPUT
DIGITAL DATA OUTPUTS
0
Active
1
High Impedance
Supply and Ground Considerations
The HI5746 has separate analog and digital supply and
ground pins to keep digital noise out of the analog signal
path. The digital data outputs also have a separate supply
pin, DVCC2 , which can be powered from a 3V or 5V supply.
This allows the outputs to interface with 3V logic if so
desired.
The part should be mounted on a board that provides
separate low impedance connections for the analog and
digital supplies and grounds. For best performance, the
supplies to the HI5746 should be driven by clean, linear
regulated supplies. The board should also have good high
frequency decoupling capacitors mounted as close as
possible to the converter. If the part is powered off a single
supply then the analog supply should be isolated with a
ferrite bead from the digital supply.
Refer to the application note “Using Intersil High Speed A/D
Converters” (AN9214) for additional considerations when
using high speed converters.
14
Static Performance Definitions
Offset Error (VOS)
The midscale code transition should occur at a level 1/4 LSB
above half-scale. Offset is defined as the deviation of the
actual code transition from this point.
Full-Scale Error (FSE)
The last code transition should occur for an analog input that
is 3/4 LSB below positive Full scale (+FS) with the offset
error removed. Fullscale error is defined as the deviation of
the actual code transition from this point.
Differential Linearity Error (DNL)
DNL is the worst case deviation of a code width from the
ideal value of 1 LSB.
Integral Linearity Error (INL)
INL is the worst case deviation of a code center from a best
fit straight line calculated from the measured data.
Power Supply Sensitivity
Each of the power supplies are moved plus and minus 5%
and the shift in the offset and full scale error (in LSBs) is
noted.
Dynamic Performance Definitions
Fast Fourier Transform (FFT) techniques are used to evaluate
the dynamic performance of the HI5746. A low distortion sine
wave is applied to the input, it is coherently sampled, and the
output is stored in RAM. The data is then transformed into the
frequency domain with an FFT and analyzed to evaluate the
dynamic performance of the A/D. The sine wave input to the
part is -0.5dB down from Fullscale for all these tests.
HI5746
SNR and SINAD are quoted in dB. The distortion numbers are
quoted in dBc (decibels with respect to carrier) and DO NOT
include any correction factors for normalizing to full scale.
Full Power Input Bandwidth (FPBW)
The effective number of bits (ENOB) is calculated from the
SINAD data by:
Full power input bandwidth is the analog input frequency at
which the amplitude of the digitally reconstructed output has
decreased 3dB below the amplitude of the input sine wave.
The input sine wave has an amplitude which swings from
-FS to +FS. The bandwidth given is measured at the
specified sampling frequency.
ENOB = (SINAD - 1.76 + VCORR) / 6.02,
Video Definitions
Effective Number Of Bits (ENOB)
where: VCORR = 0.5 dB.
VCORR adjusts the SINAD, and hence the ENOB, for the
amount the analog input signal is below fullscale.
Signal To Noise and Distortion Ratio (SINAD)
SINAD is the ratio of the measured RMS signal to RMS sum
of all the other spectral components below the Nyquist
frequency, fS/2, excluding DC.
Signal To Noise Ratio (SNR)
SNR is the ratio of the measured RMS signal to RMS noise
at a specified input and sampling frequency. The noise is the
RMS sum of all of the spectral components below fS/2
excluding the fundamental, the first five harmonics and DC.
Differential Gain and Differential Phase are two commonly
found video specifications for characterizing the distortion of
a chrominance signal as it is offset through the input voltage
range of an ADC.
Differential Gain (DG)
Differential Gain is the peak difference in chrominance
amplitude (in percent) relative to the reference burst.
Differential Phase (DP)
Differential Phase is the peak difference in chrominance
phase (in degrees) relative to the reference burst.
Timing Definitions
Refer to Figure 1 and Figure 2 for these definitions.
Total Harmonic Distortion (THD)
Aperture Delay (tAP)
THD is the ratio of the RMS sum of the first 5 harmonic
components to the RMS value of the fundamental input
signal.
Aperture delay is the time delay between the external
sample command (the falling edge of the clock) and the time
at which the signal is actually sampled. This delay is due to
internal clock path propagation delays.
2nd and 3rd Harmonic Distortion
This is the ratio of the RMS value of the applicable harmonic
component to the RMS value of the fundamental input signal.
Spurious Free Dynamic Range (SFDR)
Aperture Jitter (tAJ)
Aperture jitter is the RMS variation in the aperture delay due
to variation of internal clock path delays.
SFDR is the ratio of the fundamental RMS amplitude to the
RMS amplitude of the next largest spectral component in the
spectrum below fS /2.
Data Hold Time (tH)
Intermodulation Distortion (IMD)
Data Output Delay Time (tOD)
Nonlinearities in the signal path will tend to generate
intermodulation products when two tones, f1 and f2 , are
present at the inputs. The ratio of the measured signal to
the distortion terms is calculated. The terms included in the
calculation are (f1+f2), (f1-f2), (2f1), (2f2), (2f1+f2), (2f1-f2),
(f1+2f2), (f1-2f2). The ADC is tested with each tone 6dB
below full scale.
Data hold time is the time to where the previous data (N - 1)
is no longer valid.
Data output delay time is the time to where the new data (N)
is valid.
Data Latency (tLAT)
Transient response is measured by providing a full scale
transition to the analog input of the ADC and measuring the
number of cycles it takes for the output code to settle within
10-bit accuracy.
After the analog sample is taken, the digital data representing
an analog input sample is output to the digital data bus on
the 7th cycle of the clock after the analog sample is taken.
This is due to the pipeline nature of the converter where the
analog sample has to ripple through the internal subconverter
stages. This delay is specified as the data latency. After the
data latency time, the digital data representing each
succeeding analog sample is output during the following
clock cycle. The digital data lags the analog input sample by 7
sample clock cycles.
Over-Voltage Recovery
Power-Up Initialization
Over-Voltage Recovery is measured by providing a full scale
transition to the analog input of the ADC which overdrives
the input by 200mV, and measuring the number of cycles it
takes for the output code to settle within 10-bit accuracy.
This time is defined as the maximum number of clock cycles
that are required to initialize the converter at power-up. The
requirement arises from the need to initialize the dynamic
circuits within the converter.
Transient Response
15
HI5746
A/D
AMP
HI5703
HI5746
HI5767
HFA1100
HFA1105
HFA1106
HFA1135
HFA1145
HFA1245
DSP/P
D/A
HI5780
HI1171
HI3338
HSP9501
HSP48410
HSP48908
HSP48212
HSP43891
HSP43168
HSP43216
HFA1100:
HFA1105:
HFA1106:
HFA1135:
HFA1145:
HFA1245:
HI5703:
HI5746:
HI5767:
HSP9501:
HSP48410:
850MHz Video Op Amp
300MHz Video Op Amp
250MHz Video Op Amp with Bandwidth Limit Control
350MHz Video Op Amp with Output Limiting
300MHz Video Op Amp with Output Disable
Dual, 350MHz, Video Op Amp with Output Disable
10-Bit, 40 MSPS, Low Power A/D Converter
10-Bit, 40 MSPS, Very Low Power A/D Converter
10-Bit, 40 MSPS A/D Converter with Voltage Reference
Programmable Data Buffer
Histogrammer/Accumulating Buffer, 10-Bit Pixel
Resolution
HSP48908: 2-D Convolver, 3 x 3 Kernal Convolution, 8-Bit
HSP48212:
HSP43891:
HSP43168:
HSP43216:
HI5780:
HI1171:
HI3338:
HA5020:
HA2842:
HFA1115:
HFA1212:
HFA1412:
AMP
HA5020
HA2842
HFA1115
HFA1212
HFA1412
Digital Video Mixer
Digital Filter, 30MHz, 9-Bit
Dual FIR Filter, 10-Bit, 33MHz/45MHz
Digital Half Band Filter
10-Bit, 80 MSPS, Video D/A Converter
8-Bit, 40 MSPS, Video D/A Converter
8-Bit, 50 MSPS, Video D/A Converter
100MHz Video Op Amp
High Output Current, Video Op Amp
225MHz Programmable Gain Video Buffer with
Output Limiting
350MHz Dual Programmable Gain Video Buffer
350MHz Quad Programmable Gain Video Buffer
In addition, CMOS Logic Families in HC/HCT, AC/ACT, FCT and CD4000 are available.
FIGURE 30. 10-BIT VIDEO IMAGING COMPONENTS
A/D
AMP
HI5703
HI5746
HI5767
HFA1100
HFA1110
HFA3101
HFA3102
HFA3600
DSP/P
HSP43168
HSP43216
HSP43220
HSP43891
HSP50016
HSP50110
HSP50210
D/A
HI5721
HI5780
HI20201
HI20203
AMP
HFA1112
HFA1113
HFA1100: 850MHz Op Amp
HFA1110: 750MHz Unity Gain Video Buffer
HFA3101: Gilbert Cell Transistor Array
HFA3102: Dual Long-Tailed Pair Transistor Array
HFA3600: Low Noise Amplifier/Mixer
HI5703: 10-Bit, 40 MSPS, Low Power A/D Converter
HI5746: 10-Bit, 40 MSPS, Very Low Power A/D Converter
HI5767: 10-Bit, 40 MSPS A/D Converter with Voltage Reference
HSP43168: Dual FIR Filter, 10-Bit, 33MHz/45MHz
HSP43216: Digital Half Band Filter
HSP43220: Decimating Digital Filter
HSP43891: Digital Filter, 30MHz, 9-Bit
HSP50016: Digital Down Converter
HSP50110: Digital Quadrature Tuner
HSP50210: Digital Costas Loop
HI5721: 10-Bit, 100 MSPS, Communications D/A Converter
HI5780: 10-Bit, 80 MSPS, D/A Converter
HI20201: 10-Bit, 160 MSPS, High Speed D/A Converter
HI20203: 8-Bit, 160 MSPS, High Speed D/A Converter
HFA1112: 850MHz Programmable Gain Video Buffer
HFA1113: 850MHz Programmable Gain Video Buffer with Output Limiting
In addition, CMOS Logic Families in HC/HCT, AC/ACT, FCT and CD4000 are available.
FIGURE 31. 10-BIT COMMUNICATIONS COMPONENTS
16
Similar pages