Performance Evaluation of the HI5746 Using the HI5703 Evaluation Board Semiconductor Application Note February 1999 AN9631.1 n io at rm updated info For the most 9725 N A te o N ion see Applicat ) (HI5746EVAL A/D converter with digital error correction. Figure 1 depicts Description The HI5703EVAL evaluation board can be used to evaluate the performance of the HI5746 10-bit 40 MSPS analog-todigital converter (ADC). The HI5703EVAL evaluation board is made electrically compliant with the HI5746 by making a simple resistor change in the reference voltage generation circuits allowing the former +3.25V reference generator circuit to be adjustable to +2.5V. As shown in the HI5703EVAL Evaluation Board (Modified) Block Diagram, the evaluation board includes clock driver circuitry, reference voltage generators (modified), and a choice of analog input drive circuits. Buffered digital data outputs are conveniently provided for easy interfacing to a ribbon connector or logic probes. The evaluation board is provided with some prototyping area for the addition of user designed custom interfaces or circuits. Additionally, the evaluation board is provided with eight removable jumpers to allow for various operational configurations. Refer to AN9534, “Using the HI5703 Evaluation Board”, for a complete technical discussion on the evaluation board. HI5746 A/D Theory of Operation the circuit for the converters front-end differential-in-differential-out sample-and-hold (S/H). The switches are controlled by an internal clock which is a non-overlapping two phase signal, φ1 and φ2, derived from the master clock (CLK) driving the converter. During the sampling phase, φ1, the input signal is applied to the sampling capacitors, CS. At the same time the holding capacitors, CH, are discharged to analog ground. At the falling edge of φ1 the input signal is sampled on the bottom plates of the sampling capacitors. In the next clock phase, φ2, the two bottom plates of the sampling capacitors are connected together and the holding capacitors are switched to the op amp output nodes. The charge then redistributes between CS and CH, completing one sample-and-hold cycle. The output of the sample-and-hold is a fully-differential, sampled-data representation of the analog input. The circuit not only performs the sample-and-hold function, but can also convert a single-ended input to a fullydifferential output for the converter core. During the sampling phase, the VIN pins see only the on-resistance of the switches and CS. The relatively small values of these components result in a typical full power input bandwidth of 100MHz for the HI5746 converter. The HI5746 is a 10-bit fully differential sampling pipelined HI5703EVAL Evaluation Board (Modified) Block Diagram CLK TTL COMP CLOCK OUT 50 +5VD -5.2VD CLK 2.5V REF +2.5V (PREVIOUSLY +3.25V) +2.0V VREF + EXTREF+ VREF - VIDEO 10 DOUT EXTREF- DATA OUT BUFFER 75 VIN RF IN RF XFORMER HI5746 (REPLACES HI5703) DGND AGND 50 +5VD -5.2VD +5VA 3-122 1-888-INTERSIL or 321-724-7143 | Copyright -5VA © Intersil Corporation 1999 Application Note 9631 HI5746 Functional Block Diagram VDC CLOCK BIAS CLK VINVIN+ S/H STAGE 1 DFS 2-BIT FLASH 2-BIT DAC OE + ∑ - X2 D9 (MSB) D8 D7 D6 DIGITAL DELAY AND DIGITAL ERROR CORRECTION STAGE 9 D5 D4 D3 2-BIT FLASH 2-BIT DAC D2 D1 + D0 (LSB) ∑ - X2 STAGE 10 1-BIT FLASH AVCC 3-123 AGND DVCC1 DVCC2 DVCC3 DGND VREF + VREF - Application Note 9631 The output of each of the nine identical two-bit subconverter stages is a two-bit digital word containing a supplementary bit to be used by the digital error correction logic. The output of each subconverter stage is input to a digital delay line which is controlled by the internal clock. The function of the digital delay line is to time align the digital outputs of the nine identical two-bit subconverter stages with the corresponding output of the tenth stage flash converter before inputting the nineteen-bit result into the digital error correction logic. The digital error correction logic uses the supplementary bits to correct any error that may exist before generating the final ten-bit digital data output of the converter. As illustrated in the HI5746 Functional Block Diagram and the timing diagram in Figure 2, nine identical pipeline subconverter stages, each containing a two-bit flash converter and a two-bit multiplying digital-to-analog converter, follow the front end S/H circuit with the tenth stage being a one-bit flash converter. Each converter stage in the pipeline will be sampling in one clock phase and amplifying in the other clock phase. Each individual subconverter clock signal is offset by 180 degrees from the previous stage clock signal so that alternate stages in the pipeline will perform the same operation. φ1 VIN + φ1 φ1 Because of the pipeline nature of this converter, the digital data representing an analog input sample is output on the bus at the 7th cycle of the clock after the analog sample is taken. This delay is specified as the data latency. After the data latency time, the data representing each succeeding sample is output at the following clock pulse. The output data is synchronized to the external clock by a double buffered latching technique. The output of the digital correction circuit is available in two’s complement or offset binary format depending on the condition of the Data Format Select (DFS) input. CS φ2 VIN - φ1 CH VOUT + -+ + - VOUT- CS CH φ1 φ1 FIGURE 1. ANALOG INPUT SAMPLE-AND-HOLD ANALOG INPUT CLOCK INPUT SN-1 HN-1 SN HN SN+1 HN+1 SN+2 SN+5 HN+5 SN+6 HN+6 SN+7 HN+7 SN+8 HN+8 INPUT S/H 1ST STAGE 2ND STAGE 10TH STAGE DATA OUTPUT B1, N-1 B2, N-2 B1, N B2, N-1 B1, N+1 B1, N+4 B1, N+5 B2, N+4 B2, N B10, N-5 B10, N-4 B10, N-3 B10, N DN-6 DN-5 DN-4 DN-1 B2, N+5 B10, N+1 DN tLAT NOTES: 1. SN: N-th sampling period. 2. HN: N-th holding period. 3. BM, N: M-th stage digital output corresponding to N-th sampled input. 4. DN: Final data output corresponding to N-th sampled input. FIGURE 2. HI5746 INTERNAL CIRCUIT TIMING 3-124 B1, N+6 B1, N+7 B2, N+6 B10, N+2 B10, N+3 DN+1 DN+2 Application Note 9631 Reference Voltage Generator Circuit and Modifications The HI5746 A/D contains a resistive voltage divider between the VREF + reference voltage input pin and analog ground. The divider tap is brought out to the VREF - reference voltage input pin. The A/D requires one reference voltage connected to the VREF + input pin with the other, optional, reference voltage connected to the VREF- input pin. The reference voltage that drives VREF+ must be able to source the maximum reference current, 1mA. The reference voltage that drives VREF - has minimal current drive requirements, typically <100µA. The HI5746 is tested with VREF - equal to 2V and VREF+ equal to 2.5V for a fully differential analog input voltage range of ±0.5V. In order to make the HI5703EVAL evaluation board electrically compliant with the HI5746 it is necessary to change the value of one resistor in the VREF + reference voltage generator. All that is required is to change R16 from 15kΩ to 10kΩ, refer to the evaluation board parts layout (Figure 3) and the schematics for the location of R16. This change in resistance value will allow adjustment of the VREF + reference voltage generator output from +2.2V to +3.4V thus allowing for testing of the HI5703 or HI5746. The reference circuit on the HI5703EVAL evaluation board contains a precision +2.5V reference (U4) along with operational amplifiers (U5A and U5B) that are utilized to generate the reference voltages for the HI5746. After the required modification to the value of resistor R16 the reference voltages are set to the levels required by the HI5746 as follows. The VREF- reference input is set FIRST by monitoring JP6 with a DVM and adjusting R11 until a reading of 2.0V ±5mV is obtained. Next the VREF+ reference input is set by monitoring JP5 with a DVM and adjusting R15 until a reading of 2.5V ±5mV is obtained. The reference voltages are connected to the HI5746 through the use of jumpers. Jumper JP5 is used to connect the +2.5V reference voltage and jumper JP6 is used to connect the +2.0V reference voltage. It should be noted that operation of the HI5746 with a single +2.5V voltage reference can be demonstrated by simply removing jumper JP6 thereby removing the +2.0V VREFreference voltage from the converter. RESISTOR R16 TO BE CHANGED TO 10kΩ SILKSCREEN - TOP FIGURE 3. HI5703EVAL EVALUATION BOARD GROUND LAYER 3-125 Application Note 9631 HI5703EVAL Evaluation Board Schematic Diagrams C5 RFIN 2 1 T1 4 R5 130 R8 100 + 10µF C2 R9 100 6 7, 8 VR 0.01µF CCW VIN+ JP2 AVCC2 C4 0.1µF CW DVCC1 3 2 R21 VIDEO U2 1 7 AVEE 3 23 DC HFA1102 VIN - 10 V IN VREF + 7 V REF + VREF - 8 V - R22 DVCC2 499 AVCC1 JP8 VIN + 9 V + IN VDC 11 V 39 4 R10 200 130 VIN- HI5703 REF 1 CLK U3 5 V+ 2 R6 51 3 R1 DVCC2 820 R2 R3 2K LE + 4 C1 0.1µF DVEE 820 22 TP1 DVCC2 R4 8 1K Q Q - GND V6 13 5 DVCC1 DVCC1DVCC2 AVCCAVCC R7 6 + - C3 33pF VDC (EXT) JP3 JP1 R12 10K VDC CLOCK 7 JP4 15 CLK DFS D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DGND AGND DGND DGND AGND OE 2 4 21 6 12 14 AD9696 16 17 18 19 20 24 25 26 27 28 U1 JP7 DVEE AVCC2 U5A 8 3 R14 1 2 + - 4 CA158A AVEE AVCC2 4 0.01µF 10K U4 2 VIN VOUT GND TRIM REF03 VREF + RESISTOR VALUE THAT IS CHANGED FROM 15kΩ TO 10kΩ AVCC2 5 +1.0V R11 10K 8 5 C6 0.1µF U5B R17 7 6 + - 51 4 CA158A AVEE R19 10K +2.0V JP6 + C11 10µF C8 0.01µF 3-126 C10 0.1µF R16 10K R13 8.2K 6 + C9 10µF 51 C7 R15 VR +2.5V JP5 R18 10K C12 0.1µF VREF - D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Application Note 9631 HI5703EVAL Evaluation Board Schematic Diagrams U7 D0 D1 D2 D3 D4 D5 D6 D7 2 3 4 5 6 7 8 9 1 19 P2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 A1 A2 A3 A4 A5 A6 A7 A8 (Continued) 18 17 16 15 14 13 12 11 DOUT0 DOUT1 DOUT2 DOUT3 DOUT4 DOUT5 DOUT6 DOUT7 G1 G2 74F541 DOUT0 1 DOUT1 3 DOUT2 5 DOUT3 7 DOUT4 9 DOUT5 11 DOUT6 13 DOUT7 15 DOUT8 17 DOUT9 19 21 CLKOUT 23 25 P1C 2 4 6 8 10 12 14 16 18 20 22 24 DOUT1 DOUT2 DOUT4 DOUT6 DOUT8 U8 D8 D9 CLOCK R20 1K DVCC2 2 3 4 5 6 7 8 9 1 19 A1 A2 A3 A4 A5 A6 A7 A8 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 DOUT8 18 DOUT9 17 16 CLKOUT 15 14 13 12 11 CLKOUT G1 G2 74F541 FB5 DVCC2 +5V +5V AVCC2 + C13 10µF +5V FB4 DVCC1 DVCC2 DVCC1 AVCC1 + C14 10µF +5V DGND DVEE FB6 DOUT3 DOUT5 DOUT7 DOUT9 FB1 AVCC2 FB3 AVCC1 FB2 AVEE + C29 10µF AVEE -5V DVCC2 DVCC1 C18 0.1µF U1 C17 0.1µF U1 AVCC1 C21 0.1µF U6 DVEE C31 0.1µF U3 C22 0.1µF U7 AVCC2 C24 0.1µF U1 3-127 DOUT0 + C28 10µF + C30 10µF DVEE -5.2V C23 0.1µF U1 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 AGND + C15 10µF C16 0.1µF U1 P1A C25 0.1µF U2 C26 0.1µF U5 C27 0.1µF U3 AVEE C32 0.1µF U4 C19 0.1µF U2 C20 0.1µF U5 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 Application Note 9631 HI5703EVAL Evaluation Board Parts List REFERENCE DESIGNATOR QTY DESCRIPTION R4, R20 2 1kΩ, 1/8W, 5% R1, R3 2 820Ω, 1/8W, 5% R6, R14, R17 3 51Ω, 1/8W, 5% R18, R19 2 10kΩ, 1/8W, 5% R8, R9 2 100Ω, 1/8W, 5% R7 1 39Ω, 1/8W, 5% R21 1 200Ω, 1/8W, 5% R16 1 10kΩ, 1/8W, 5% (previously 15K) R13 1 8.2kΩ, 1/8W, 5% R5, R10 2 130Ω, 1/4W, 5% R22 1 499Ω, 1206 CHIP R2 1 2kΩ Trim Pot R12, R11, R15 3 10kΩ Trim Pot C5, C9, C11, C13, C14, C15, C19, C25, C28, C29, C30 11 10µF Tant Cap, 35WVDC, 20% C2, C7, C8 3 0.01µF Ceramic Cap, 100WVDC, 10% C33, C34 2 1000pF 1206 Chip Cap, 50WVDC, XR7 10% C1, C4, C6, C20, C26, C27, C31 7 0.1µF Ceramic Cap, 50WVDC, 10% C10, C12, C16, C17, C18, C21, C22, C23, C24, C32 10 0.1µF 1206 Chip Cap, 50WVDC, Z5U, 20% C3 1 33pF 1206 Chip Cap, 100WVDC, COG(NPO), 5% FB1-6 6 10µH Ferrite Bead T1 1 RF Transformer TP1 1 Probe Tip Adapter JP1-8 8 1 x 2 Header J1-8 8 1 x 2 Header Jumper P2 1 2 x 13 Header VDC, AGND, DGND 3 Test Point P1 1 64-Lead DIN RT Angle SMA1-3 3 SMA, Straight Female Jack PCB MNT SU2-5, ST1 5 8-Lead Socket SU6-7 2 20-Lead Socket U1 1 Intersil HI5703KCB 10-Bit 40MHz A/D Converter U2 1 Intersil HFA1102IP Operational Amplifier U3 1 Ultrafast Voltage Comparator U4 1 +2.5V Precision Voltage Reference U5 1 Intersil CA158AE Operational Amplifier U6-7 2 Octal Buffer/Line Driver 3-128