DATASHEET

Data Sheet
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TERSIL
1-888-IN
10-Bit, 20/40/60MSPS A/D Converter with
Internal Voltage Reference
Features
The HI5767 is a monolithic, 10-bit, analog-to-digital
converter fabricated in a CMOS process. It is designed for
high speed applications where wide bandwidth and low
power consumption are essential. Its high sample clock
rate is made possible by a fully differential pipelined
architecture with both an internal sample and hold and
internal band-gap voltage reference.
• 8.8 Bits at fIN = 10MHz, fS = 40MSPS
The 250MHz Full Power Input Bandwidth and superior high
frequency performance of the HI5767 converter make it an
excellent choice for implementing Digital IF architectures in
communications applications.
The HI5767 has excellent dynamic performance while
consuming only 310mW power at 40MSPS. Data output
latches are provided which present valid data to the output
bus with a latency of 7 clock cycles.
FN4319.6
• Sampling Rate . . . . . . . . . . . . . . . . . . . . . . 20/40/60MSPS
• Low Power at 40MSPS . . . . . . . . . . . . . . . . . . . . .310mW
• Wide Full Power Input Bandwidth . . . . . . . . . . . . 250MHz
• On-Chip Sample and Hold
• Internal 2.5V Band-Gap Voltage Reference
• Fully Differential or Single-Ended Analog Input
• Single Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . .+5V
• TTL/CMOS Compatible Digital Inputs
• CMOS Compatible Digital Outputs. . . . . . . . . . . 3.0V/5.0V
• Offset Binary or Two’s Complement Output Format
• Pb-Free Available (RoHS Compliant)
Applications
The HI5767 is offered in 20MSPS, 40MSPS and 60MSPS
sampling rates.
• Digital Communication Systems
Pinout
• Professional Video Digitizing
HI5767 (SOIC, SSOP)
TOP VIEW
HI5767
• QAM Demodulators
• Medical Imaging
• High Speed Data Acquisition
DVCC1 1
28 D0
DGND 2
27 D1
DVCC1 3
26 D2
DGND 4
25 D3
AVCC 5
AGND 6
24 D4
23 DVCC2
22 CLK
VREFIN 7
21 DGND
VREFOUT 8
VIN+ 9
20 D5
VIN- 10
19 D6
VDC 11
AGND 12
18 D7
AVCC 13
16 D9
17 D8
15 DFS
OE 14
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HI5767
Ordering Information
PART
NUMBER
TEMP.
RANGE
(oC)
PACKAGE
PKG.
DWG. #
SAMPLING
RATE
(MSPS)
HI5767/2CB
0 to 70
28 Ld SOIC
M28.3
20
HI5767/2CBZ
(See Note)
0 to 70
28 Ld SOIC
(Pb-free)
M28.3
20
HI5767/4CB*
0 to 70
28 Ld SOIC
M28.3
40
HI5767/4CBZ*
(See Note)
0 to 70
28 Ld SOIC
(Pb-free)
M28.3
40
HI5767/6CB*
0 to 70
28 Ld SOIC
M28.3
60
HI5767/6CBZ*
(See Note)
0 to 70
28 Ld SOIC
(Pb-free)
M28.3
60
HI5767/6IB
-40 to 85 28 Ld SOIC
M28.3
60
HI5767/6IBZ
(See Note)
-40 to 85 28 Ld SOIC
(Pb-free)
M28.3
60
HI5767/2CA
0 to 70
28 Ld SSOP
M28.15
20
HI5767/2CAZ
(See Note)
0 to 70
28 Ld SSOP
(Pb-free)
M28.15
20
HI5767/2IA
-40 to 85 28 Ld SSOP
M28.15
20
HI5767/2IAZ
(See Note)
-40 to 85 28 Ld SSOP
(Pb-free)
M28.15
20
HI5767/4CA
0 to 70
28 Ld SSOP
M28.15
40
HI5767/4CAZ
(See Note)
0 to 70
28 Ld SSOP
(Pb-free)
M28.15
40
HI5767/6CA
0 to 70
28 Ld SSOP
M28.15
60
HI5767/6CAZ
(See Note)
0 to 70
28 Ld SSOP
(Pb-free)
M28.15
60
HI5767EVAL1
25
Evaluation Board
60
HI5767EVAL2
25
Evaluation Board
60
* Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2
HI5767
Functional Block Diagram
VDC
CLOCK
BIAS
CLK
VINVIN+
REFERENCE
S/H
VREFOUT
VREFIN
STAGE 1
DFS
2-BIT
FLASH
2-BIT
DAC
OE
+

DVCC2
X2
D9 (MSB)
D8
D7
D6
DIGITAL DELAY
AND
DIGITAL ERROR
CORRECTION
STAGE 8
D5
D4
D3
2-BIT
FLASH
2-BIT
DAC
D2
D1
+

D0 (LSB)
-
X2
DGND2
STAGE 9
2-BIT
FLASH
AVCC
3
AGND
DVCC1
DGND1
HI5767
Typical Application Schematic
HI5767
0.1F
VREFIN (7)
VREFOUT (8)
(LSB) (28) D0
D0
(27) D1
D1
(26) D2
D2
(25) D3
D3
(24) D4
D4
DGND1 (2)
(20) D5
D5
DGND1 (4)
(19) D6
D6
DGND2 (21)
(18) D7
D7
(17) D8
D8
(MSB) (16) D9
D9
AGND (12)
AGND (6)
VIN +
VIN + (9)
VIN -
CLOCK
(3) DVCC1
VIN - (10)
(23) DVCC2
CLK (22)
(13) AVCC
DFS (15)
(5) AVCC
AGND
BNC
10F AND 0.1F CAPS
ARE PLACED AS CLOSE
TO PART AS POSSIBLE
(1) DVCC1
VDC (11)
DGND
OE (14)
0.1F
+
10F
0.1F
+
10F
+5V
+5V
Pin Descriptions
PIN NO.
NAME
Digital Supply (+5.0V)
15
DFS
Data Format Select Input
DGND1
Digital Ground
16
D9
Data Bit 9 Output (MSB)
3
DVCC1
Digital Supply (+5.0V)
17
D8
Data Bit 8 Output
4
DGND1
Digital Ground
18
D7
Data Bit 7 Output
5
AVCC
Analog Supply (+5.0V)
19
D6
Data Bit 6 Output
6
AGND
Analog Ground
20
D5
Data Bit 5 Output
7
VREFIN
+2.5V Reference Voltage Input
21
DGND2
8
VREFOUT
+2.5V Reference Voltage Output
22
CLK
9
VIN+
Positive Analog Input
23
DVCC2
10
VIN-
Negative Analog Input
24
D4
Data Bit 4 Output
11
VDC
DC Bias Voltage Output
25
D3
Data Bit 3 Output
12
AGND
Analog Ground
26
D2
Data Bit 2 Output
13
AVCC
Analog Supply (+5.0V)
27
D1
Data Bit 1 Output
14
OE
Digital Output Enable Control Input
28
D0
Data Bit 0 Output (LSB)
PIN NO.
NAME
1
DVCC1
2
DESCRIPTION
4
DESCRIPTION
Digital Ground
Sample Clock Input
Digital Output Supply (+3.0V or +5.0V)
HI5767
Absolute Maximum Ratings TA = 25oC
Thermal Information
Supply Voltage, AVCC or DVCC to AGND or DGND . . . . . . . . . . .6V
DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V
Digital I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND to DVCC
Analog I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND to AVCC
Thermal Resistance (Typical, Note 1)
Operating Conditions
Temperature Range
HI5767/xCx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
HI5767/xIx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
JA (oC/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
AVCC = DVCC1 = 5.0V, DVCC2 = 3.0V; VREFIN = VREFOUT; fS = 40MSPS at 50% Duty Cycle;
CL = 10pF; TA = 25oC; Differential Analog Input; Typical Values are Test Results at 25oC,
Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
10
-
-
Bits
ACCURACY
Resolution
Integral Linearity Error, INL
fIN = 1MHz Sinewave
-
0.75
1.75
LSB
Differential Linearity Error, DNL
(Guaranteed No Missing Codes)
fIN = 1MHz Sinewave
-
0.35
1.0
LSB
Offset Error, VOS
fIN = DC
-40
-
40
LSB
Full Scale Error, FSE
fIN = DC
-
4
-
LSB
No Missing Codes
-
0.5
1
MSPS
HI5767/2
No Missing Codes
20
-
-
MSPS
HI5767/4
No Missing Codes
40
-
-
MSPS
HI5767/6
No Missing Codes
60
-
-
MSPS
HI5767/2
fS = 20MSPS, fIN = 10MHz
8.7
9
-
Bits
HI5767/4
fS = 40MSPS, fIN = 10MHz
8.55
8.8
-
Bits
HI5767/6
fS = 60MSPS, fIN = 10MHz
8.1
8.4
-
Bits
HI5767/2
fS = 20MSPS, fIN = 10MHz
-
55.9
-
dB
HI5767/4
fS = 40MSPS, fIN = 10MHz
-
54.7
-
dB
HI5767/6
fS = 60MSPS, fIN = 10MHz
-
53.8
-
dB
HI5767/2
fS = 20MSPS, fIN = 10MHz
-
55.9
-
dB
HI5767/4
fS = 40MSPS, fIN = 10MHz
-
55
-
dB
HI5767/6
fS = 60MSPS, fIN = 10MHz
-
54
-
dB
fS = 20MSPS, fIN = 10MHz
-
-71
-
dBc
DYNAMIC CHARACTERISTICS
Minimum Conversion Rate
Maximum Conversion Rate
Effective Number of Bits, ENOB
Signal to Noise and Distortion Ratio, SINAD
RMS Signal
= -------------------------------------------------------------RMS Noise + Distortion
Signal to Noise Ratio, SNR
RMS Signal
= ------------------------------RMS Noise
Total Harmonic Distortion, THD
HI5767/2
5
HI5767
Electrical Specifications
AVCC = DVCC1 = 5.0V, DVCC2 = 3.0V; VREFIN = VREFOUT; fS = 40MSPS at 50% Duty Cycle;
CL = 10pF; TA = 25oC; Differential Analog Input; Typical Values are Test Results at 25oC,
Unless Otherwise Specified (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
HI5767/4
fS = 40MSPS, fIN = 10MHz
-
-65
-
dBc
HI5767/6
fS = 60MSPS, fIN = 10MHz
-
-64.5
-
dBc
HI5767/2
fS = 20MSPS, fIN = 10MHz
-
-76
-
dBc
HI5767/4
fS = 40MSPS, fIN = 10MHz
-
-73
-
dBc
HI5767/6
fS = 60MSPS, fIN = 10MHz
-
-70
-
dBc
HI5767/2
fS = 20MSPS, fIN = 10MHz
-
-80
-
dBc
HI5767/4
fS = 40MSPS, fIN = 10MHz
-
-69
-
dBc
HI5767/6
fS = 60MSPS, fIN = 10MHz
-
-67
-
dBc
HI5767/2
fS = 20MSPS, fIN = 10MHz
-
76
-
dBc
HI5767/4
fS = 40MSPS, fIN = 10MHz
-
69
-
dBc
HI5767/6
2nd Harmonic Distortion
3rd Harmonic Distortion
Spurious Free Dynamic Range, SFDR
fS = 60MSPS, fIN = 10MHz
-
67
-
dBc
Intermodulation Distortion, IMD
f1 = 1MHz, f2 = 1.02MHz
-
64
-
dBc
Differential Gain Error
fS = 17.72MHz, 6 Step, Mod Ramp
-
0.5
-
%
Differential Phase Error
fS = 17.72MHz, 6 Step, Mod Ramp
-
0.2
-
Degree
Transient Response
(Note 2)
-
1
-
Cycle
Over-Voltage Recovery
0.2V Overdrive (Note 2)
-
1
-
Cycle
Maximum Peak-to-Peak Differential Analog Input
Range (VIN+ - VIN-)
-
0.5
-
V
Maximum Peak-to-Peak Single-Ended
Analog Input Range
-
1.0
-
V
(Note 3)
-
1
-
M
-
10
-
pF
Analog Input Bias Current, IB+ or IB-
(Note 3)
-10
-
+10
A
Differential Analog Input Bias Current
IBDIFF = (IB+ - IB-)
(Note 3)
-
0.5
-
A
ANALOG INPUT
Analog Input Resistance, RIN
Analog Input Capacitance, CIN
Full Power Input Bandwidth, FPBW
-
250
-
MHz
0.25
-
4.75
V
Reference Voltage Output, VREFOUT (Loaded)
-
2.5
-
V
Reference Output Current, IREFOUT
-
1
2
mA
Reference Temperature Coefficient
-
120
-
ppm/oC
Reference Voltage Input, VREFIN
-
2.5
-
V
Total Reference Resistance, RREFIN
-
2.5
-
k
Reference Input Current, IREFIN
-
1
-
mA
-
3.0
-
V
Analog Input Common Mode Voltage Range
(VIN+ + VIN-) / 2
Differential Mode (Note 2)
INTERNAL REFERENCE VOLTAGE
REFERENCE VOLTAGE INPUT
DC BIAS VOLTAGE
DC Bias Voltage Output, VDC
6
HI5767
Electrical Specifications
AVCC = DVCC1 = 5.0V, DVCC2 = 3.0V; VREFIN = VREFOUT; fS = 40MSPS at 50% Duty Cycle;
CL = 10pF; TA = 25oC; Differential Analog Input; Typical Values are Test Results at 25oC,
Unless Otherwise Specified (Continued)
PARAMETER
TEST CONDITIONS
Maximum Output Current
MIN
TYP
MAX
UNITS
-
-
0.2
mA
DIGITAL INPUTS
Input Logic High Voltage, VIH
CLK, DFS, OE
2.0
-
-
V
Input Logic Low Voltage, VIL
CLK, DFS, OE
-
-
0.8
V
Input Logic High Current, IIH
CLK, DFS, OE, VIH = 5V
-10.0
-
+10.0
A
Input Logic Low Current, IIL
CLK, DFS, OE, VIL = 0V
-10.0
-
+10.0
A
-
7
-
pF
Input Capacitance, CIN
DIGITAL OUTPUTS
Output Logic High Voltage, VOH
IOH = 100A; DVCC2 = 5V
4.0
-
-
V
Output Logic Low Voltage, VOL
IOL = 100A; DVCC2 = 5V
-
-
0.8
V
Output Three-State Leakage Current, IOZ
VO = 0/5V; DVCC2 = 5V
-10
1
10
A
Output Logic High Voltage, VOH
IOH = 100A; DVCC2 = 3V
2.4
-
-
V
Output Logic Low Voltage, VOL
IOL = 100A; DVCC2 = 3V
-
-
0.5
V
Output Three-State Leakage Current, IOZ
VO = 0/5V; DVCC2 = 3V
-10
1
10
A
-
10
-
pF
Aperture Delay, tAP
-
5
-
ns
Aperture Jitter, tAJ
-
5
-
psRMS
Data Output Hold, tH
-
5
-
ns
Data Output Delay, tOD
-
6
-
ns
Data Output Enable Time, tEN
-
5
-
ns
Data Output Enable Time, tDIS
-
5
-
ns
Output Capacitance, COUT
TIMING CHARACTERISTICS
Data Latency, tLAT
For a Valid Sample (Note 2)
-
-
7
Cycles
Power-Up Initialization
Data Invalid Time (Note 2)
-
-
20
Cycles
Sample Clock Pulse Width (Low)
fS = 40MSPS
11.3
12.5
-
ns
Sample Clock Pulse Width (High)
fS = 40MSPS
11.3
12.5
-
ns
Sample Clock Duty Cycle Variation
fS = 40MSPS
-
5
-
%
4.75
5.0
5.25
V
POWER SUPPLY CHARACTERISTICS
Analog Supply Voltage, AVCC
Digital Supply Voltage, DVCC1
Digital Output Supply Voltage, DVCC2
4.75
5.0
5.25
V
At 3.0V
2.7
3.0
3.3
V
At 5.0V
4.75
5.0
5.25
V
Supply Current, ICC
fIN = 1MHz and DFS = “0”
-
62
-
mA
Power Dissipation
fIN = 1MHz and DFS = “0”
-
310
-
mW
Offset Error Sensitivity, VOS
AVCC or DVCC = 5V 5%
-
0.7
-
LSB
Gain Error Sensitivity, FSE
AVCC or DVCC = 5V 5%
-
0.1
-
LSB
NOTES:
2. Parameter guaranteed by design or characterization and not production tested.
3. With the clock low and DC input.
7
HI5767
Timing Waveforms
ANALOG
INPUT
tAP
tAJ
CLOCK
INPUT
1.5V
1.5V
tOD
tH
2.4V
DATA
OUTPUT
DATA N-1
DATA N
0.5V
FIGURE 1. INPUT TO OUTPUT TIMING
Typical Performance Curves
59
9.5
fIN = 1MHz
9.0
60
fIN = 5MHz
fIN = 1MHz
fIN = 5MHz
fIN = 10MHz
8.0
fIN = 15MHz
47
7.5
SNR (dB)
53
8.5
SINAD (dB)
ENOB (BITS)
55
50
fIN = 10MHz
45
fIN = 15MHz
7.0
TA = 25oC
6.5
10
20
TA = 25oC
30
40
50
60
41
80
70
40
10
20
SAMPLING FREQUENCY (MSPS)
FIGURE 2. EFFECTIVE NUMBER OF BITS (ENOB) AND
SINAD vs SAMPLING FREQUENCY
80
75
60
70
80
fIN = 1MHz
fIN = 5MHz
fIN = 5MHz
70
SFDR (dBc)
70
-THD (dBc)
50
75
fIN = 1MHz
65
fIN = 10MHz
55
20
30
40
50
60
fIN = 10MHz
60
TA = 25oC
70
SAMPLING FREQUENCY (MSPS)
FIGURE 4. -THD vs SAMPLING FREQUENCY
8
fIN = 15MHz
65
55
fIN = 15MHz
TA = 25oC
50
10
40
FIGURE 3. SNR vs SAMPLING FREQUENCY
80
60
30
SAMPLING FREQUENCY (MSPS)
80
50
10
20
30
40
50
60
70
SAMPLING FREQUENCY (MSPS)
FIGURE 5. SFDR vs SAMPLING FREQUENCY
80
HI5767
Typical Performance Curves
(Continued)
9.5
9.1
20MSPS
9.0
9.0
40MSPS
8.0
60MSPS
7.5
20MSPS
8.9
ENOB (BITS)
ENOB (BITS)
8.5
7.0
8.8
TA = 25oC, fIN = 10MHz
DIFFERENTIAL ANALOG INPUT
8.7
8.6
40MSPS
6.5
8.5
6.0
5.5
30
8.4
TA = 25oC, fIN = 10MHz
35
40
45
50
55
60
65
60MSPS
8.3
0.25 0.75
70
1.25
1.75
DUTY CYCLE (%, tH/tCLK)
3.25
3.75
4.25
4.75
FIGURE 7. EFFECTIVE NUMBER OF BITS (ENOB) vs
ANALOG INPUT COMMON MODE VOLTAGE
80
9.2
20MSPS
ICC
70
9.0
60
AICC
50
40
30
ENOB (BITS)
SUPPLY CURRENT (mA)
2.75
VCM (V)
FIGURE 6. EFFECTIVE NUMBER OF BITS (ENOB) vs
SAMPLE CLOCK DUTY CYCLE
TA = 25oC, 1MHz < fIN < 15MHz
0
10
8.8
40MSPS
8.6
8.4
DICC1
20
60MSPS
fIN = 10MHz, VREFIN = VREFOUT
DIFFERENTIAL ANALOG INPUT
8.2
10
DICC2
15
20
25
30
35
40
45
50
55
8.0
-40
60
-20
0
20
40
60
80
TEMPERATURE (oC)
fS (MSPS)
FIGURE 8. SUPPLY CURRENT vs SAMPLE CLOCK
FREQUENCY
FIGURE 9. EFFECTIVE NUMBER OF BITS (ENOB) vs
TEMPERATURE
2.530
3.1
2.525
VREFOUT
VDC (V)
REFERENCE VOLTAGE, (VREFOUT) (V)
2.25
2.520
3.0
VDC
2.515
2.510
-40
-20
0
20
40
60
80
TEMPERATURE (oC)
FIGURE 10. INTERNAL REFERENCE VOLTAGE (VREFOUT) vs
TEMPERATURE
9
2.9
-40
-20
0
20
40
60
80
TEMPERATURE (oC)
FIGURE 11. DC BIAS VOLTAGE (VDC) vs TEMPERATURE
HI5767
Typical Performance Curves
(Continued)
6.5
80
ICC
SUPPLY CURRENT (mA)
70
6.0
tOD (ns)
tOD
5.5
5.0
60
50
30
-20
0
20
60
40
80
60MSPS, fIN = 10MHz,
AVCC = DVCC1 = 5V
DVCC2 = 3V
DICC1
20
10
4.5
-40
AICC
40
DICC2
0
-40
-20
0
TEMPERATURE (oC)
20
60
40
TEMPERATURE (oC)
FIGURE 12. DATA OUTPUT DELAY (tOD) vs TEMPERATURE
FIGURE 13. SUPPLY CURRENT vs TEMPERATURE
0
-10
OUTPUT LEVEL (dB)
-20
-30
1
TA = 25oC, fS = 60MSPS, fIN = 10MHz
-40
VIN+
-50
-70
VIN-
-80
-90
0
100
200
300
400
500
600
700
800
900
1
CH
1
CS
2
-60
-100
1
-+
VOUT+
+-
VOUT-
CS
1
CH
1
1023
FREQUENCY (BIN)
FIGURE 14. 2048 POINT FFT PLOT
10
FIGURE 15. ANALOG INPUT SAMPLE-AND-HOLD
80
HI5767
TABLE 1. A/D CODE TABLE
OFFSET BINARY OUTPUT CODE
(DFS LOW)
M
S
B
TWO’S COMPLEMENT OUTPUT CODE
(DFS HIGH)
L
S
B
M
S
B
L
S
B
DIFFERENTIAL
INPUT VOLTAGE
(VIN+ - VIN-)
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
+Full Scale (+FS) 1/ LSB
4
0.499756V
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
+FS - 11/4 LSB
0.498779V
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
0
+3/4 LSB
-1/4 LSB
-FS + 13/4 LSB
732.422V
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-244.141V
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
-0.498291V
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
-0.499268V
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
CODE CENTER
DESCRIPTION
-Full Scale (-FS) +
3/ LSB
4
NOTE:
4. The voltages listed above represent the ideal center of each output code shown with VREFIN = +2.5V.
Detailed Description
Theory of Operation
The HI5767 is a 10-bit fully differential sampling pipeline A/D
converter with digital error correction logic. Figure 16 depicts
the circuit for the front end differential-in-differential-out sampleand-hold (S/H). The switches are controlled by an internal
sampling clock which is a non-overlapping two phase signal1
and 2 , derived from the master sampling clock. During the
sampling phase, 1 , the input signal is applied to the sampling
capacitors, CS . At the same time the holding capacitors, CH ,
are discharged to analog ground. At the falling edge of 1 the
input signal is sampled on the bottom plates of the sampling
capacitors. In the next clock phase,2 , the two bottom plates
of the sampling capacitors are connected together and the
holding capacitors are switched to the op-amp output nodes.
The charge then redistributes between CS and CH completing
one sample-and-hold cycle. The front end sample-and-hold
output is a fully-differential, sampled-data representation of the
analog input. The circuit not only performs the sample-and-hold
function but will also convert a single-ended input to a fullydifferential output for the converter core. During the sampling
phase, the VIN pins see only the on-resistance of a switch and
CS . The relatively small values of these components result in a
typical full power input bandwidth of 250MHz for the converter.
As illustrated in the functional block diagram and the timing
diagram in Figure 1, eight identical pipeline subconverter
stages, each containing a two-bit flash converter and a twobit multiplying digital-to-analog converter, follow the S/H
circuit with the ninth stage being a two bit flash converter.
Each converter stage in the pipeline will be sampling in one
phase and amplifying in the other clock phase. Each
individual subconverter clock signal is offset by 180 degrees
from the previous stage clock signal resulting in alternate
stages in the pipeline performing the same operation.
11
The output of each of the eight identical two-bit subconverter
stages is a two-bit digital word containing a supplementary bit
to be used by the digital error correction logic. The output of
each subconverter stage is input to a digital delay line which is
controlled by the internal sampling clock. The function of the
digital delay line is to time align the digital outputs of the eight
identical two-bit subconverter stages with the corresponding
output of the ninth stage flash converter before applying the
eighteen bit result to the digital error correction logic. The
digital error correction logic uses the supplementary bits to
correct any error that may exist before generating the final ten
bit digital data output of the converter.
Because of the pipeline nature of this converter, the digital data
representing an analog input sample is output to the digital data
bus on the 7th cycle of the clock after the analog sample is
taken. This time delay is specified as the data latency. After the
data latency time, the digital data representing each
succeeding analog sample is output during the following clock
cycle. The digital output data is synchronized to the external
sampling clock by a double buffered latching technique. The
digital output data is available in two’s complement or offset
binary format depending on the state of the Data Format Select
(DFS) control input (see Table 1, A/D Code Table).
Internal Reference Voltage Output, VREFOUT
The HI5767 is equipped with an internal reference voltage
generator, therefore, no external reference voltage is required.
VREFOUT must be connected to VREFIN when using the
internal reference voltage.
An internal band-gap reference voltage followed by an
amplifier/buffer generates the precision +2.5V reference
voltage used by the converter. A 4:1 array of substrate
PNPs generates the “delta-VBE” and a two-stage op-amp
closes the loop to create an internal +1.25V band-gap
reference voltage. This voltage is then amplified by a
wideband uncompensated operational amplifier connected
HI5767
in a gain-of-two configuration. An external, user-supplied,
0.1F capacitor connected from the VREFOUT output pin to
analog ground is used to set the dominant pole and to
maintain the stability of the operational amplifier.
Reference Voltage Input, VREFIN
The HI5767 is designed to accept a +2.5V reference voltage
source at the VREF IN input pin. Typical operation of the
converter requires VREFIN to be set at +2.5V. The HI5767 is
tested with VREFIN connected to VREFOUT yielding a fully
differential analog input voltage range of 0.5V.
The user does have the option of supplying an external
+2.5V reference voltage. As a result of the high input
impedance presented at the VREFIN input pin, 2.5k
typically, the external reference voltage being used is only
required to source 1mA of reference input current. In the
situation where an external reference voltage will be used
an external 0.1F capacitor must be connected from the
VREFOUT output pin to analog ground in order to maintain
the stability of the internal operational amplifier.
In order to minimize overall converter noise it is
recommended that adequate high frequency decoupling be
provided at the reference voltage input pin, VREFIN .
Analog Input, Differential Connection
The analog input to the HI5767 is a differential input that can
be configured in various ways depending on the signal
source and the required level of performance. A fully
differential connection (Figure 17 and Figure 18) will deliver
the best performance from the converter.
VIN+
VIN
R
The analog input can be DC coupled (Figure 18) as long as
the inputs are within the analog input common mode voltage
range (0.25V  VDC  4.75V).
VIN
VIN+
VDC
R
C
HI5767
VDC
R
-VIN
VDC
VIN-
FIGURE 17. DC COUPLED DIFFERENTIAL INPUT
The resistors, R, in Figure 18 are not absolutely necessary
but may be used as load setting resistors. A capacitor, C,
connected from VIN+ to VIN- will help filter any high
frequency noise on the inputs, also improving performance.
Values around 20pF are sufficient and can be used on AC
coupled inputs as well. Note, however, that the value of
capacitor C chosen must take into account the highest
frequency component of the analog input signal.
Analog Input, Single-Ended Connection
The configuration shown in Figure 19 may be used with a
single ended AC coupled input.
HI5767
VDC
R
-VIN
the VIN and -VIN input signals are 0.5VP- P, with -VIN being
180 degrees out of phase with VIN . The converter will be at
positive full scale when the VIN+ input is at VDC + 0.25V and
the VIN- input is at VDC - 0.25V (VIN+ - VIN- = +0.5V).
Conversely, the converter will be at negative full scale when
the VIN+ input is equal to VDC - 0.25V and VIN- is at
VDC + 0.25V (VIN+ - VIN- = -0.5V).
VIN+
VIN
R
VDC
VIN-
HI5767
VIN-
FIGURE 16. AC COUPLED DIFFERENTIAL INPUT
Since the HI5767 is powered by a single +5V analog supply,
the analog input is limited to be between ground and +5V.
For the differential input connection this implies the analog
input common mode voltage can range from 0.25V to 4.75V.
The performance of the ADC does not change significantly
with the value of the analog input common mode voltage.
A DC voltage source, VDC , equal to 3.2V (typical), is made
available to the user to help simplify circuit design when using
an AC coupled differential input. This low output impedance
voltage source is not designed to be a reference but makes
an excellent DC bias source and stays well within the analog
input common mode voltage range over temperature.
For the AC coupled differential input (Figure 17) and with
VREFIN connected to VREFOUT, full scale is achieved when
12
FIGURE 18. AC COUPLED SINGLE ENDED INPUT
Again, with VREFIN connected to VREFOUT, if VIN is a 1VP-P
sinewave, then VIN+ is a 1.0VP-P sinewave riding on a positive
voltage equal to VDC. The converter will be at positive full scale
when VIN+ is at VDC + 0.5V (VIN+ - VIN- = +0.5V) and will be at
negative full scale when VIN+ is equal to VDC - 0.5V (VIN+ - VIN= -0.5V). Sufficient headroom must be provided such that the
input voltage never goes above +5V or below AGND. In this
case, VDC could range between 0.5V and 4.5V without a
significant change in ADC performance. The simplest way to
produce VDC is to use the DC bias source, VDC, output of the
HI5767.
HI5767
The single ended analog input can be DC coupled
(Figure 20) as long as the input is within the analog input
common mode voltage range.
VIN
VIN+
VDC
R
HI5767
C
VDC
VIN-
FIGURE 19. DC COUPLED SINGLE ENDED INPUT
The resistor, R, in Figure 20 is not absolutely necessary but
may be used as a load setting resistor. A capacitor, C,
connected from VIN+ to VIN- will help filter any high
frequency noise on the inputs, also improving performance.
Values around 20pF are sufficient and can be used on AC
coupled inputs as well. Note, however, that the value of
capacitor C chosen must take into account the highest
frequency component of the analog input signal.
A single ended source may give better overall system
performance if it is first converted to differential before
driving the HI5767.
Digital Output Control and Clock Requirements
The HI5767 provides a standard high-speed interface to
external TTL logic families.
pin, DVCC2 , which can be powered from a 3.0V or 5.0V
supply. This allows the outputs to interface with 3.0V logic if
so desired.
The part should be mounted on a board that provides separate
low impedance connections for the analog and digital supplies
and grounds. For best performance, the supplies to the HI5767
should be driven by clean, linear regulated supplies. The board
should also have good high frequency decoupling capacitors
mounted as close as possible to the converter. If the part is
powered off a single supply, then the analog supply should be
isolated with a ferrite bead from the digital supply.
Refer to the application note “Using Intersil High Speed A/D
Converters” (AN9214) for additional considerations when
using high speed converters.
Static Performance Definitions
Offset Error (VOS)
The midscale code transition should occur at a level 1/4 LSB
above half-scale. Offset is defined as the deviation of the
actual code transition from this point.
Full-Scale Error (FSE)
The last code transition should occur for an analog input that
is 3/4 LSB below Positive Full Scale (+FS) with the offset
error removed. Full scale error is defined as the deviation of
the actual code transition from this point.
Differential Linearity Error (DNL)
In order to ensure rated performance of the HI5767, the duty
cycle of the clock should be held at 50% 5%. It must also
have low jitter and operate at standard TTL levels.
DNL is the worst case deviation of a code width from the
ideal value of 1 LSB.
Performance of the HI5767 will only be guaranteed at
conversion rates above 1 MSPS. This ensures proper
performance of the internal dynamic circuits. Similarly, when
power is first applied to the converter, a maximum of 20
cycles at a sample rate above 1 MSPS will have to be
performed before valid data is available.A Data Format
Select (DFS) pin is provided which will determine the format
of the digital data outputs. When at logic low, the data will be
output in offset binary format. When at logic high, the data
will be output in two’s complement format. Refer to Table 1
for further information.
INL is the worst case deviation of a code center from a best
fit straight line calculated from the measured data.
The output enable pin, OE, when pulled high will three-state
the digital outputs to a high impedance state. Set the OE
input to logic low for normal operation.
OE INPUT
DIGITAL DATA OUTPUTS
0
Active
1
High Impedance
Supply and Ground Considerations
The HI5767 has separate analog and digital supply and
ground pins to keep digital noise out of the analog signal
path. The digital data outputs also have a separate supply
13
Integral Linearity Error (INL)
Power Supply Sensitivity
Each of the power supplies are moved plus and minus 5% and
the shift in the offset and full scale error (in LSBs) is noted.
Dynamic Performance Definitions
Fast Fourier Transform (FFT) techniques are used to evaluate
the dynamic performance of the HI5767. A low distortion sine
wave is applied to the input, it is coherently sampled, and the
output is stored in RAM. The data is then transformed into the
frequency domain with an FFT and analyzed to evaluate the
dynamic performance of the A/D. The sine wave input to the
part is typically -0.5dB down from full scale for all these tests.
SNR and SINAD are quoted in dB. The distortion numbers are
quoted in dBc (decibels with respect to carrier) and DO NOT
include any correction factors for normalizing to full scale.
The Effective Number of Bits (ENOB) is calculated from the
SINAD data by:
ENOB = (SINAD - 1.76 + VCORR) / 6.02,
HI5767
where: VCORR = 0.5 dB (Typical).
Intermodulation Distortion (IMD)
VCORR adjusts the SINAD, and hence the ENOB, for the
amount the analog input signal is backed off from full scale.
SINAD is the ratio of the measured RMS signal to RMS sum
of all the other spectral components below the Nyquist
frequency, fS/2, excluding DC.
Nonlinearities in the signal path will tend to generate
intermodulation products when two tones, f1 and f2 , are
present at the inputs. The ratio of the measured signal to the
distortion terms is calculated. The terms included in the
calculation are (f1+f2), (f1-f2), (2f1), (2f2), (2f1+f2), (2f1-f2),
(f1+2f2), (f1-2f2). The ADC is tested with each tone 6dB
below full scale.
Signal To Noise Ratio (SNR)
Transient Response
SNR is the ratio of the measured RMS signal to RMS noise at
a specified input and sampling frequency. The noise is the
RMS sum of all of the spectral components below fS /2
excluding the fundamental, the first five harmonics and DC.
Transient response is measured by providing a full-scale
transition to the analog input of the ADC and measuring the
number of cycles it takes for the output code to settle within
10-bit accuracy.
Total Harmonic Distortion (THD)
Over-Voltage Recovery
THD is the ratio of the RMS sum of the first 5 harmonic
components to the RMS value of the fundamental input signal.
Over-Voltage Recovery is measured by providing a full-scale
transition to the analog input of the ADC which overdrives
the input by 200mV, and measuring the number of cycles it
takes for the output code to settle within 10-bit accuracy.
Signal To Noise and Distortion Ratio (SINAD)
2nd and 3rd Harmonic Distortion
This is the ratio of the RMS value of the applicable harmonic
component to the RMS value of the fundamental input signal.
Spurious Free Dynamic Range (SFDR)
SFDR is the ratio of the fundamental RMS amplitude to the
RMS amplitude of the next largest spectral component in the
spectrum below fS /2.
14
Full Power Input Bandwidth (FPBW)
Full power input bandwidth is the analog input frequency at
which the amplitude of the digitally reconstructed output has
decreased 3dB below the amplitude of the input sine wave.
The input sine wave has an amplitude which swings from
-FS to +FS. The bandwidth given is measured at the
specified sampling frequency.
HI5767
Video Definitions
Data Hold Time (tH)
Differential Gain and Differential Phase are two commonly
found video specifications for characterizing the distortion of
a chrominance signal as it is offset through the input voltage
range of an ADC.
Data hold time is the time to where the previous data (N - 1)
is no longer valid.
Data Output Delay Time (tOD)
Differential Gain (DG)
Data output delay time is the time to where the new data (N)
is valid.
Differential Gain is the peak difference in chrominance
amplitude (in percent) relative to the reference burst.
Data Latency (tLAT)
Differential Phase (DP)
Differential Phase is the peak difference in chrominance
phase (in degrees) relative to the reference burst.
Timing Definitions
Refer to Figure 1 and Figure 2 for these definitions.
Aperture Delay (tAP)
Aperture delay is the time delay between the external
sample command (the falling edge of the clock) and the time
at which the signal is actually sampled. This delay is due to
internal clock path propagation delays.
Aperture Jitter (tAJ)
Aperture jitter is the RMS variation in the aperture delay due
to variation of internal clock path delays.
After the analog sample is taken, the digital data representing
an analog input sample is output to the digital data bus on
the 7th cycle of the clock after the analog sample is taken.
This is due to the pipeline nature of the converter where the
analog sample has to ripple through the internal subconverter
stages. This delay is specified as the data latency. After the
data latency time, the digital data representing each
succeeding analog sample is output during the following
clock cycle. The digital data lags the analog input sample by 7
sample clock cycles.
Power-Up Initialization
This time is defined as the maximum number of clock cycles
that are required to initialize the converter at power-up. The
requirement arises from the need to initialize the dynamic
circuits within the converter.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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15
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