KDC5512EVAL, KDC5512HEVAL, KDC5512-50EVAL, KDC5514EVAL C10 100pF SDO C38 C37 100pF CSB SCLK 100pF SDIO 100pF C36 100pF C35 OVDD pin36 OVDD C27 0.1uF pin27 C24 0.1uF pin56 C14 0.1uF OVDD 6 7 8 AVDD GND GND C11 100pF 9 10 VinIm VinIp GND AVDD OVDD DGND 56 55 ORP ORN D13P D13N D12P D12N D11P D11N OVDD OVSS DGND 65 64 63 62 61 60 59 58 57 ORP ORN D13P D13N D12P D12N D11P D11N OVSS SDIO SCLK CSB SDO 69 68 67 66 AVDD AVSS AVSS CLKOUTP CLKOUTN VINN VINP RLVDS OVSS AVSS AVDD DNC DNC VCM CLKDIV DNC DNC clk_inp clk_inn AVDD 19 20 21 AVDD CLKP CLKN Vcm clkdivn 11 12 13 14 15 16 17 18 D10P D10N D9P D9N D8P D8N DNC DNC DNC DNC D7P D7N D6P D6N D5P D5N D4P D4N 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 D10P D10N D9P D9N D8P D8N CLKOUTP CLKOUTN 10K DGND R46 D7P D7N D6P D6N D5P D5N D4P D4N OVDD Bead AVDD Under DUT. OVDD 36 Bead L14 C9 100pF 2 3 4 5 SCL SDA D0N D0P D1N D1P D2N D2P D3N D3P L13 C8 100pF SDA 28 29 30 31 32 33 34 35 Bead U1 KAD5512 L15 bead D0N D0P D1N D1P D2N D2P D3N D3P L3 RESETN OVSS OVDD SD0 SCL 25 DGND 26 OVDD 27 Bead RESETN L4 OUTMODE NAPSLP AVDD 1 AVDD SC0 SDIO SCLK CSB SDO GND AVDD OUTFMT C12 100pF output_mode 22 nap_sleep_normal 23 AVDD 24 C45 100pF pin70 OUTFMT pin23 nap_sleep_normal C44 0.1uF GND C43 0.1uF 72 71 70 C42 0.1uF pin22 output_mode pin16 clkdivn pin15 Vcm C26 0.1uF 0 C25 0.1uF pin71 AVDD pin24 AVDD C22 0.1uF EP C20 0.1uF pin19 pin12 AVDD pin6 C15 0.1uF AVSS AVDD OUTFMT C13 0.1uF AVDD AVDD pin1 AVDD KDC5512EVAL, KDC5512HEVAL, KDC5512-50EVAL, KDC5514EVAL Schematics L16 bead L17 bead L18 bead anlg_1.8V HI= Gray_Code LO= Unsign Ft=Twos_Comp R15 DNP anlg_1.8V R25 DNP anlg_1.8V HI= clk_div4 LO= clk_div2 Ft=clk_div1 R22 DNP OUTFMT R14 1K HI=2mA LVDS LO= LVCMOS Ft= 3mA LVDS output_mode R24 DNP anlg_1.8V R26 DNP nap_sleep_normal clkdivn R23 DNP HI= Nap LO = Normal Ft= Sleep R28 1K INTERSIL PROPRIETARY AND CONFIDENTIAL. SUBJECT TO NONDISCLOSURE Title KDB5512P/5512HP/5514P/5512-5 Size B FIGURE 1. ADC, MODE PINS AND POWER SUPPLY BYPASS 1 Number page1 Revision B KDC5512EVAL, KDC5512HEVAL, KDC5512-50EVAL, KDC5514EVAL KDC5512EVAL, KDC5512HEVAL, KDC5512-50EVAL, KDC5514EVAL Schematics (Continued) J3 C41 50 Ohms coplanar SMA AT1 0dB AT2 1 2 2 ADT1-1WT ADT1-1WT 3 T4 3 T5 4 DNP R18 4 VinIm 3dB 1 R47 DNP 0.01uF 2 1 2 6 1 DNP R20 6 VinIp R43 0 Vcm DNP R44 C40 0.1uF Vcm C39 0.1uF C16 L5 0.1uF 1uH R16 L6 Bead VinIm 0 L7 DNP C17 J2 50 Ohms coplanar SMA AT3 1 0dB AT4 2 2 1 6 1 6 3 4 3 4 R19 28 3dB 0.1uF C21 1 0.01uF DNP C19 T1 L10 ADTL1-12+ Bead T2 ADTL1-12+ R21 28 L9 DNP R17 VinIp 0 L8 Vcm 0 1uH R45 C18 0.1uF C23 0.1uF Vcm 220pF C53 IN VT VREFAC IN EP GND SMA 12 11 10 9 C52 0.1uF Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 C29 49.9 49.9 49.9 49.9 49.9 49.9 49.9 T3 R56 R53 R49 R50 R52 R54 15 16 1 2 3 4 5 6 TC4-1W SMA DNP C46 clk_inp R48 100 clk_inn 1000pF C30 C32 R27 200 50 Ohms coplanar "CLOCK IN" J4 1000pF C28 10000pF clk_inp DNP C47 1000pF clk_inn 0 13 "CLOCK IN" J5 U5 R51 NB6L14MMNG C49 1000pF R55 C51 1000pF 8 7 14 C50 0.1uF EN Vcc Vcc C48 0.1uF anlg_3.3V 49.9 anlg_3.3V INTERSIL PROPRIETARY AND CONFIDENTIAL. Title FIGURE 2. CLOCK AND ANALOG INPUTS 2 KDC5512EVAL, KDC5512HEVAL, KDC5512-50EVAL, KDC5514EVAL KDC5512EVAL, KDC5512HEVAL, KDC5512-50EVAL, KDC5514EVAL Schematics (Continued) DGND GND AVDD AVDD 33uF anlg_1.8V C31 C_vdd3_anlg anlg_3.3V Anlg_5V 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 VCC 0.1uF C5 VCC 0.1uF C34 dig_1.8V 0.1uF dig_1.8V D13P D13N C33 C4 33uF 33uF C7 ORP ORN C1 dig_1.8V VCC 0.1uF Dig_5V dig_1.8V D12P D12N see page 11 for J6 pinout notes D11P D11N dig_1.8V 4.7K R39 C3 0.1uF dig_1.8V D7P D7N R1 1K TDO D5P D5N dig_1.8V SCLK SDO R5 1K R6 1K SDIO CSB R7 1K D4P D4N D3P D3N 24AA32A-I/SN XC2C64A-6VQG44C dig_1.8V IO(2) TDO GND VCCIO2 IO(2) IO(2) IO(2) IO_GLB_S/R IO_GOE IO_GOE IO_GOE TCK TMS TDI IO(1) VCCIO1 I/O(1) I/O(1) GND I/O(1) I/O(1) I/O(GCK) TCK 11 TMS 10 TDI 9 1K 8 R9 7 VCC 6 R10 1K R11 1K 5 4 R12 1K 3 2 R13 1K 1 CPLD SPARE1 C2 0.1uF SPARE EEPROM U2 1 2 3 4 PC3 IO_GOE VAUX IO(2) IO(2) IO(2) IO(1) IO(1) IO(1) IO(1) IO(GCK) IO(GCK) D2P D2N 23 24 25 26 27 28 29 30 31 32 33 D1P D1N A0 A1 A2 Vss Vcc WP SCL SDA dig_1.8V 8 7 6 R33 5 R32 WP_2V 0 0 SC0 SD0 24AA64-I/SN 34 35 36 37 38 39 40 41 42 43 44 D0P D0N WP_2V SC2 SD2 U4 IO(2) IO(2) IO(2) IO(2) I(2) GND IO(1) VCC IO(1) IO(1) IO(1) D6P D6N 8 7 6 5 4.7K 4.7K 22 21 20 19 18 17 16 15 14 13 12 dig_1.8V Vcc WP SCL SDA R34 CLKOUTP CLKOUTN A0 A1 A2 Vss R31 R29 D8P D8N U3 1 2 3 4 10K dig_1.8V D9P D9N 1K R8 dig_1.8V 1K R41 1K R40 WP PC1 D10P D10N 1K R3 SPI_CONF 1K R35 RESETN 4.7K R37 PORn_ExtResetn_fpga 1K R4 ID EEPROM PC6 PC7 PC0 daughter card detected PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC4 PC5 PC2 WP SPI_master_drive CPLD SPARE1 SCLK_3V CSB_3V MISO_3V MOSI_3V R30 1K VCC R36 1K R38 1K WP_2V SCLK_3V CSB_3V SPI_master_drive R42 1K MISO_3V MOSI_3V 33uF C6 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 R2 OVDD OVDD 4.7K J6 dig_1.8V SD0 SC0 SD2 SC2 PORn_ExtResetn_fpga JTAG connector PLCD Programing J1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 DGND GND VCC TMS TCK TDO TDI INTERSIL PROPRIETARY AND CONFIDENTIAL. SUBJECT TO NONDISC 2MM HDR 14P SMT Title Size 53475-1879 B Date: File: FIGURE 3. INPUT/OUTPUT MEZZANINE CONNECTOR 3 KDB5512P/5512HP/5514P/5512 Number Rev page3 1/30/2009 \\..\KDC5512_INTLV_IO.SchDoc Sheet of Drawn By: KDC5512EVAL, KDC5512HEVAL, KDC5512-50EVAL, KDC5514EVAL KDC5512EVAL, KDC5512HEVAL, KDC5512-50EVAL, KDC5514EVAL REV B Layers FIGURE 4. LAYER - SECONDARY SIDE SILKSCREEN 4 KDC5512EVAL, KDC5512HEVAL, KDC5512-50EVAL, KDC5514EVAL KDC5512EVAL, KDC5512HEVAL, KDC5512-50EVAL, KDC5514EVAL REV B Layers FIGURE 5. LAYER 1 - PRIMARY SIDE 5 (Continued) KDC5512EVAL, KDC5512HEVAL, KDC5512-50EVAL, KDC5514EVAL KDC5512EVAL, KDC5512HEVAL, KDC5512-50EVAL, KDC5514EVAL REV B Layers FIGURE 6. LAYER 2 - GND PLANE 1 6 (Continued) KDC5512EVAL, KDC5512HEVAL, KDC5512-50EVAL, KDC5514EVAL KDC5512EVAL, KDC5512HEVAL, KDC5512-50EVAL, KDC5514EVAL REV B Layers FIGURE 7. LAYER 3 - PWR PLANE 7 (Continued) KDC5512EVAL, KDC5512HEVAL, KDC5512-50EVAL, KDC5514EVAL KDC5512EVAL, KDC5512HEVAL, KDC5512-50EVAL, KDC5514EVAL REV B Layers FIGURE 8. LAYER 4 - INTERNAL SIGNAL 8 (Continued) KDC5512EVAL, KDC5512HEVAL, KDC5512-50EVAL, KDC5514EVAL KDC5512EVAL, KDC5512HEVAL, KDC5512-50EVAL, KDC5514EVAL REV B Layers FIGURE 9. LAYER 5 - GND PLANE 2 9 (Continued) KDC5512EVAL, KDC5512HEVAL, KDC5512-50EVAL, KDC5514EVAL KDC5512EVAL, KDC5512HEVAL, KDC5512-50EVAL, KDC5514EVAL REV B Layers FIGURE 10. LAYER 6 - SECONDARY SIDE 10 (Continued) KDC5512EVAL, KDC5512HEVAL, KDC5512-50EVAL, KDC5514EVAL KDC5512EVAL, KDC5512HEVAL, KDC5512-50EVAL, KDC5514EVAL REV B Layers (Continued) FIGURE 11. LAYER - PRIMARY SIDE SILKSCREEN J6 pinout is shown for 14bit device. ADC Output Data pins are MSB justified at J6. Pins 20, 22 at J6 are the MSB for 14 ,12, 10 and 8 bit devices ( MSB = D13, D11, D9, and D7 for 14,12,10, and 8 bit devices respectively. J6 pins 26,28 are MSB -1. Contact factory for additional information if needed. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding. For information regarding Intersil Corporation and its products, see www.intersil.com 11