DATASHEET

12-Bit, 250MSPS/200MSPS/130MSPS ADC
ISLA212P
Features
The ISLA212P is a series of low power, high performance
12-bit analog-to-digital converters. Designed with Intersil’s
proprietary FemtoCharge™ technology on a standard CMOS
process, the series supports sampling rates of up to 250MSPS.
The ISLA212P is part of a pin-compatible family of 12 to 16-bit
A/Ds with maximum sample rates ranging from 130MSPS to
500MSPS.
• Single Supply 1.8V Operation
A serial peripheral interface (SPI) port allows for extensive
configurability, as well as fine control of various parameters
such as gain and offset. Digital output data is presented in
selectable LVDS or CMOS formats, and can be configured as
full-width, single data rate (SDR) or half-width, double data
rate (DDR). The ISLA212P is available in a 72-contact QFN
package with an exposed paddle. Operating from a 1.8V
supply, performance is specified over the full industrial
temperature range (-40°C to +85°C).
1
• Data Output Clock
• SDR/DDR LVDS-Compatible or LVCMOS Outputs
• Broadband Communications
• High-Performance Data Acquisition
• Communications Test Equipment
MODEL
RESOLUTION
SPEED
(MSPS)
ISLA216P25
16
250
ISLA216P20
16
200
CLKOUTP
ISLA216P13
16
130
CLKOUTN
ISLA214P50
14
500
ISLA214P25
14
250
ISLA214P20
14
200
D[11:0]N
ISLA214P13
14
130
ISLA212P50
12
500
ISLA212P25
12
250
ISLA212P20
12
200
ISLA212P13
12
130
OVSS
RLVDS
CSB
SCLK
SDIO
SDO
RESETN
AVSS
NAPSLP
SPI
CONTROL
November 30, 2012
FN7717.2
- SPI Programmable Fine Gain and Offset Control
- Support for Multiple ADC Synchronization
- Optimized Output Timing
• Nap and Sleep Modes
- 200µs Sleep Wake-up Time
• Software Defined Radios
D[11:0]P
DIGITAL
ERROR
CORRECTION
+
–
VCM
• Multi-ADC Support
• Radar Array Processing
OVDD
CLKDIVRSTN
CLKDIV
CLKDIVRSTP
AVDD
12-BIT
250 MSPS
ADC
SHA
VINN
• Programmable Built-in Test Patterns
Pin-Compatible Family
CLOCK
MANAGEMENT
VINP
• 700MHz Bandwidth
Applications
• SNR @ 250/200/130MSPS
70.5/71.0/71.5dBFS fIN = 30MHz
68.7/68.9/68.8dBFS fIN = 363MHz
• SFDR @ 250/200/130MSPS
83/83/88dBc fIN = 30MHz
78/81/85dBc fIN = 363MHz
• Total Power Consumption = 440mW @ 250MSPS
CLKN
• 75fs Clock Jitter
• Selectable Clock Divider
Key Specifications
CLKP
• Clock Duty Cycle Stabilizer
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2011, 2012. All Rights Reserved
Intersil (and design) and FemtoCharge are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISLA212P
Pin Configuration - LVDS MODE
AVDD
AVDD
AVDD
SDIO
SCLK
CSB
SDO
OVSS
ORP
ORN
OVDD
OVSS
DNC
DNC
DNC
DNC
D0P
D0N
ISLA212P
(72 LD QFN)
TOP VIEW
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
DNC
1
54 D1P
DNC
2
53 D1N
NAPSLP
3
52 D2P
VCM
4
51 D2N
AVSS
5
50 D3P
AVDD
6
49 D3N
AVSS
7
48 CLKOUTP
VINN
8
47 CLKOUTN
VINN
9
46 RLVDS
VINP 10
45 OVSS
VINP 11
44 D4P
AVSS 12
43 D4N
AVDD 13
42 D5P
AVSS 14
41 D5N
CLKDIV 15
40 D6P
IPTAT 16
39 D6N
Thermal Pad Not Drawn to Scale,
Consult Mechanical Drawing
for Physical Dimensions
DNC 17
Connect Thermal Pad to AVSS
38 D7P
RESETN 18
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
AVDD
CLKP
CLKN
CLKDIVRSTP
CLKDIVRSTN
OVSS
OVDD
D11N
D11P
D10N
D10P
OVDD
D9N
D9P
D8N
D8P
AVDD
19
AVDD
37 D7N
2
FN7717.2
November 30, 2012
ISLA212P
Pin Descriptions - 72 Ld QFN, LVDS Mode
PIN NUMBER
LVDS PIN NAME
LVDS PIN FUNCTION
1, 2, 17, 57, 58, 59, 60
DNC
Do Not Connect
6, 13, 19, 20, 21, 70, 71,
72
AVDD
1.8V Analog Supply
5, 7, 12, 14
AVSS
Analog Ground
27, 32, 62
OVDD
1.8V Output Supply
26, 45, 61, 65
OVSS
Output Ground
3
NAPSLP
4
VCM
Common Mode Output
8, 9
VINN
Analog Input Negative
DDR MODE COMMENTS
Tri-Level Power Control (Nap, Sleep modes)
10, 11
VINP
15
CLKDIV
Analog Input Positive
16
IPTAT
18
RESETN
22, 23
CLKP, CLKN
24, 25
CLKDIVRSTP, CLKDIVRSTN
28
D11N
LVDS Bit 11(MSB) Output Complement
NC in DDR Mode
29
D11P
LVDS Bit 11 (MSB) Output True
NC in DDR Mode
30
D10N
LVDS Bit 10 Output Complement
DDR Logical Bits 10, 11
31
D10P
LVDS Bit 10 Output True
DDR Logical Bits 10, 11
33
D9N
LVDS Bit 9 Output Complement
NC in DDR Mode
34
D9P
LVDS Bit 9 Output True
NC in DDR Mode
35
D8N
LVDS Bit 8 Output Complement
DDR Logical Bits 8, 9
36
D8P
LVDS Bit 8 Output True
DDR Logical Bits 8, 9
Tri-Level Clock Divider Control
Temperature Monitor (Output current proportional to absolute
temperature)
Power On Reset (Active Low)
Clock Input True, Complement
Synchronous Clock Divider Reset True, Complement
37
D7N
LVDS Bit 7 Output Complement
NC in DDR Mode
38
D7P
LVDS Bit 7 Output True
NC in DDR Mode
39
D6N
LVDS Bit 6 Output Complement
DDR Logical Bits 6, 7
40
D6P
LVDS Bit 6 Output True
DDR Logical Bits 6, 7
41
D5N
LVDS Bit 5 Output Complement
NC in DDR Mode
42
D5P
LVDS Bit 5 Output True
NC in DDR Mode
43
D4N
LVDS Bit 4 Output Complement
DDR Logical Bits 4, 5
44
D4P
LVDS Bit 4 Output True
DDR Logical Bits 4, 5
46
RLVDS
47, 48
CLKOUTN, CLKOUTP
LVDS Bias Resistor (Connect to OVSS with 1% 10kΩ)
49
D3N
LVDS Bit 3 Output Complement
NC in DDR Mode
50
D3P
LVDS Bit 3 Output True
NC in DDR Mode
LVDS Clock Output Complement, True
51
D2N
LVDS Bit 2 Output Complement
DDR Logical Bits 2, 3
52
D2P
LVDS Bit 2 Output True
DDR Logical Bits 2, 3
53
D1N
LVDS Bit 1 Output Complement
NC in DDR Mode
54
D1P
LVDS Bit 1 Output True
NC in DDR Mode
55
D0N
LVDS Bit 0 Output Complement
DDR Logical Bits 0, 1
56
D0P
LVDS Bit 0 Output True
DDR Logical Bits 0, 1
63, 64
ORN, ORP
LVDS Over Range Complement, True
DDR Over Range
3
FN7717.2
November 30, 2012
ISLA212P
Pin Descriptions - 72 Ld QFN, LVDS Mode
PIN NUMBER
LVDS PIN NAME
66
SDO
SPI Serial Data Output
67
CSB
SPI Chip Select (active low)
68
SCLK
SPI Clock
69
SDIO
SPI Serial Data Input/Output
Exposed Paddle
AVSS
Analog Ground
(Continued)
LVDS PIN FUNCTION
DDR MODE COMMENTS
Pin Configuration - CMOS MODE
CSB
SDO
OVSS
OR
DNC
OVDD
OVSS
DNC
68
67
66
65
64
63
62
61
60
59
DNC
SCLK
69
D0
SDIO
70
DNC
AVDD
71
DNC
AVDD
72
DNC
AVDD
ISLA212P
(72 LD QFN)
TOP VIEW
58
57
56
55
DNC
1
54 D1
DNC
2
53 DNC
NAPSLP
3
52 D2
VCM
4
51 DNC
AVSS
5
50 D3
AVDD
6
49 DNC
AVSS
7
48 CLKOUT
VINN
8
47 DNC
VINN
9
46 RLVDS
VINP 10
45 OVSS
VINP 11
44 D4
AVSS 12
43 DNC
AVDD 13
42 D5
AVSS 14
41 DNC
CLKDIV 15
40 D6
IPTAT 16
39 DNC
Thermal Pad Not Drawn to Scale,
Consult Mechanical Drawing
for Physical Dimensions
DNC 17
Connect Thermal Pad to AVSS
38 D7
RESETN 18
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
AVDD
CLKP
CLKN
CLKDIVRSTP
CLKDIVRSTN
OVSS
OVDD
DNC
D11
DNC
D10
OVDD
DNC
D9
DNC
D8
AVDD
19
AVDD
37 DNC
4
FN7717.2
November 30, 2012
ISLA212P
Pin Descriptions - 72 Ld QFN, CMOS Mode
PIN NUMBER
CMOS PIN NAME
1, 2, 17, 28, 30, 33, 35,
37, 39, 41, 43, 47, 49,
51, 53, 55, 57, 58, 59,
60, 63
DNC
Do Not Connect
6, 13, 19, 20, 21, 70, 71,
72
AVDD
1.8V Analog Supply
5, 7, 12, 14
AVSS
Analog Ground
27, 32, 62
OVDD
1.8V Output Supply
26, 45, 61, 65
OVSS
Output Ground
3
NAPSLP
4
VCM
Common Mode Output
8, 9
VINN
Analog Input Negative
10, 11
VINP
Analog Input Positive
15
CLKDIV
16
IPTAT
18
RESETN
22, 23
CLKP, CLKN
24, 25
CMOS PIN FUNCTION
DDR MODE COMMENTS
Tri-Level Power Control (Nap, Sleep modes)
Tri-Level Clock Divider Control
Temperature Monitor (Output current proportional to absolute
temperature)
Power On Reset (Active Low)
Clock Input True, Complement
CLKDIVRSTP, CLKDIVRSTN Synchronous Clock Divider Reset True, Complement
29
D11
CMOS Bit 11 (MSB) Output
NC in DDR Mode
31
D10
CMOS Bit 10 Output
DDR Logical Bits 10, 11
34
D9
CMOS Bit 9 Output
NC in DDR Mode
36
D8
CMOS Bit 8 Output
DDR Logical Bits 8, 9
38
D7
CMOS Bit 7 Output
NC in DDR Mode
40
D6
CMOS Bit 6 Output
DDR Logical Bits 6, 7
42
D5
CMOS Bit 5 Output
NC in DDR Mode
44
D4
CMOS Bit 4 Output
DDR Logical Bits 4, 5
46
RLVDS
LVDS Bias Resistor (Connect to OVSS with 1% 10kΩ)
48
CLKOUT
CMOS Clock Output
50
D3
CMOS Bit 3 Output
NC in DDR Mode
52
D2
CMOS Bit 2 Output
DDR Logical Bits 2, 3
54
D1
CMOS Bit 1 Output
NC in DDR Mode
56
D0
CMOS Bit 0 (LSB) Output
DDR Logical Bits 0, 1
64
OR
CMOS Over Range
DDR Over Range
66
SDO
SPI Serial Data Output
67
CSB
SPI Chip Select (active low)
68
SCLK
SPI Clock
69
SDIO
SPI Serial Data Input/Output
Exposed Paddle
AVSS
Analog Ground
5
FN7717.2
November 30, 2012
ISLA212P
Ordering Information
PART NUMBER
(Notes 1, 2)
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISLA212P13IRZ
ISLA212P13 IRZ
-40°C to +85°C
72 Ld QFN
L72.10x10E
ISLA212P20IRZ
ISLA212P20 IRZ
-40°C to +85°C
72 Ld QFN
L72.10x10E
ISLA212P25IRZ
ISLA212P25 IRZ
-40°C to +85°C
72 Ld QFN
L72.10x10E
Coming Soon
ISLA212P13IR1Z
ISLA212P13 IR1Z
-40°C to +85°C
48 Ld QFN
TBD
Coming Soon
ISLA212P20IR1Z
ISLA212P20 IR1Z
-40°C to +85°C
48 Ld QFN
TBD
Coming Soon
ISLA212P25IR1Z
ISLA212P25 IR1Z
-40°C to +85°C
48 Ld QFN
TBD
ISLA214IR72EV1Z
14-bit 250MSPS ADC Evaluation Board (This 14-bit ADC evaluation board can be configured for 12-bit testing.)
NOTES:
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate-e4
termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. For Moisture Sensitivity Level (MSL), please see device information page for ISLA212P. For more information on MSL please see Tech Brief TB363.
6
FN7717.2
November 30, 2012
ISLA212P
Table of Contents
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Power-On Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
User Initiated Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Temperature Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Nap/Sleep. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20
20
21
21
21
21
21
22
Clock Divider Synchronous Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
SPI Physical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Configuration/Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Global Device Configuration/Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
25
26
26
27
28
SPI Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Equivalent Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
A/D Evaluation Platform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Split Ground and Power Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Input Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Exposed Paddle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bypass and Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LVDS Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LVCMOS Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Unused Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33
33
33
33
33
33
33
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7
FN7717.2
November 30, 2012
ISLA212P
Absolute Maximum Ratings
Thermal Information
AVDD to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.4V to 2.1V
OVDD to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.4V to 2.1V
AVSS to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V
Analog Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V
Clock Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V
Logic Input to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V
Logic Inputs to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V
Latchup (Tested per JESD-78C;Class 2,Level A) . . . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
72 Ld QFN (Notes 3, 4) . . . . . . . . . . . . . . . .
23
0.9
48 Ld QFN (Notes 3, 4) . . . . . . . . . . . . . . . .
24
1.0
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
3. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
4. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V,
OVDD = 1.8V, TA = -40°C to +85°C (Typical specifications at +25°C), AIN = -1dBFS, fSAMPLE = Maximum Conversion Rate (per speed grade).
Boldface limits apply over the operating temperature range, -40°C to +85°C.
ISLA212P25
PARAMETER
SYMBOL
CONDITIONS
ISLA212P20
MIN
MAX
MIN
(Note 5) TYP (Note 5) (Note 5) TYP
ISLA212P13
MAX
MIN
(Note 5) (Note 5) TYP
MAX
(Note 5)
UNITS
2.1
VP-P
DC SPECIFICATIONS (Note 6)
Analog Input
Full-Scale Analog Input
Range
VFS
Differential
1.95
2.0
2.1
1.95
2.0
2.1
1.95
2.0
Input Resistance
RIN
Differential
600
600
600
Ω
Input Capacitance
CIN
Differential
4.5
4.5
4.5
pF
Full Temp
108
84
72
ppm/°C
Full Scale Range Temp.
Drift
AVTC
Input Offset Voltage
VOS
Common-Mode Output
Voltage
VCM
0.94
0.94
0.94
V
Common-Mode Input
Current (per pin)
ICM
2.6
2.6
2.6
µA/MSPS
Inputs Common Mode
Voltage
0.9
0.9
0.9
V
CLKP, CLKN Input Swing
(Note 7)
1.8
1.8
1.8
V
-5.0
-1.7
5.0
-5.0
-1.7
5.0
-5.0
-1.7
5.0
mV
Clock Inputs
Power Requirements
1.8V Analog Supply
Voltage
AVDD
1.7
1.8
1.9
1.7
1.8
1.9
1.7
1.8
1.9
V
1.8V Digital Supply
Voltage
OVDD
1.7
1.8
1.9
1.7
1.8
1.9
1.7
1.8
1.9
V
1.8V Analog Supply
Current
IAVDD
188
200
174
184
152
161
mA
1.8V Digital Supply
Current (Note 6)
I
OVDD
3mA LVDS (SDR)
72
80
68
76
61
69
mA
Power Supply Rejection
Ratio
PSRR
30MHz, 30mVP-P signal
on AVDD
40
8
40
40
dB
FN7717.2
November 30, 2012
ISLA212P
Electrical Specifications
All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V,
OVDD = 1.8V, TA = -40°C to +85°C (Typical specifications at +25°C), AIN = -1dBFS, fSAMPLE = Maximum Conversion Rate (per speed grade).
Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
ISLA212P25
PARAMETER
SYMBOL
CONDITIONS
ISLA212P20
MIN
MAX
MIN
(Note 5) TYP (Note 5) (Note 5) TYP
ISLA212P13
MAX
MIN
(Note 5) (Note 5) TYP
MAX
(Note 5)
UNITS
Total Power Dissipation
Normal Mode
PD
Nap Mode
PD
Sleep Mode
PD
2mA LVDS
445
3mA LVDS (SDR)
468
3mA LVDS (DDR)
440
405
353
mW
CMOS (SDR)
427
380
315
mW
CMOS (DDR)
416
373
308
mW
CSB at logic high
Nap/Sleep Mode
Wakeup Time
Sample Clock Running
412
504
436
360
468
383
mW
414
mW
55.8
60
52.2
57
48.6
53
mW
6
12
6
12
6
12
mW
200
400
630
µs
AC SPECIFICATIONS
Differential Nonlinearity
DNL
fIN = 105MHz
No Missing Codes
-0.9
±0.16
0.9
-0.5
±0.12
0.5
-0.5
±0.12
0.5
LSB
Integral Nonlinearity
INL
fIN = 105MHz
-1.8
±0.6
1.8
-1.5
±0.5
1.5
-1.5
±0.5
1.5
LSB
Minimum Conversion
Rate (Note 8)
fS MIN
40
MSPS
Maximum Conversion
Rate
fS MAX
Signal-to-Noise Ratio
(Note 9)
SNR
Signal-to-Noise and
Distortion
(Note 9)
Effective Number of Bits
(Note 9)
40
250
fIN = 30MHz
fIN = 105MHz
SINAD
9
200
70.5
69.0
70.5
130
71.0
70.0
71.0
70.4
MSPS
71.5
dBFS
71.2
dBFS
fIN = 190MHz
69.8
70.3
70.5
dBFS
fIN = 363MHz
68.7
68.9
68.8
dBFS
fIN = 461MHz
68.1
68.1
67.7
dBFS
fIN = 605MHz
66.9
66.7
66.2
dBFS
fIN = 30MHz
69.4
70.7
71.4
dBFS
70.8
dBFS
fIN = 105MHz
ENOB
40
68.5
69.4
69.4
70.7
69.1
fIN = 190MHz
68.9
69.9
69.9
dBFS
fIN = 363MHz
68.1
68.6
68.6
dBFS
fIN = 461MHz
65.2
66.3
64.9
dBFS
fIN = 605MHz
60.2
60.8
60.2
dBFS
fIN = 30MHz
11.24
11.45
11.57
Bits
fIN = 105MHz
11.09 11.24
11.24 11.45
11.19 11.47
Bits
fIN = 190MHz
11.15
11.32
11.32
Bits
fIN = 363MHz
11.02
11.10
11.10
Bits
fIN = 461MHz
10.54
10.72
10.49
Bits
fIN = 605MHz
9.71
9.81
9.71
Bits
FN7717.2
November 30, 2012
ISLA212P
Electrical Specifications
All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V,
OVDD = 1.8V, TA = -40°C to +85°C (Typical specifications at +25°C), AIN = -1dBFS, fSAMPLE = Maximum Conversion Rate (per speed grade).
Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
ISLA212P25
PARAMETER
SYMBOL
Spurious-Free Dynamic
Range
(Note 9)
SFDR
CONDITIONS
MIN
MAX
MIN
(Note 5) TYP (Note 5) (Note 5) TYP
fIN = 30MHz
fIN = 105MHz
ISLA212P20
83
73
83
ISLA212P13
MAX
MIN
(Note 5) (Note 5) TYP
83
73
83
71
MAX
(Note 5)
UNITS
88
dBc
81
dBc
fIN = 190MHz
77
83
78
dBc
fIN = 363MHz
78
81
85
dBc
fIN = 461MHz
68
71
68
dBc
fIN = 605MHz
60
62
61
dBc
Spurious-Free Dynamic SFDRX23 fIN = 30MHz
Range Excluding H2, H3
fIN = 105MHz
89
94
99
dBc
91
90
96
dBc
fIN = 190MHz
88
89
92
dBc
fIN = 363MHz
87
91
95
dBc
fIN = 461MHz
88
93
94
dBc
fIN = 605MHz
88
88
87
dBc
fIN = 70MHz
87
86
87
dBFS
fIN = 170MHz
97
104
101
dBFS
10-12
10-12
700
700
Intermodulation
Distortion
IMD
Word Error Rate
WER
10-12
Full Power Bandwidth
FPBW
700
MHz
NOTES:
5. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
6. Digital Supply Current is dependent upon the capacitive loading of the digital outputs. IOVDD specifications apply for 10pF load on each digital output
7. See “Clock Input” on page 20.
8. The DLL Range setting must be changed for low-speed operation.
9. Minimum specification guaranteed when calibrated at +85°C.
Digital Specifications
Boldface limits apply over the operating temperature range, -40°C to +85°C.
PARAMETER
SYMBOL
CONDITIONS
MIN
(Note 5)
TYP
MAX
(Note 5) UNITS
0
1
10
µA
-25
-12
-8
µA
4
12
µA
-600
-415
-300
µA
40
58
75
5
10
INPUTS (Note 10)
Input Current High (RESETN)
IIH
VIN = 1.8V
Input Current Low (RESETN)
IIL
VIN = 0V
Input Current High (SDIO)
IIH
VIN = 1.8V
Input Current Low (SDIO)
IIL
VIN = 0V
Input Current High (CSB)
IIH
VIN = 1.8V
Input Current Low (CSB)
IIL
VIN = 0V
Input Current High (CLKDIV)
IIH
16
25
34
µA
Input Current Low (CLKDIV)
IIL
-34
-25
-16
µA
Input Voltage High (SDIO, RESETN)
VIH
1.17
Input Voltage Low (SDIO, RESETN)
VIL
Input Capacitance
CDI
10
V
0.63
4
V
pF
FN7717.2
November 30, 2012
ISLA212P
Digital Specifications
Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
SYMBOL
CONDITIONS
MIN
(Note 5)
MAX
(Note 5) UNITS
TYP
LVDS INPUTS (CLKDIVRSTP, CLKDIVRSTN)
Input Common Mode Range
VICM
825
1575
mV
Input Differential Swing (peak to peak, single-ended)
VID
250
450
mV
CLKDIVRSTP Input Pull-down Resistance
RIpd
100
kΩ
CLKDIVRSTN Input Pull-up Resistance
RIpu
100
kΩ
612
mVP-P
LVDS OUTPUTS
Differential Output Voltage (Note 11)
Output Offset Voltage
VT
3mA Mode
VOS
3mA Mode
1120
1150
1200
mV
Output Rise Time
tR
240
ps
Output Fall Time
tF
240
ps
OVDD - 0.1
V
CMOS OUTPUTS
Voltage Output High
VOH
IOH = -500µA
Voltage Output Low
VOL
IOL = 1mA
OVDD - 0.3
0.1
0.3
V
Output Rise Time
tR
1.8
ns
Output Fall Time
tF
1.4
ns
NOTES:
10. The Tri-Level Inputs internal switching thresholds are approximately 0.43V and 1.34V. It is advised to float the inputs or tie to ground or AVDD,
depending on desired function.
11. The voltage is expressed in peak-to-peak differential swing. The peak-to-peak singled-ended swing is one-half of the differential swing.
Timing Diagrams
INP
INN
tA
CLKN
CLKP
LATENCY = L CYCLES
tCPD
CLKOUTN
CLKOUTP
tDC
tPD
D[10/8/6/4/2/0]N
D[10/8/6/4/2/0]P
ODD
N-L
EVEN
N-L
ODD
N-L+1
EVEN
N-L+1
EVEN
N-1
ODD
N
EVEN
N
FIGURE 1A. LVDS DDR
11
FN7717.2
November 30, 2012
ISLA212P
Timing Diagrams (Continued)
INP
INN
tA
CLKN
CLKP
LATENCY = L CYCLES
tCPD
CLKOUTN
CLKOUTP
tDC
tPD
D[11:0]N
DATA
N-L
D[11:0]P
DATA
N
DATA
N-L+1
FIGURE 1B. LVDS SDR
FIGURE 1. LVDS TIMING DIAGRAMS
INP
INN
tA
CLKN
CLKP
LATENCY = L CYCLES
tCPD
CLKOUT
tDC
tPD
D[10/8/6/4/2/0]
ODD
N-L
EVEN
N-L
ODD
N-L+1
EVEN
N-L+1
EVEN
N-1
ODD
N
EVEN
N
FIGURE 2A. CMOS DDR
12
FN7717.2
November 30, 2012
ISLA212P
Timing Diagrams (Continued)
INP
INN
tA
CLKN
CLKP
LATENCY = L CYCLES
tCPD
CLKOUT
tDC
tPD
DATA
N-L
D[11:0]
DATA
N
DATA
N-L+1
FIGURE 2B. CMOS SDR
FIGURE 2. CMOS TIMING DIAGRAMS
Switching Specifications
Boldface limits apply over the operating temperature range, -40°C to +85°C.
PARAMETER
SYMBOL
CONDITION
MIN
(Note 5)
TYP
MAX
(Note 5)
UNITS
ADC OUTPUT
Aperture Delay
tA
114
ps
RMS Aperture Jitter
jA
75
fs
Input Clock to Output Clock Propagation
Delay
Relative Input Clock to Output Clock
Propagation Delay (Note 12)
tCPD
AVDD, OVDD = 1.7V to 1.9V,
TA = -40°C to +85°C
1.65
2.4
3
ns
tCPD
AVDD, OVDD = 1.8V, TA = +25°C
1.9
2.3
2.75
ns
dtCPD
AVDD, OVDD = 1.7V to 1.9V,
TA = -40°C to +85°C
-450
450
ps
Input Clock to Data Propagation Delay
tPD
Output Clock to Data Propagation Delay,
LVDS Mode
tDC
Output Clock to Data Propagation Delay,
CMOS Mode
tDC
Synchronous Clock Divider Reset Setup
Time (with respect to the positive edge of
CLKP)
tRSTS
Synchronous Clock Divider Reset Hold Time
(with respect to the positive edge of CLKP)
tRSTH
Synchronous Clock Divider Reset Recovery
Time
tRSTRT
Latency (Pipeline Delay)
L
13
1.65
2.4
3.5
ns
Rising/Falling Edge
-0.1
0.16
0.5
ns
Rising/Falling Edge
-0.1
0.2
0.65
ns
0.4
0.06
0.02
DLL recovery time after
Synchronous Reset
ns
0.35
ns
52
µs
10
cycles
FN7717.2
November 30, 2012
ISLA212P
Switching Specifications
PARAMETER
Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
SYMBOL
Overvoltage Recovery
MIN
(Note 5)
CONDITION
TYP
tOVR
MAX
(Note 5)
UNITS
1
cycles
SPI INTERFACE (Notes 13, 14)
t
SCLK Period
CLK
Write Operation
16
cycles
tCLK
Read Operation
16
cycles
CSB↓ to SCLK↑ Setup Time
tS
Read or Write
28
cycles
CSB↑ after SCLK↑ Hold Time
tH
Write
5
cycles
CSB↑ after SCLK↓ Hold Time
tHR
Read
16
cycles
Data Valid to SCLK↑ Setup Time
tDS
Write
6
cycles
Data Valid after SCLK↑ Hold Time
tDH
Read or Write
4
cycles
Data Valid after SCLK↓ Time
tDVR
Read
5
cycles
NOTES:
12. The relative propagation delay is the difference in propagation time between any two devices that are matched in temperature and voltage, and is
specified over the full operating temperature and voltage range.
13. SPI Interface timing is directly proportional to the ADC sample period (tS). Values above reflect multiples of a 4ns sample period, and must be scaled
proportionally for lower sample rates. ADC sample clock must be running for SPI communication.
14. The SPI may operate asynchronously with respect to the ADC sample clock.
Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C,
AIN = -1dBFS, fIN = 105MHz, fSAMPLE = 250MSPS.
-60
90
SFDR @ 130MSPS
85
SFDR @ 250MSPS
80
75
70
65 SNR @ 250MSPS
60
0
100
SNR @ 130MSPS
200
300
400
INPUT FREQUENCY (MHz)
FIGURE 3. SNR AND SFDR vs fIN
14
500
600
HD2 AND HD3 MAGNITUDE (dBc)
SNR (dBFS) AND SFDR (dBc)
95
HD3 @ 250MSPS
-65
HD2 @ 250MSPS
-70
-75
-80
-85
-90
HD3 @ 130MSPS
-95
HD2 @ 130MSPS
-100
-105
0
100
200
300
400
500
600
INPUT FREQUENCY (MHz)
FIGURE 4. HD2 AND HD3 vs fIN
FN7717.2
November 30, 2012
ISLA212P
Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C,
AIN = -1dBFS, fIN = 105MHz, fSAMPLE = 250MSPS. (Continued)
-30
90
HD2 AND HD3 MAGNITUDE (dBc
100
SFDR (dBfs)
SNR AND SFDR
80
70
SNR (dBfs)
60
SFDR (dBc)
50
SNR (dBc)
40
30
20
10
-60
-50
-40
-30
-20
-10
-40
-60
HD3 (dBc)
-70
HD2 (dBfs)
-80
HD3 (dBfs)
-90
-100
-110
0
HD2 (dBc)
-50
-60
-50
-40
INPUT AMPLITUDE (dBFS)
FIGURE 5. SNR AND SFDR vs AIN
-10
0
-75
HD2 AND HD3 MAGNITUDE (dBc)
SNR (dBFS) AND SFDR (dBc)
-20
FIGURE 6. HD2 AND HD3 vs AIN
90
85
SFDR
80
75
SNR
70
90
110
130
150
170
190
210
230
-80
H3
-85
-90
H2
-95
-100
-105
70
70
250
90
110
130
150
170
190
210
230
250
SAMPLE RATE (MSPS)
SAMPLE RATE (MSPS)
FIGURE 7. SNR AND SFDR vs fSAMPLE
FIGURE 8. HD2 AND HD3 vs fSAMPLE
500
0.5
475
0.4
0.3
450
0.2
425
400
DNL (LSBs)
TOTAL POWER (mW)
-30
INPUT AMPLITUDE (dBFS)
LVDS
375
0
-0.1
-0.2
350
-0.3
CMOS
325
300
0.1
-0.4
40
60
80
100 120 140 160 180
SAMPLE RATE (MSPS)
200
220
FIGURE 9. POWER vs fSAMPLE IN 3mA LVDS MODE (SDR)
AND CMOS MODE (DDR)
15
240
-0.5
0
500
1000
1500
2000 2500
CODES
3000
3500
4000
FIGURE 10. DIFFERENTIAL NONLINEARITY
FN7717.2
November 30, 2012
ISLA212P
Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C,
AIN = -1dBFS, fIN = 105MHz, fSAMPLE = 250MSPS. (Continued)
1.0
85
SNR (dBFS) AND SFDR (dBc)
0.8
0.6
INL (LSBs)
0.4
0.2
0
-0.2
-0.4
-0.6
80
SFDR AIN = -2dBFS
75
SFDR AIN = -1dBFS
70
SNR AIN = -1dBFS
65
-0.8
-1.0
0
500
1000
1500
2000 2500
CODES
3000
3500
60
0.75
4000
0
183,974
-20
140,000
AMPLITUDE (dBFS)
NUMBER OF HITS
160,000
120,000
100,000
80,000
60,000
40,000
-40
-60
-80
0
0
2041
2042
10,754
5,272
2043
0
2044
CODE
2045
0
2046
-120
2047
FIGURE 13. NOISE HISTOGRAM
0
20
40
60
80
FREQUENCY (MHz)
100
120
FIGURE 14. SINGLE-TONE SPECTRUM @ 105MHz
0
0
AIN = -1.0 dBFS
SNR = 70.2 dBFS
-20 SFDR = 78.4 dBc
SINAD = 69.4 dBFS
AIN = -1.0 dBFS
SNR = 69.2 dBFS
SFDR = 78.4 dBc
SINAD = 68.7 dBFS
-20
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
1.15
-100
20,000
-40
-60
-80
-100
-120
0
1.05
AIN = -1.0 dBFS
SNR = 70.9 dBFS
SFDR = 79.7 dBc
SINAD = 70.3 dBFS
180,000
0
0.95
VCM
FIGURE 12. SNR AND SFDR vs VCM
FIGURE 11. INTEGRAL NONLINEARITY
200,000
0.85
-40
-60
-80
-100
20
40
60
80
FREQUENCY (MHz)
100
FIGURE 15. SINGLE-TONE SPECTRUM @ 190MHz
16
120
-120
0
20
40
60
80
FREQUENCY (MHz)
100
120
FIGURE 16. SINGLE-TONE SPECTRUM @ 363MHz
FN7717.2
November 30, 2012
ISLA212P
Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C,
AIN = -1dBFS, fIN = 105MHz, fSAMPLE = 250MSPS. (Continued)
0
0
IMD2
IMD3
2ND HARMONICS
3RD HARMONICS
IMD2
IMD3
2ND HARMONICS
3RD HARMONICS
-20
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
-20
-40
-60
IMD3 = -87 dBFS
-80
-40
-60
IMD3 = -97 dBFS
-80
-100
-100
-120
-120
0
20
40
60
80
FREQUENCY (MHz)
100
120
FIGURE 17. TWO-TONE SPECTRUM (F1 = 70MHz, F2 = 71MHz AT
-7dBFS)
Theory of Operation
Functional Description
The ISLA212P is based on a 12-bit, 250MSPS A/D converter core
that utilizes a pipelined successive approximation architecture
(see Figure 19). The input voltage is captured by a Sample-Hold
Amplifier (SHA) and converted to a unit of charge. Proprietary
charge-domain techniques are used to successively compare the
input to a series of reference charges. Decisions made during the
successive approximation operations determine the digital code
for each input value. Digital error correction is also applied,
resulting in a total latency of 10 clock cycles. This is evident to the
user as a latency between the start of a conversion and the data
being available on the digital outputs.
Power-On Calibration
As mentioned previously, the cores perform a self-calibration at
start-up. An internal power-on-reset (POR) circuit detects the
supply voltage ramps and initiates the calibration when the
analog and digital supply voltages are above a threshold. The
following conditions must be adhered to for the power-on
calibration to execute successfully.
• A frequency-stable conversion clock must be applied to the
CLKP/CLKN pins.
0
Filename
Core fs (MHz)
20
40
60
80
FREQUENCY (MHz)
100
120
FIGURE 18. TWO-TONE SPECTRUM (F1 = 170MHz, F2 = 171MHz AT
-7dBFS)
A user-initiated reset can subsequently be invoked if these
conditions cannot be met at power-up.
After the power supply has stabilized, the internal POR releases
RESETN, and an internal pull-up pulls it high, which starts the
calibration sequence. If a subsequent user-initiated reset is
desired, the RESETN pin should be connected to an open-drain
driver with an off-state/high impedance state leakage of less
than 0.5mA. This assures exit from the reset state so calibration
can start.
The calibration sequence is initiated on the rising edge of
RESETN, as shown in Figure 20. Calibration status can be
determined by reading the cal_status bit (LSB) at 0xB6. This bit is
‘0’ during calibration and goes to a logic ‘1’ when calibration is
complete. The data outputs produce 0xCCCC during calibration;
this can also be used to determine calibration status.
If the selectable clock divider is set to 1 (default), the output
clock (CLKOUTP/CLKOUTN) will not be affected by the assertion
of RESETN. If the selectable clock divider is set to 2 or 4, the
output clock is set low while RESETN is asserted (low). Normal
operation of the output clock resumes at the next input clock
edge (CLKP/CLKN) after RESETN is de-asserted. At 250MSPS the
nominal calibration time is 200ms, while the maximum
calibration time is 550ms.
• DNC pins must not be connected.
• SDO has an internal pull-up and should not be driven
externally.
• RESETN is pulled low by the ADC internally during POR.
External driving of RESETN is optional.
• SPI communications must not be attempted.
17
FN7717.2
November 30, 2012
ISLA212P
CLOCK
GENERATION
INP
2.5-BIT
FLASH
2.5-BIT
FLASH
SHA
6- STAGE
1.5- BIT/ STAGE
3- STAGE
1- BIT/ STAGE
3- BIT
FLASH
INN
1.25V
+
–
DIGITAL
ERROR
CORRECTION
LVDS/LVCMOS
OUTPUTS
FIGURE 19. A/D CORE BLOCK DIAGRAM
CLKN
CLKP
CALIBRATION
TIME
A supply voltage variation of <100mV generally results in an SNR
change of <0.5dBFS and an SFDR change of <3dBc.
RESETN
CAL_STATUS
BIT
changes may necessitate recalibration, depending on system
performance requirements. Best performance is achieved by
recalibrating the A/D under the environmental conditions at
which it will operate.
CALIBRATION
BEGINS
CALIBRATION
COMPLETE
CLKOUTP
FIGURE 20. CALIBRATION TIMING
User Initiated Reset
Recalibration of the A/D can be initiated at any time by driving
the RESETN pin low for a minimum of one clock cycle. An
open-drain driver with a drive strength in its high impedance
state of less than 0.5mA is recommended, as RESETN has an
internal high impedance pull-up to OVDD. As is the case during
power-on reset, RESETN and DNC pins must be in the proper
state for the calibration to execute successfully.
In situations where the sample rate is not constant, best results
are obtained if the device is calibrated at the highest sample
rate. Reducing the sample rate by less than 80MSPS typically
results in an SNR change of <0.5dBFS and an SFDR change of
<3dBc.
Figures 21 through 26 show the effect of temperature on SNR
and SFDR performance, with power-on calibration performed at
-40°C, +25°C, and +85°C. Each plot shows the variation of
SNR/SFDR across temperature after a single power-on
calibration at -40°C, +25°C and +85°C. Best performance is
typically achieved by a user-initiated power on calibration at the
operating conditions, as stated previously. However, it can be
seen that performance drift with temperature is not a very strong
function of the temperature at which the power-on calibration is
performed.
The performance of the ISLA212P changes with variations in
temperature, supply voltage or sample rate. The extent of these
18
FN7717.2
November 30, 2012
ISLA212P
Temperature Calibration
72
95
130MSP
250MSPS
SFDR (dBc)
SNR (dBFS)
200MSP
250MSP
71
90
130MSPS
85
-2dBFS ANALOG INPUT
-2dBFS ANALOG INPUT
200MSP
-1 dBFS ANALOG INPUT
-1dBFS ANALOG INPUT
70
-40
-35
-30
TEMPERATURE (°C)
-25
80
-40
-20
FIGURE 21. TYPICAL SNR PERFORMANCE vs TEMPERATURE,
DEVICE CALIBRATED AT -40°C, fIN = 105MHz
-35
-30
TEMPERATURE (°C)
-25
-20
FIGURE 22. TYPICAL SFDR PERFORMANCE vs TEMPERATURE,
DEVICE CALIBRATED AT -40°C, fIN = 105MHz
72
95
200MSP
130MSPS
SFDR (dBc)
SNR (dBFS)
90
71
200MSPS
130MSPS
85
250MSPS
80
250MSPS
-2dBFS ANALOG INPUT
-2dBFS ANALOG INPUT
-1dBFS ANALOG INPUT
70
5
10
15
20
25
30
TEMPERATURE (°C)
35
40
75
45
FIGURE 23. TYPICAL SNR PERFORMANCE vs TEMPERATURE,
DEVICE CALIBRATED AT +25°C, fIN = 105MHz
-1dBFS ANALOG INPUT
5
10
15
20
25
30
TEMPERATURE (°C)
35
40
45
FIGURE 24. TYPICAL SFDR PERFORMANCE vs TEMPERATURE,
DEVICE CALIBRATED AT +25°C, fIN = 105MHz
72
90
200MSP
-2dBFS ANALOG INPUT
-1dBFS ANALOG INPUT
SFDR (dBc)
SNR (dBFS)
130MSPS
130MSPS
71
200MSPS
85
80 -2dBFS ANALOG INPUT
250MSPS
-1dBFS ANALOG INPUT
250MSPS
70
65
67
69
71
73
75
77
79
TEMPERATURE (°C)
81
83
85
FIGURE 25. TYPICAL SNR PERFORMANCE vs TEMPERATURE,
DEVICE CALIBRATED AT +85°C, fIN = 105MHz
19
75
65
70
75
TEMPERATURE (°C)
80
85
FIGURE 26. TYPICAL SFDR PERFORMANCE vs TEMPERATURE,
DEVICE CALIBRATED AT +85°C, fIN = 105MHz
FN7717.2
November 30, 2012
ISLA212P
Analog Input
A single, fully differential input (VINP/VINN) connects to the
sample-and-hold amplifier (SHA) of each unit A/D. The ideal
full-scale input voltage is 2.0V, centered at the VCM voltage of
0.94V, as shown in Figure 27.
A/D
VINN
1.8
VINP
1.4
VCM
0.94V
1.0V
1.0
FIGURE 30. DIFFERENTIAL AMPLIFIER INPUT
0.6
0.2
FIGURE 27. ANALOG INPUT RANGE
Best performance is obtained when the analog inputs are driven
differentially. The common-mode output voltage, VCM, should be
used to properly bias the inputs, as shown in Figures 28
through 30. An RF transformer gives the best noise and
distortion performance for wideband and high intermediate
frequency (IF) inputs. Two different transformer input schemes
are shown in Figures 28 and 29.
ADT1-1WT
ADT1-1WT
1000pF
A/D
VCM
0.1µF
FIGURE 28. TRANSFORMER INPUT FOR GENERAL PURPOSE
APPLICATIONS
A differential amplifier, as shown in the simplified block diagram
in Figure 30, can be used in applications that require DC
coupling. In this configuration, the amplifier typically dominates
the achievable SNR and distortion performance. The new Intersil
ISL552xx differential amplifier family can also be used in certain
AC applications with minimal performance degradation. Contact
Intersil sales support with your needs.
Clock Input
The clock input circuit is a differential pair (see Figure 44).
Driving these inputs with a high level (up to 1.8VP-P on each
input) sine or square wave provides the lowest jitter
performance. A transformer with 4:1 impedance ratio provides
increased drive levels. The clock input is functional with
AC-coupled LVDS, LVPECL, and CML drive levels. To maintain the
lowest possible aperture jitter, a high slew rate at the zero
crossing of the differential clock input signal is recommended.
The recommended drive circuit is shown in Figure 31. A duty
range of 40% to 60% is acceptable. The clock can be driven
single-ended, but this reduces the edge rate and may affect SNR
performance. The clock inputs are internally self-biased to
AVDD/2 to facilitate AC coupling.
TC4-19G2+
ADTL1-12
1000pF
TX-2-5-1
1000pF
CLKP
A/D
200
0.01µF
VCM
1000pF
CLKN
1000pF
FIGURE 29. TRANSMISSION-LINE TRANSFORMER INPUT FOR
HIGH IF APPLICATIONS
This dual transformer scheme is used to improve common-mode
rejection, which keeps the common-mode level of the input
matched to VCM. The value of the shunt resistor should be
determined based on the desired load impedance. The
differential input resistance of the ISLA212P is 600Ω.
The SHA design uses a switched capacitor input stage (see
Figure 43), which creates current spikes when the sampling
capacitance is reconnected to the input voltage. This causes a
disturbance at the input, which must settle before the next
sampling point. Lower source impedance results in faster settling
and improved performance; therefore, a 2:1 or 1:1 transformer
and low shunt resistance are recommended for optimal
performance.
20
1000pF
FIGURE 31. RECOMMENDED CLOCK DRIVE
A selectable 2x or 4x frequency divider is provided in series with
the clock input. The divider can be used in the 2x mode with a
sample clock equal to twice the desired sample rate or in 4x
mode with a sample clock equal to four times the desired
sample rate. This allows the use of the Phase Slip feature, which
enables synchronization of multiple ADCs. The Phase Slip feature
can be used as an alternative to the CLKDIVRST pins to
synchronize ADCs in a multiple ADC system.
FN7717.2
November 30, 2012
ISLA212P
Digital Outputs
TABLE 1. CLKDIV PIN SETTINGS
CLKDIV PIN
DIVIDE RATIO
AVSS
2
Float
1
AVDD
4
Output data is available as a parallel bus in LVDS-compatible
(default) or CMOS modes. In either case, the data is presented in
double data rate (DDR) format. Figures 1 and 2 show the timing
relationships for LVDS and CMOS modes, respectively.
The clock divider can also be controlled through the SPI port,
which overrides the CLKDIV pin setting. See “SPI Physical
Interface” on page 25. A delay-locked loop (DLL) generates
internal clock signals for various stages within the charge
pipeline. If the frequency of the input clock changes, the DLL may
take up to 52μs to regain lock at 250MSPS. The lock time is
inversely proportional to the sample rate.
The DLL has two ranges of operation: slow and fast. The slow
range can be used for sample rates between 40MSPS and
100MSPS, while the default fast range can be used from
80MSPS to the maximum specified sample rate.
Additionally, the drive current for LVDS mode can be set to a
nominal 3mA (default) or a power-saving 2mA. The lower current
setting can be used in designs where the receiver is in close
physical proximity to the A/D. The applicability of this setting is
dependent upon the PCB layout; therefore, the user should
experiment to determine whether performance degradation is
observed.
The output mode can be controlled through the SPI port by
writing to address 0x73 (see “Serial Peripheral Interface” on
page 25).
An external resistor creates the bias for the LVDS drivers. A 10kΩ,
1% resistor must be connected from the RLVDS pin to OVSS.
Jitter
Power Dissipation
In a sampled data system, clock jitter directly impacts the
achievable SNR performance. The theoretical relationship
between clock jitter (tJ) and SNR is shown in Equation 1 and
illustrated in Figure 32.
The power dissipated by the ISLA212P is primarily dependent on
the sample rate and the output modes: LVDS vs CMOS and DDR
vs SDR. There is a static bias in the analog supply, while the
remaining power dissipation is linearly related to the sample
rate. The output supply dissipation changes to a lesser degree in
LVDS mode but is more strongly related to the clock frequency in
CMOS mode.
1
SNR = 20 log 10 ⎛ -------------------⎞
⎝ 2πf t ⎠
IN J
(EQ. 1)
Nap/Sleep
100
95
Portions of the device may be shut down to save power during
times when operation of the A/D is not required. Two power saving
modes are available: Nap, and Sleep. Nap mode reduces power
dissipation to < 60mW while Sleep mode reduces power
dissipation to 9mW typically.
tj = 0.1ps
90
14 BITS
SNR (dB)
85
80
tj = 1ps
75
12 BITS
70
tj = 10ps
65
60
10 BITS
tj = 100ps
55
50
1M
10M
100M
INPUT FREQUENCY (Hz)
1G
FIGURE 32. SNR vs CLOCK JITTER
This relationship shows the SNR that would be achieved if clock
jitter were the only non-ideal factor. In reality, achievable SNR is
limited by internal factors such as linearity, aperture jitter and
thermal noise. Internal aperture jitter is the uncertainty in the
sampling instant shown in Figure1A. The internal aperture jitter
combines with the input clock jitter in a root-sum-square fashion
(not statistically correlated), which determines the total jitter in
the system. The total jitter, combined with other noise sources,
then determines the achievable SNR.
Voltage Reference
A temperature compensated internal voltage reference provides
the reference charges used in the successive approximation
operations. The full-scale range of each A/D is proportional to the
reference voltage. The nominal value of the voltage reference is
1.25V.
21
All digital outputs (Data, CLKOUT and OR) are placed in a high
impedance state during Nap or Sleep. The input clock should
remain running and at a fixed frequency during Nap or Sleep, and
CSB should be high. Recovery time from Nap mode will increase
if the clock is stopped, since the internal DLL can take up to 52µs
to regain lock at 250MSPS.
By default after the device is powered on, the operational state is
controlled by the NAPSLP pin as shown in Table 2.
TABLE 2. NAPSLP PIN SETTINGS
NAPSLP PIN
MODE
AVSS
Normal
Float
Sleep
AVDD
Nap
The power-down mode can also be controlled through the SPI
port, which overrides the NAPSLP pin setting. Details on this are
contained in “Serial Peripheral Interface” on page 25.
FN7717.2
November 30, 2012
ISLA212P
Data Format
Output data can be presented in three formats: two’s
complement (default), Gray code and offset binary. The data
format can be controlled through the SPI port, by writing to
address 0x73. Details on this are contained in “Serial Peripheral
Interface” on page 25.
Offset binary coding maps the most negative input voltage to
code 0x000 (all zeros) and the most positive input to 0xFFF (all
ones). Two’s complement coding simply complements the MSB
of the offset binary representation.
When calculating Gray code the MSB is unchanged. The
remaining bits are computed as the XOR of the current bit
position and the next most significant bit. Figure 33 shows this
operation.
BINARY
11
10
9
••••
1
11
10
••••
9
1
0
FIGURE 33. BINARY TO GRAY CODE CONVERSION
Converting back to offset binary from Gray code must be done
recursively, using the result of each bit for the next lower bit as
shown in Figure 34.
GRAY CODE
11
10
9
••••
1
TABLE 3. INPUT VOLTAGE TO OUTPUT CODE MAPPING
INPUT
VOLTAGE
OFFSET BINARY
TWO’S
COMPLEMENT
GRAY CODE
–Full Scale
0000 0000 0000
1000 0000 0000
0000 0000 0000
–Full Scale
+ 1LSB
0000 0000 0001
1000 0000 0001
0000 0000 0001
Mid–Scale
1000 0000 0000
0000 0000 0000
1100 0000 0000
+Full Scale
– 1LSB
1111 1111 1110
0111 1111 1110
1000 0000 0001
+Full Scale
1111 1111 1111
0111 1111 1111
1000 0000 0000
Clock Divider Synchronous Reset
0
••••
GRAY CODE
Mapping of the input voltage to the various data formats is
shown in Table 3.
0
If the selectable clock divider is used, the ADC's internal sample
clock will be at half the frequency (DIV=2) or one quarter the
frequency (DIV=4) of the device clock. The phase relationship
between the sample clock and the device clock is initially
indeterminate. An output clock (CLKOUTP, CLKOUTN) is provided
to facilitate latching of the sampled data and estimation of the
internal sample clock's phase. The output clock has a fixed
phase relationship to the sample clock. When the selectable
clock divider is set to 2 or 4, the output clock's phase relationship
to the sample clock remains fixed but is initially indeterminate
with respect to the device clock. When the selectable clock
divider is set to 2 or 4, the synchronous clock divider reset
feature allows the phase of the internal sample clock and the
output clock to be synchronized (refer to Figure 35) with respect
to the device clock. This simplifies data capture in systems
employing multiple A/Ds where sampling of the inputs is desired
to be synchronous.
The reset signal must be well-timed with respect to the sample
clock (See “Switching Specifications” on page 13).
A 100Ω differential termination resistor must be supplied
between CLKDIVRSTP and CLKDIVRSTN, external to the ADC, (on
the PCB) and should be located as close to the CLKDIVRSTP/N
pins as possible.
••••
••••
BINARY
11
10
9
••••
1
0
FIGURE 34. GRAY CODE TO BINARY CONVERSION
22
FN7717.2
November 30, 2012
ISLA212P
DEVICE
CLOCK
DEVICE
CLOCK
INPUT
NPUT
L+td
(Note 13)
ANALOG INPUT
s1
tRSTH
CLKDIVRSTP (Note 14)
tRSTS
tRSTRT
ADC1 OUTPUT DATA
s0
ODD
s0
EVEN
s1
ODD
s1
EVEN
s0
ODD
s0
EVEN
s1
ODD
s1
EVEN
ADC1 CLKOUTP
ADC2 OUTPUT DATA
ADC2 CLKOUTP
(PHASE 1) (Note 15)
ADC2 CLKOUTP (Note 15)
(PHASE 2)
NOTES:
13. Delay equals fixed pipeline latency (L cycles of sample clock) plus fixed analog propagation
delay, td.
14. CLKDIVRSTP setup and hold times are with respect to input sample clock rising edge.
CLKDIVRSTN is not shown but must be driven, and is the complement of CLKDIVRSTP.
15. Either Output Clock Phase (phase 1 or phase 2 ) equally likely prior to synchronization.
FIGURE 35. SYNCHRONOUS RESET OPERATION, CLOCK DIVIDE = 2, DDR-MODE
CSB
SCLK
SDIO
R/W
W1
W0
A12
A11
A10
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
D2
D3
D4
D5
D6
D7
FIGURE 36. MSB-FIRST ADDRESSING
CSB
SCLK
SDIO
A0
A1
A2
A11
A12
W0
W1
R/W
D0
D1
FIGURE 37. LSB-FIRST ADDRESSING
23
FN7717.2
November 30, 2012
ISLA212P
tDSW
CSB
tCLK
tHI
tDHW
tS
tH
tLO
SCLK
SDIO
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
D4
D3
D2
D1
D0
SPI WRITE
FIGURE 38. SPI WRITE
tDSW
CSB
tCLK
tHI
tDVR
tS
tDHW
tHR
tLO
SCLK
WRITING A READ COMMAND
READING DATA
(3-WIRE MODE)
SDIO
R/W
W1
W0
A12
A11
A10
A9
A2
A1
A0
D7
D6
D3
SDO
D2
D1
D0
(4-WIRE MODE)
D7
D3
D2
D1
D0
SPI READ
FIGURE 39. SPI READ
CSB STALLING
CSB
SCLK
SDIO
INSTRUCTION/ADDRESS
DATA WORD 1
DATA WORD 2
FIGURE 40. 2-BYTE TRANSFER
LAST LEGAL
CSB STALLING
CSB
SCLK
SDIO
INSTRUCTION/ADDRESS
DATA WORD 1
DATA WORD N
FIGURE 41. N-BYTE TRANSFER
24
FN7717.2
November 30, 2012
ISLA212P
Serial Peripheral Interface
A serial peripheral interface (SPI) bus is used to facilitate
configuration of the device and to optimize performance. The
SPI bus consists of chip select (CSB), serial clock (SCLK) serial
data output (SDO), and serial data input/output (SDIO). The
maximum SCLK rate is equal to the A/D sample rate (fSAMPLE)
divided by 16 for both write operations and read operations. At
fSAMPLE = 250MHz, maximum SCLK is 15.63MHz for writing
and read operations. There is no minimum SCLK rate.
The following sections describe various registers that are used to
configure the SPI or adjust performance or functional parameters.
Many registers in the available address space (0x00 to 0xFF) are
not defined in this document. Additionally, within a defined
register there may be certain bits or bit combinations that are
reserved. Undefined registers and undefined values within defined
registers are reserved and should not be selected. Setting any
reserved register or value may produce indeterminate results.
After the instruction/address bytes have been read, the
appropriate number of data bytes are written to or read from the
A/D (based on the R/W bit status). The data transfer will
continue as long as CSB remains low and SCLK is active. Stalling
of the CSB pin is allowed at any byte boundary
(instruction/address or data) if the number of bytes being
transferred is three or less. For transfers of four bytes or more,
CSB is allowed to stall in the middle of the instruction/address
bytes or before the first data byte. If CSB transitions to a high
state after that point the state machine will reset and terminate
the data transfer.
TABLE 4. BYTE TRANSFER SELECTION
[W1:W0]
BYTES TRANSFERRED
00
1
SPI Physical Interface
The serial clock pin (SCLK) provides synchronization for the data
transfer. By default, all data is presented on the serial data
input/output (SDIO) pin in three-wire mode. The state of the SDIO
pin is set automatically in the communication protocol
(described in the following). A dedicated serial data output pin
(SDO) can be activated by setting 0x00[7] high to allow operation
in four-wire mode.
The SPI port operates in a half duplex master/slave
configuration, with the ISLA212P functioning as a slave. Multiple
slave devices can interface to a single master in three-wire mode
only, since the SDO output of an unaddressed device is asserted
in four wire mode.
The chip-select bar (CSB) pin determines when a slave device is
being addressed. Multiple slave devices can be written to
concurrently, but only one slave device can be read from at a
given time (again, only in three-wire mode). If multiple slave
devices are selected for reading at the same time, the results will
be indeterminate.
The communication protocol begins with an instruction/address
phase. The first rising SCLK edge following a high-to-low
transition on CSB determines the beginning of the two-byte
instruction/address command; SCLK must be static low before
the CSB transition. Data can be presented in MSB-first order or
LSB-first order. The default is MSB-first, but this can be changed
by setting 0x00[6] high. Figures 36 and 37 show the appropriate
bit ordering for the MSB-first and LSB-first modes, respectively. In
MSB-first mode, the address is incremented for multi-byte
transfers, while in LSB-first mode it is decremented.
In the default mode, the MSB is R/W, which determines if the
data is to be read (active high) or written. The next two bits, W1
and W0, determine the number of data bytes to be read or
written (see Table 4). The lower 13 bits contain the first address
for the data transfer. This relationship is illustrated in Figure 38,
and timing values are given in “Switching Specifications” on
page 13.
25
01
2
10
3
11
4 or more
Figures 40 and 41 on page 24 illustrate the timing relationships
for 2-byte and N-byte transfers, respectively. The operation for a
3-byte transfer can be inferred from these diagrams.
SPI Configuration
ADDRESS 0X00: CHIP_PORT_CONFIG
Bit ordering and SPI reset are controlled by this register. Bit order
can be selected as MSB to LSB (MSB first) or LSB to MSB (LSB
first) to accommodate various micro controllers.
Bit 7 SDO Active
Bit 6 LSB First
Setting this bit high configures the SPI to interpret serial data
as arriving in LSB to MSB order.
Bit 5 Soft Reset
Setting this bit high resets all SPI registers to default values.
Bit 4 Reserved
This bit should always be set high.
Bits 3:0 These bits should always mirror bits 4:7 to avoid
ambiguity in bit ordering.
ADDRESS 0X02: BURST_END
If a series of sequential registers are to be set, burst mode can
improve throughput by eliminating redundant addressing. The
burst is ended by pulling the CSB pin high. Setting the burst_end
address determines the end of the transfer; during a write
operation, the user must be cautious to transmit the correct
number of bytes based on the starting and ending addresses.
FN7717.2
November 30, 2012
ISLA212P
Bits 7:0 Burst End Address
This register value determines the ending address of the burst
data.
register value then write the incremented or decremented value
back to the same register. Bit 0 in register 0xFE must be set high
to enable updates written to 0x23 and 0x24 to be used by the
ADC (see description for 0xFE).
Device Information
TABLE 6. COARSE GAIN ADJUSTMENT
ADDRESS 0X08: CHIP_ID
0x22[3:0] CORE 0
0x26[3:0] CORE 1
ADDRESS 0X09: CHIP_VERSION
The generic die identifier and a revision number, respectively, can
be read from these two registers.
Device Configuration/Control
A common SPI map, which can accommodate single-channel or
multi-channel devices, is used for all Intersil A/D products.
ADDRESS 0X20: OFFSET_COARSE_ADC0
ADDRESS 0X21: OFFSET_FINE_ADC0
The input offset of the A/D core can be adjusted in fine and
coarse steps. Both adjustments are made via an 8-bit word as
detailed in Table 5. The data format is twos complement.
The default value of each register will be the result of the selfcalibration after initial power-up. If a register is to be
incremented or decremented, the user should first read the
register value then write the incremented or decremented value
back to the same register. Bit 0 in register 0xFE must be set high
to enable updates written to 0x20 and 0x21 to be used by the
ADC (see description for 0xFE).
TABLE 5. OFFSET ADJUSTMENTS
NOMINAL COARSE GAIN ADJUST
(%)
Bit3
+2.8
Bit2
+1.4
Bit1
-2.8
Bit0
-1.4
TABLE 7. MEDIUM AND FINE GAIN ADJUSTMENTS
PARAMETER
0x23[7:0]
MEDIUM GAIN
0x24[7:0]
FINE GAIN
Steps
256
256
–Full Scale (0x00)
-2%
-0.20%
Mid–Scale (0x80)
0.00%
0.00%
+Full Scale (0xFF)
+2%
+0.2%
Nominal Step Size
0.016%
0.0016%
ADDRESS 0X25: MODES
Two distinct reduced power modes can be selected. By default,
the tri-level NAPSLP pin can select normal operation, nap or
sleep modes (refer to“Nap/Sleep” on page 21). This functionality
can be overridden and controlled through the SPI. This is an
indexed function when controlled from the SPI, but a global
function when driven from the pin. This register is not changed by
a Soft Reset.
PARAMETER
0x20[7:0]
COARSE OFFSET
0x21[7:0]
FINE OFFSET
Steps
255
255
–Full Scale (0x00)
-133LSB (-47mV)
-5LSB (-1.75mV)
VALUE
0x25[2:0]
POWER DOWN MODE
Mid–Scale (0x80)
0.0LSB (0.0mV)
0.0LSB
000
Pin Control
+Full Scale (0xFF)
+133LSB (+47mV)
+5LSB (+1.75mV)
001
Normal Operation
Nominal Step Size
1.04LSB (0.37mV)
0.04LSB (0.014mV)
010
Nap Mode
100
Sleep Mode
ADDRESS 0X22: GAIN_COARSE_ADC0
ADDRESS 0X23: GAIN_MEDIUM_ADC0
ADDRESS 0X24: GAIN_FINE_ADC0
Gain of the A/D core can be adjusted in coarse, medium and fine
steps. Coarse gain is a 4-bit adjustment while medium and fine
are 8-bit. Multiple Coarse Gain Bits can be set for a total
adjustment range of ±4.2%. (‘0011’ ≅ -4.2% and ‘1100’ ≅ +4.2%)
It is recommended to use one of the coarse gain settings (-4.2%,
-2.8%, -1.4%, 0, 1.4%, 2.8%, 4.2%) and fine-tune the gain using the
registers at 0x0023 and 0x24.
The default value of each register will be the result of the selfcalibration after initial power-up. If a register is to be
incremented or decremented, the user should first read the
26
TABLE 8. POWER-DOWN CONTROL
ADDRESS 0X26: OFFSET_COARSE_ADC1
ADDRESS 0X27: OFFSET_FINE_ADC1
The input offset of A/D core#1 can be adjusted in fine and
coarse steps in the same way that offset for core#0 can be
adjusted. Both adjustments are made via an 8-bit word as
detailed in Table 5. The data format is two’s complement.
The default value of each register will be the result of the selfcalibration after initial power-up. If a register is to be incremented or
decremented, the user should first read the register value then write
the incremented or decremented value back to the same register.
FN7717.2
November 30, 2012
ISLA212P
Bit 0 in register 0xFE must be set high to enable updates written to
0x26 and 0x27 to be used by the ADC (see description for 0xFE).
ADDRESS 0X28: GAIN_COARSE_ADC1
ADDRESS 0X29: GAIN_MEDIUM_ADC1
ADDRESS 0X2A: GAIN_FINE_ADC1
Gain of A/D core #1 can be adjusted in coarse, medium and fine
steps in the same way that core #0 can be adjusted. Coarse gain is
a 4-bit adjustment while medium and fine are 8-bit. Multiple
Coarse Gain Bits can be set for a total adjustment range of ±4.2.
Bit 0 in register 0xFE must be set high to enable updates written to
0x29 and 0x2A to be used by the ADC (see description for 0xFE).
ADDRESS 0X73: OUTPUT_MODE_A
The output_mode_A register controls the physical output format
of the data, as well as the logical coding. The ISLA212P can
present output data in two physical formats: LVDS (default) or
LVCMOS. Additionally, the drive strength in LVDS mode can be set
high (default, 3mA or low (2mA).
Data can be coded in three possible formats: two’s complement
(default), Gray code or offset binary. See Table 11.
This register is not changed by a Soft Reset.
TABLE 10. OUTPUT MODE CONTROL
Global Device Configuration/Control
VALUE
0x73[7:5]
OUTPUT MODE
000
LVDS 3mA (Default)
001
LVDS 2mA
100
LVCMOS
ADDRESS 0X71: PHASE_SLIP
The output data clock is generated by dividing down the A/D input
sample clock. Some systems with multiple A/Ds can more easily latch
the data from each A/D by controlling the phase of the output data
clock. This control is accomplished through the use of the phase_slip
SPI feature, which allows the rising edge of the output data clock to be
advanced by one input clock period, as shown in Figure 42. Execution of
a phase_slip command is accomplished by first writing a '0' to bit 0 at
address 0x71, followed by writing a '1' to bit 0 at address 0x71.
ADC Input
Clock (500MHz)
VALUE
0x73[2:0]
OUTPUT FORMAT
000
Two’s Complement (Default)
010
Gray Code
100
Offset Binary
ADDRESS 0X74: OUTPUT_MODE_B
2ns
Output Data
Clock (250MHz)
No clock_slip
TABLE 11. OUTPUT FORMAT CONTROL
4ns
Bit 6 DLL Range
This bit sets the DLL operating range to fast (default) or slow.
2ns
Output Data
Clock (250MHz)
1 clock_slip
Internal clock signals are generated by a delay-locked loop (DLL),
which has a finite operating range. Table 12 shows the allowable
sample rate ranges for the slow and fast settings.
Output Data
Clock (250MHz)
2 clock_slip
Bit 4 DDR Enable
FIGURE 42. PHASE SLIP
Set to a ‘1’ to enable DDR.
ADDRESS 0X72: CLOCK_DIVIDE
TABLE 12. DLL RANGES
The ISLA212P has a selectable clock divider that can be set to
divide by four, two or one (no division). By default, the tri-level
CLKDIV pin selects the divisor. This functionality can be
overridden and controlled through the SPI, as shown in Table 9.
This register is not changed by a Soft Reset.
TABLE 9. CLOCK DIVIDER SELECTION
VALUE
0x72[2:0]
CLOCK DIVIDER
000
Pin Control
001
Divide by 1
010
Divide by 2
100
Divide by 4
other
Not Allowed
27
DLL RANGE
MIN
MAX
UNIT
Slow
40
100
MSPS
Fast
80
250
MSPS
ADDRESS 0XB6: CALIBRATION STATUS
The LSB at address 0xB6 can be read to determine calibration
status. The bit is ‘0’ during calibration and goes to a logic ‘1’
when calibration is complete. This register is unique in that it can
be read after POR at calibration, unlike the other registers on
chip, which cannot be read until calibration is complete.
DEVICE TEST
The ISLA212P can produce preset or user defined patterns on
the digital outputs to facilitate in-situ testing. A user can pick
from preset built-in patterns by writing to the output test mode
FN7717.2
November 30, 2012
ISLA212P
field [7:4] at 0xC0 or user defined patterns by writing to the user
test mode field [2:0] at 0xC0. The user defined patterns should
be loaded at address space 0xC1 through 0xD0, see the “SPI
Memory Map” on page 30 for more detail. The predefined
patterns are shown in Table 13. The test mode is enabled
asynchronously to the sample clock, therefore several sample
clock cycles may elapse before the data is present on the output
bus.
ADDRESS 0XC7: USER_PATT4_LSB
ADDRESS 0XC0: TEST_IO
ADDRESS 0XCA: USER_PATT5_MSB
Bits 7:4 Output Test Mode
These bits set the test mode according to Table 13. Other values
are reserved. User test patterns loaded at 0xC1 through 0xD0 are
also available by writing ‘1000’ to [7:4] at 0xC0 and a pattern
depth value to [2:0] at 0xC0. See “SPI Memory Map” on page 30.
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 5.
Bits 2:0 User Test Mode
The three LSBs in this register determine the test pattern in
combination with registers 0xC1 through 0xD0. Refer to the
SPI Memory Map on page 30.
ADDRESS 0XC8: USER_PATT4_MSB
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 4.
ADDRESS 0XC9: USER_PATT5_LSB
ADDRESS 0XCB: USER_PATT6_LSB
ADDRESS 0XCC: USER_PATT6_MSB
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 6.
ADDRESS 0XCD: USER_PATT7_LSB
ADDRESS 0XCE: USER_PATT7_MSB
TABLE 13. OUTPUT TEST MODES
VALUE
0xC0[7:4]
OUTPUT TEST MODE
WORD 1
WORD 2
0000
Off
0001
Midscale
0x8000
N/A
0010
Positive Full-Scale
0xFFFF
N/A
0011
Negative Full-Scale
0x0000
N/A
0100
SDR/DDR Dependent
N/A
N/A
0101
Reserved
N/A
N/A
0110
Reserved
N/A
N/A
0111
SDR/DDR Dependent
N/A
N/A
1000
User Pattern
user_patt1
user_patt2
1001
Reserved
N/A
N/A
1010
Ramp
N/A
N/A
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 7.
ADDRESS 0XCF: USER_PATT8_LSB
ADDRESS 0XC1: USER_PATT1_LSB
ADDRESS 0XC2: USER_PATT1_MSB
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 1.
ADDRESS 0XC3: USER_PATT2_LSB
ADDRESS 0XC4: USER_PATT2_MSB
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 2
ADDRESS 0XC5: USER_PATT3_LSB
ADDRESS 0XC6: USER_PATT3_MSB
ADDRESS 0XD0: USER_PATT8_MSB
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 8.
ADDRESS 0XFE: OFFSET/GAIN_ADJUST_ENABLE
Bit 0 at this register must be set high to enable adjustment of
offset coarse and fine adjustments (0x20 and 0x21), and gain
medium and fine adjustments (0x23 and 0x24). It is
recommended that new data be written to the offset and gain
adjustment registers and while Bit 0 is a '0'. Subsequently, Bit 0
should be set to '1' to allow the values written to the
aforementioned registers to be used by the ADC. Bit 0 should be
set to a '0' upon completion.
Digital Temperature Sensor
ADDRESS 0X4B: TEMP_COUNTER_HIGH
Bits [2:0] of this register hold the 3 MSBs of the 11-bit
temperature code.
Bit [7] of this register indicates a valid temperature_counter read
was performed. A logic ‘1’ indicates a valid read.
ADDRESS 0X4C: TEMP_COUNTER_LOW
Bits [7:0] of this register hold the lower 8 LSBs of the 11-bit
temperature code.
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 3
28
FN7717.2
November 30, 2012
ISLA212P
ADDRESS 0X4D: TEMP_COUNTER_CONTROL
Bit [7] Measurement mode select bit, set to ‘1’ for recommended
PTAT mode. ‘0’ (default) is IPTAT mode and is less accurate and
not recommended.
Bit [6] Temperature counter enable bit. Set to ‘1’ to enable.
Bit [5] Temperature counter power down bit. Set to ‘1’ to
power-down temperature counter.
Bit [4] Temperature counter reset bit. Set to ‘1’ to reset count.
Bit [3:1] Three bit frequency divider field. Sets temperature
counter update rate. Update rate is proportional to ADC sample
clock rate and divide ratio. A ‘101’ updates the temp counter
every ~66µs (for 250MSPS). Faster updates rates result in lower
precision.
information that can be used to decide when to recalibrate the
A/D as needed.
The nominal transfer function of the temperature monitor should
be estimated for each device by reading the temperature sensor
at two temperatures and extrapolating a line through these two
points.
A typical temperature measurement can occur as follows:
1. Write ‘0xCA’ to address 0x4D - enable temp counter,
divide = ‘101’
2. Wait ≥ 132µs (at 250Msps) - longer wait time ensures the
sensor completes one valid cycle.
3. Write ‘0x20’ to address 0x4D - power down, disable temp
counter - recommended between measurements. This
ensures that the output does not change between MSB and
LSB reads.
Bit [0] Select sampler bit. Set to ‘0’.
4. Read address 0x4B (MSBs)
This set of registers provides digital access to an PTAT or
IPTAT-based temperature sensor, allowing the system to
estimate the temperature of the die, allowing easy access to
5. Read address 0x4C (LSBs)
29
6. Record temp code value
7. Write ‘0x20’ to address 0x4D - power-down, disable temp
counter. Contact the factory for more information if needed.
FN7717.2
November 30, 2012
ISLA212P
Device Config/Control
DUT Info
SPI Config/Control
SPI Memory Map
ADDR.
(Hex)
PARAMETER NAME
BIT 7 (MSB)
BIT 6
BIT 5
00
Port_config
SDO Active
LSB First
Soft Reset
01
Reserved
Reserved
02
Burst_end
Burst end address [7:0]
03-07
Reserved
Reserved
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0 (LSB)
Mirror (bit5) Mirror (bit6) Mirror (bit7)
DEF. VALUE
(HEX)
00h
00h
08
Chip_id
Chip ID #
Read only
09
Chip_version
Chip Version #
Read only
0A-0F
Reserved
Reserved
10-1F
Reserved
Reserved
20
Offset_coarse_adc0
Coarse Offset
cal. value
21
Offset_fine_adc0
22
Gain_coarse_adc0
Fine Offset
23
Gain_medium_adc0
Medium Gain
cal. value
24
Gain_fine_adc0
Fine Gain
cal. value
25
Modes_adc0
26
Offset_coarse_adc1
Coarse Offset
cal. value
27
Offset_fine_adc1
Fine Offset
cal. value
Reserved
Reserved
28
Gain_coarse_adc1
29
Gain_medium_adc1
Reserved
Coarse Gain
Gain_fine_adc1
Modes_adc1
2C-2F
Reserved
Reserved
30-4A
Reserved
Reserved
4B
Temp_counter_high
Temp_counter_low
cal. value
cal. value
Power Down Mode ADC1 [2:0]
000 = Pin Control
001 = Normal Operation
010 = Nap
100 = Sleep
Other codes = Reserved
00h
NOT reset by
Soft Reset
Temp Counter [10:8]
Read only
Temp Counter [7:0]
Enable
PD
Reset
4E-6F
Reserved
Reserved
70
Skew_diff
Differential Skew
71
Phase_slip
72
Clock_divide
73
Output_mode_A
Reserved
30
cal. value
Fine Gain
Reserved
Temp_counter_control
00h
NOT reset by
Soft Reset
Medium Gain
2A
4C
cal. value
Power Down Mode ADC0 [2:0]
000 = Pin Control
001 = Normal Operation
010 = Nap
100 = Sleep
Other codes = Reserved
2B
4D
cal. value
Coarse Gain
Output Mode [7:5]
000 = LVDS 3mA (Default)
001 = LVDS 2mA
100 = LVCMOS
Other codes = Reserved
Read only
Divider [2:0]
Select
00h
80h
Next Clock
Edge
00h
Clock Divide [2:0]
000 = Pin Control
001 = divide by 1
010 = divide by 2
100 = divide by 4
Other codes = Reserved
00h
NOT reset by
Soft Reset
Output Format [2:0]
000 = Two’s Complement (Default)
010 = Gray Code
100 = Offset Binary
Other codes = Reserved
00h
NOT reset by
Soft Reset
FN7717.2
November 30, 2012
ISLA212P
Device Test
Device Config/Control
SPI Memory Map
ADDR.
(Hex)
PARAMETER NAME
74
Output_mode_B
75-B5
Reserved
B6
Cal_status
B7-BF
Reserved
C0
Test_io
(Continued)
BIT 7 (MSB)
BIT 6
BIT 5
DLL Range
0 = Fast
1 = Slow
Default=’0’
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0 (LSB)
DDR Enable
DEF. VALUE
(HEX)
00h
NOT reset by
Soft Reset
Reserved
Calibration
Done
Output Test Mode [7:4]
User Test Mode [2:0]
Part in SDR Mode
0 = Off (Note 15)
1 = Midscale Short
2 = +FS Short
3 = -FS Short
4 = Checkerboard Output (0xAAAA, 0x5555) (Note 16)
7 = 0xFFFF, 0x0000 all on pattern (Note 17)
8 = User Pattern (1 to 8 deep, MSB Justified)
10 = Ramp
5, 6, 9, 11-15 = Reserved
Part in SDR Mode
0 = User pattern 1 only
1 = Cycle pattern 1 through 2
2 = Cycle pattern 1 through 3
3 = Cycle pattern 1 through 4
4 = Cycle pattern 1 through 5
5= Cycle pattern 1 through 6
6 = Cycle pattern 1 through7
7 = Cycle pattern 1 through 8
Part in DDR Mode
0 = Off (Note 15)
1 = Midscale Short
2 = +FS Short16
3 = -FS Short
4 = Reserved (Note 16)
7 = Reserved (Note 17)
8 = User Pattern (1 to 4 deep, MSB Justified)
10 = Ramp
5, 6, 9, 11-15 = Reserved
Part in DDR Mode
0 = User pattern 1 only
1 = Cycle pattern 1,3
2 = Cycle pattern 1,3,5
3 = Cycle pattern 1,3,5,7
4-7 = NA
Read Only
00h
C1
User_patt1_lsb
B7
B6
B5
B4
B3
B2
B1
B0
0x00
C2
User_patt1_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
C3
User_patt2_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
C4
User_patt2_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
C5
User_patt3_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
C6
User_patt3_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
C7
User_patt4_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
C8
User_patt4_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
C9
User_patt5_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
CA
User_patt5_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
CB
User_patt6_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
CC
User_patt6_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
CD
User_patt7_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
CE
User_patt7_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
CF
User_patt8_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
B15
B14
B13
B12
B11
B10
B9
B8
00h
Enable
1 = Enable
00h
D0
User_patt8_msb
D1-FF
Reserved
FE
Offset/Gain_Adjust_Enable
FF
Reserved
Reserved
Reserved
Reserved
NOTES:
15. During Calibration xCCCC (MSB justified) is presented at the output data bus, toggling on the LSB (and higher) data bits occurs at completion of calibration. This
behavior can be used as an option to determine calibration state.
16. Use test_io = 0x80 and User Pattern 1 = 0x9999 for Checkerboard outputs in DDR mode. In SDR mode, write ‘0x41’ to test_io for Checkerboard outputs.
17. Use test_io = 0x80 and User Pattern 1 = 0xAAAA for all ones/zeroes outputs in DDR mode. In SDR mode, write ‘0x71’ to test_io for all ones/zeros outputs.
31
FN7717.2
November 30, 2012
ISLA212P
Equivalent Circuits
AVDD
TO
CLOCK-PHASE
GENERATION
AVDD
CLKP
AVDD
AVDD
CSAMP
4pF
TO
CHARGE
PIPELINE
INP
E2
E1
600
AVDD
TO
CHARGE
PIPELINE
INN
E2
E1
18k
E3
CSAMP
4pF
AVDD
11k
CLKN
E3
FIGURE 43. ANALOG INPUTS
AVDD
18k
11k
FIGURE 44. CLOCK INPUTS
AVDD
(20k PULL-UP
ON RESETN
ONLY)
AVDD
75k
AVDD
OVDD
TO
SENSE
LOGIC
75k
280
INPUT
OVDD
OVDD
20k
INPUT
75k
TO
LOGIC
280
75k
FIGURE 46. DIGITAL INPUTS
FIGURE 45. TRI-LEVEL DIGITAL INPUTS
OVDD
2mA OR
3mA
OVDD
DATA
DATA
OVDD
OVDD
D[11:0]P
OVDD
DATA
D[11:0]
D[11:0]N
DATA
DATA
2mA OR
3mA
FIGURE 47. LVDS OUTPUTS
32
FIGURE 48. CMOS OUTPUTS
FN7717.2
November 30, 2012
ISLA212P
Equivalent Circuits (Continued)
AVDD
VCM
0.94V
+
–
FIGURE 49. VCM_OUT OUTPUT
A/D Evaluation Platform
LVDS Outputs
Intersil offers an A/D Evaluation platform that can be used to
evaluate any of the Intersil high-speed A/D products. The
platform consists of an FPGA-based data capture motherboard
and a family of A/D daughtercards. This USB-based platform
allows a user to quickly evaluate the A/D performance at
user-specific application frequency requirements. More
information is available at
http://www.intersil.com/converters/adc_eval_platform/
Output traces and connections must be designed for 50Ω (100Ω
differential) characteristic impedance. Keep traces direct, and
minimize bends where possible. Avoid crossing ground and
power-plane breaks with signal traces.
Layout Considerations
Split Ground and Power Planes
Data converters operating at high sampling frequencies require
extra care in PC board layout. Many complex board designs
benefit from isolating the analog and digital sections. Analog
supply and ground planes should be laid out under signal and
clock inputs. Locate the digital planes under outputs and logic
pins. Grounds should be joined under the chip.
Clock Input Considerations
Use matched transmission lines to the transformer inputs for the
analog input and clock signals. Locate transformers and
terminations as close to the chip as possible.
Exposed Paddle
The exposed paddle must be electrically connected to analog
ground (AVSS) and for optimal thermal performance should be
connected to a large copper plane using numerous vias.
Bypass and Filtering
Bulk capacitors should have low equivalent series resistance.
Tantalum is a good choice. For best performance, keep ceramic
bypass capacitors very close to device pins. Longer traces
increase inductance, resulting in diminished dynamic
performance and accuracy. Make sure that connections to
ground are direct and low impedance. Avoid forming ground
loops.
LVCMOS Outputs
Output traces and connections must be designed for 50Ω
characteristic impedance.
Unused Inputs
Standard logic inputs (RESETN, CSB, SCLK, SDIO, SDO) that are
not operated do not require connection to ensure optimal A/D
performance. These inputs can be left floating if they are not
used. Tri-level inputs (NAPSLP) accept a floating input as a valid
state and therefore should be biased according to the desired
functionality.
Definitions
Analog Input Bandwidth is the analog input frequency at which
the spectral output power at the fundamental frequency (as
determined by FFT analysis) is reduced by 3dB from its full-scale
low-frequency value. This is also referred to as Full Power
Bandwidth.
Aperture Delay or Sampling Delay is the time required after the
rise of the clock input for the sampling switch to open, at which
time the signal is held for conversion.
Aperture Jitter is the RMS variation in aperture delay for a set of
samples.
Clock Duty Cycle is the ratio of the time the clock wave is at logic
high to the total time of one clock period.
Differential Non-Linearity (DNL) is the deviation of any code width
from an ideal 1 LSB step.
Effective Number of Bits (ENOB) is an alternate method of
specifying Signal to Noise-and-Distortion Ratio (SINAD). In dB, it
is calculated as: ENOB = (SINAD - 1.76)/6.02
Gain Error is the ratio of the difference between the voltages that
cause the lowest and highest code transitions to the full-scale
voltage less than 2 LSB. It is typically expressed in percent.
33
FN7717.2
November 30, 2012
ISLA212P
I2E The Intersil Interleave Engine. This highly configurable
circuitry performs estimates of offset, gain, and sample time
skew mismatches between the core converters, and updates
analog adjustments for each to minimize interleave spurs.
Integral Non-Linearity (INL) is the maximum deviation of the
A/D’s transfer function from a best fit line determined by a least
squares curve fit of that transfer function, measured in units of
LSBs.
Least Significant Bit (LSB) is the bit that has the smallest value or
weight in a digital word. Its value in terms of input voltage is
VFS/(2N-1) where N is the resolution in bits.
Missing Codes are output codes that are skipped and will never
appear at the A/D output. These codes cannot be reached with
any input value.
Most Significant Bit (MSB) is the bit that has the largest value or
weight.
Pipeline Delay is the number of clock cycles between the
initiation of a conversion and the appearance at the output pins
of the data.
Power Supply Rejection Ratio (PSRR) is the ratio of the observed
magnitude of a spur in the A/D FFT, caused by an AC signal
superimposed on the power supply voltage.
Signal to Noise-and-Distortion (SINAD) is the ratio of the RMS
signal amplitude to the RMS sum of all other spectral
components below one half the clock frequency, including
harmonics but excluding DC.
Signal-to-Noise Ratio (without Harmonics) is the ratio of the RMS
signal amplitude to the RMS sum of all other spectral
components below one-half the sampling frequency, excluding
harmonics and DC.
SNR and SINAD are either given in units of dB when the power of
the fundamental is used as the reference, or dBFS (dB to full
scale) when the converter’s full-scale input power is used as the
reference.
Spurious-Free-Dynamic Range (SFDR) is the ratio of the RMS
signal amplitude to the RMS value of the largest spurious
spectral component. The largest spurious spectral component
may or may not be a harmonic.
34
FN7717.2
November 30, 2012
ISLA212P
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure
you have the latest Rev.
DATE
REVISION
CHANGE
November 21, 2012
FN7717.2
Improved the accuracy and clarity of datasheet.
May 11, 2011
FN7717.1
Initial Release
About Intersil
Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management
semiconductors. The company's products address some of the fastest growing markets within the industrial and infrastructure,
personal computing and high-end consumer markets. For more information about Intersil or to find out how to become a member of
our winning team, visit our website and career page at www.intersil.com.
For a complete listing of Applications, Related Documentation and Related Parts, please see the respective product information page.
Also, please check the product information page to ensure that you have the most updated datasheet: ISLA212P
To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff
Reliability reports are available from our website at: http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
35
FN7717.2
November 30, 2012
ISLA212P
Package Outline Drawing
L72.10x10E
72 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 11/09
A
X
10.00
9.75
72
Z
EXPOSED
PAD AREA
B
6
PIN #1
INDEX AREA
72
1
1
6
PIN 1
INDEX AREA
8.500 REF. (4X)
9.75
3.000
REF.
6.000 REF.
10.00
0.100 M C A B
(4X)
0.15
4.150 REF.
TOP VIEW
7.150 REF.
0.100 M C A B
BOTTOM VIEW
11°
ALL AROUND
9.75 ±0.10
Y
C0.400X45° (4X)
10.00 ±0.10
(0.350)
0.450
R0.200
SIDE VIEW
25
.1
(0
(4X 9.70)
LL
A
A
O
R
D
N
)
1
C0.190X45°
(4.15 REF)
U
(1.500)
(7.15)
0.500 ±0.100
72
R0.115 TYP.
(3.00 )
(4X 8.50)
(6.00)
DETAIL "Z"
R0.200 MAX.
ALL AROUND
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ANSI Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.10
Angular ±2.50°
4.
Dimension applies to the metallized terminal and is measured
between 0.015mm and 0.30mm from the terminal tip.
5.
Tiebar shown (if present) is a non-functional feature.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
7.
Package outline compliant to JESD-M0220.
0.190~0.245
SEATING
PLANE
0.080 C
0.50
0.025 ±0.020
0.23 ±0.050
0.85 ±0.050
0.100 C
( 72X 0 .70)
0.650 ±0.050
( 72X 0 .23)
DETAIL "X"
C
0.100 M C A B
0.050 M C
DETAIL "Y"
either a mold or mark feature.
36
FN7717.2
November 30, 2012
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