DATASHEET

X9522
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COM SUBST 6, ISLData
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X958
®
Laser Diode Control for Fiber Optic Modules
September 7, 2010
Triple DCP, Dual Voltage Monitors
FN8208.2
DESCRIPTION
The X9522 combines three Digitally Controlled
Potentiometers (DCPs), and two programmable
voltage monitor inputs with software and hardware indicators. All functions of the X9522 are
accessed by an industry standard 2-Wire serial
interface.
FEATURES
• Three Digitally Controlled Potentiometers (DCPs)
—64 Tap - 10kΩ
—100 Tap - 10kΩ
—256 Tap - 100kΩ
—Nonvolatile
—Write Protect Function
• 2-Wire industry standard Serial Interface
• Dual Voltage Monitors
—Programmable Threshold Voltages
• Single Supply Operation
—2.7V to 5.5V
• Hot Pluggable
• 20 Pin package
—TSSOP
Two of the DCPs of the X9522 may be utilized to
control the bias and modulation currents of the
laser diode in a Fiber Optic module. The third DCP
may be used to set other various reference quantities, or as a coarse trim for one of the other two
DCPs.The programmable voltage monitors may be
used for monitoring various module alarm levels.
The features of the X9522 are ideally suited to simplifying the design of fiber optic modules. The
integration of these functions into one package
significantly reduces board area, cost and
increases reliability of laser diode modules.
BLOCK DIAGRAM
RH0
WIPER
COUNTER
REGISTER
RW0
RL0
8
WP
6 - BIT
NONVOLATILE
MEMORY
PROTECT LOGIC
RH1
SDA
SCL
WIPER
COUNTER
REGISTER
DATA
REGISTER
RW1
RL1
COMMAND
DECODE &
CONTROL
LOGIC
7 - BIT
NONVOLATILE
MEMORY
CONSTAT
REGISTER
RH2
WIPER
COUNTER
REGISTER
THRESHOLD
RESET LOGIC
RW2
RL2
2
VTRIP3
+
VTRIP 2
+
V3
V2
8 - BIT
NONVOLATILE
MEMORY
V3RO
V2RO
Vcc / V1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
©2000 Intersil Inc., Patents Pending. Copyright Intersil Americas Inc. 2006, 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9522
Ordering Information
PART NUMBER
PART MARKING
PRESET (FACTORY SHIPPED) VTRIPx
THRESHOLD LEVELS (x = 2, 3)
TEMP RANGE (°C)
PACKAGE
X9522V20I-A
X9522VIA
Optimized for 3.3V system monitoring
-40 to +85
20 Ld TSSOP
X9522V20I-B
X9522VIB
Optimized for 5V system monitoring
-40 to +85
20 Ld TSSOP
X9522V20IZ-A (Note)
X9522VZIA
Optimized for 3.3V system monitoring
-40 to +85
20 Ld TSSOP (Pb-free)
X9522V20IZ-B (Note)
X9522VZIB
Optimized for 5V system monitoring
-40 to +85
20 Ld TSSOP (Pb-free)
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2
FN8208.2
September 7, 2010
X9522
PIN CONFIGURATION
20 Pin TSSOP
RH2
RW2
RL2
V3
V3RO
NC
WP
1
2
3
4
5
6
SCL
7
8
SDA
VSS
9
10
Vcc / V1
20
19
18
17
NC
V2RO
V2
RL0
RW0
16
15
14
13
12
11
RH0
RH1
RW1
RL1
NOT TO SCALE
DETAILED DEVICE DESCRIPTION
The X9522 combines three Intersil Digitally Controlled Potentiometer (DCP) devices, and two voltage monitors, in one package. These functions are
suited to the control, support, and monitoring of
various system parameters in fiber optic modules.
The combination of the X9522 functionality lowers
system cost, increases reliability, and reduces
board space requirements.
Two high resolution DCPs allow for the “set-andforget” adjustment of Laser Driver IC parameters
such as Laser Diode Bias and Modulation Currents. One lower resolution DCP may be used for
setting sundry system parameters such as maximum laser output power (for eye safety requirements).
The dual Voltage Monitor circuits continuously
compare their inputs to individual trip voltages. If
an input voltage exceeds it’s associated trip level,
a hardware output (V3RO, V2RO) are allowed to go
HIGH. If the input voltage becomes lower than it’s
associated trip level, the corresponding output is
driven LOW. A corresponding binary representation of the two monitor circuit outputs (V2RO and
V3RO) are also stored in latched, volatile (CONSTAT) register bits. The status of these two monitor outputs can be read out via the 2-wire serial
port.
Intersil’s unique circuits allow for all internal trip
voltages to be individually programmed with high
accuracy. This gives the designer great flexibility
in changing system parameters, either at the time
of manufacture, or in the field.
The device features a 2-Wire interface and software protocol allowing operation on an I2C™ compatible serial bus.
3
FN8208.2
September 7, 2010
X9522
PIN ASSIGNMENT
Pin
Name
Function
1
RH2
Connection to end of resistor array for (the 256 Tap) DCP 2.
2
Rw2
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 2.
3
RL2
Connection to other end of resistor array for (the 256 Tap) DCP 2.
4
V3
V3 Voltage Monitor Input. V3 is the input to a non-inverting voltage comparator circuit. When the V3
input is higher than the VTRIP3 threshold voltage, V3RO makes a transition to a HIGH level. Connect
V3 to VSS when not used.
5
V3RO
V3 RESET Output. This open drain output makes a transition to a HIGH level when V3 is greater than
VTRIP3 and goes LOW when V3 is less than VTRIP3. There is no delay circuitry on this pin. The V3RO
pin requires the use of an external “pull-up” resistor.
7
WP
Write Protect Control Pin. WP pin is a TTL level compatible input. When held HIGH, Write Protection is
enabled. In the enabled state, this pin prevents all nonvolatile “write” operations. Also, when the Write
Protection is enabled, and the DCP Write Lock feature is active (i.e. the DCP Write Lock bit is set to
“1”), then no “write” (volatile or nonvolatile) operations can be performed in the device (including the
wiper position of any of the integrated Digitally Controlled Potentiometers (DCPs). The WP pin uses an
internal “pull-down” resistor, thus if left floating the write protection feature is disabled.
8
SCL
Serial Clock. This is a TTL level compatible input pin used to control the serial bus timing for data input
and output.
9
SDA
Serial Data. SDA is a bidirectional TTL level compatible pin used to transfer data into and out of the
device. The SDA pin input buffer is always active (not gated). This pin requires an external pull up resistor.
10
Vss
Ground.
11
RL1
Connection to other end of resistor for (the 100 Tap) DCP 1.
12
Rw1
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 1.
13
RH1
Connection to end of resistor array for (the 100 Tap) DCP 1.
14
RH0
Connection to end of resistor array for (the 64 Tap) Digitally Controlled Potentiometer (DCP) 0.
15
RW0
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 0.
16
RL0
Connection to the other end of resistor array for (the 64 Tap) DCP 0.
17
V2
V2 Voltage Monitor Input. V2 is the input to a non-inverting voltage comparator circuit. When the V2
input is greater than the VTRIP2 threshold voltage, V2RO makes a transition to a HIGH level. Connect
V2 to VSS when not used.
18
V2RO
V2 RESET Output. This open drain output makes a transition to a HIGH level when V2 is greater than
VTRIP2, and goes LOW when V2 is less than VTRIP2. There is no power-up reset delay circuitry on this
pin. The V2RO pin requires the use of an external “pull-up” resistor.
20
Vcc / V1
6, 19
NC
Supply Voltage.
No Connect.
4
FN8208.2
September 7, 2010
X9522
SCL
SDA
Data Stable
Figure 1.
Data Change
Data Stable
Valid Data Changes on the SDA Bus
Serial Stop Condition
PRINCIPLES OF OPERATION
SERIAL INTERFACE
Serial Interface Conventions
The device supports a bidirectional bus oriented
protocol. The protocol defines any device that
sends data onto the bus as a transmitter, and the
receiving device as the receiver. The device controlling the transfer is called the master and the
device being controlled is called the slave. The
master always initiates data transfers, and provides the clock for both transmit and receive operations. Therefore, the X9522 operates as a slave in
all applications.
Serial Clock and Data
Data states on the SDA line can change only while
SCL is LOW. SDA state changes while SCL is
HIGH are reserved for indicating START and STOP
conditions. See Figure 1. On power-up of the
X9522, the SDA pin is in the input mode.
Serial Start Condition
All commands are preceded by the START condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH. The device continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until
this condition has been met. See Figure 2.
All communications must be terminated by a STOP
condition, which is a LOW to HIGH transition of
SDA while SCL is HIGH. The STOP condition is also
used to place the device into the Standby power
mode after a read sequence. A STOP condition can
only be issued after the transmitting device has
released the bus. See Figure 2.
Serial Acknowledge
An ACKNOWLEDGE (ACK) is a software convention used to indicate a successful data transfer. The
transmitting device, either master or slave, will
release the bus after transmitting eight bits. During
the ninth clock cycle, the receiver will pull the SDA
line LOW to ACKNOWLEDGE that it received the
eight bits of data. Refer to Figure 3.
The device will respond with an ACKNOWLEDGE
after recognition of a START condition if the correct Device Identifier bits are contained in the
Slave Address Byte. If a write operation is
selected, the device will respond with an
ACKNOWLEDGE after the receipt of each subsequent eight bit word.
In the read mode, the device will transmit eight
bits of data, release the SDA line, then monitor the
line for an ACKNOWLEDGE. If an ACKNOWLEDGE
is detected and no STOP condition is generated by
the master, the device will continue to transmit
data. The device will terminate further data transmissions if an ACKNOWLEDGE is not detected.
The master must then issue a STOP condition to
place the device into a known state.
SCL
SDA
Start
Figure 2.
5
Stop
Valid Start and Stop Conditions
FN8208.2
September 7, 2010
X9522
DEVICE INTERNAL ADDRESSING
SCL
from
Master
Data Output
from
Transmitter
Data Output
from
Receiver
1
8
9
Start
Figure 3.
Acknowledge
Acknowledge Response From Receiver
Addressing Protocol Overview
The user addressable internal components of the
X9522 can be split up into two main parts:
—Three Digitally Controlled Potentiometers (DCPs)
—Control and Status (CONSTAT) Register
Depending upon the operation to be performed
on each of these individual parts, a 1, 2 or 3 Byte
protocol is used. All operations however must
begin with the Slave Address Byte being issued
on the SDA pin. The Slave address selects the
part of the X9522 to be addressed, and specifies
if a Read or Write operation is to be performed.
It should be noted that in order to perform a write
operation to a DCP, the Write Enable Latch (WEL)
bit must first be set.
Slave Address Byte
Following a START condition, the master must
output a Slave Address Byte (Refer to Figure 4.).
This byte consists of three parts:
—The Device Type Identifier which consists of the most
significant four bits of the Slave Address (SA7 - SA4).
The Device Type Identifier must always be set to 1010
in order to select the X9522.
—The next three bits (SA3 - SA1) are the Internal Device
Address bits. Setting these bits to 111 internally selects
the DCP structures in the X9522. The CONSTAT Register may be selected using the Internal Device
Address 010.All other bit combinations are
RESERVED.
—The Least Significant Bit of the Slave Address (SA0)
Byte is the R/W bit. This bit defines the operation to be
performed on the device being addressed (as defined
in the bits SA3 - SA1). When the R/W bit is “1”, then a
READ operation is selected. A “0” selects a WRITE
operation (Refer to Figure 4.)
SA7
SA6 SA5
1 0 1
SA3
SA2
SA1
SA0
0
DEVICE TYPE
IDENTIFIER
R/W
READ /
WRITE
INTERNAL
DEVICE
ADDRESS
Internal Address
(SA3 - SA1)
Internally Addressed
Device
010
CONSTAT Register
111
DCP
Others
RESERVED
Bit SA0
Operation
0
WRITE
1
READ
Figure 4.
6
SA4
Slave Address Format
FN8208.2
September 7, 2010
X9522
Nonvolatile Write Acknowledge Polling
After a nonvolatile write command sequence (for
either the Non Volatile Memory of a DCP (NVM), or
the CONSTAT Register) has been correctly issued
(including the final STOP condition), the X9522 initiates an internal high voltage write cycle. This
cycle typically requires 5 ms. During this time, no
further Read or Write commands can be issued to
the device. Write Acknowledge Polling is used to
determine when this high voltage write cycle has
been completed.
To perform acknowledge polling, the master
issues a START condition followed by a Slave
Address Byte. The Slave Address issued must
contain a valid Internal Device Address. The LSB
of the Slave Address (R/W) can be set to either 1 or
0 in this case. If the device is still busy with the
high voltage cycle then no ACKNOWLEDGE will
be returned. If the device has completed the write
operation, an ACKNOWLEDGE will be returned
and the host can then proceed with a read or write
operation. (Refer to Figure 5.)
WIPER
COUNTER
REGISTER
(WCR)
DECODER
“WIPER”
FET
SWITCHES
RESISTOR
ARRAY
2
NON
VOLATILE
MEMORY
(NVM)
1
0
RLx
RWx
Figure 6.
DCP Internal Structure
DIGITALLY CONTROLLED POTENTIOMETERS
DCP Functionality
Byte load completed
by issuing STOP.
Enter ACK Polling
Issue START
Issue Slave Address
Byte (Read or Write)
Issue STOP
YES
High Voltage Cycle
NO
Issue STOP
complete. Continue
The X9522 includes three independent resistor
arrays. These arrays respectively contain 63, 99
and 255 discrete resistive segments that are
connected in series. The physical ends of each
array are equivalent to the fixed terminals of a
mechanical potentiometer (RHx and RLx inputs where x = 0,1,2).
At both ends of each array and between each
resistor segment there is a CMOS switch connected to the wiper (Rwx) output. Within each individual array, only one switch may be turned on at
any one time. These switches are controlled by the
Wiper Counter Register (WCR) (See Figure 6). The
WCR is a volatile register.
NO
ACK
returned?
command sequence?
YES
Continue normal
Read or Write
command sequence
PROCEED
Figure 5.
RHx
N
On power-up of the X9522, wiper position data is
automatically loaded into the WCR from its associated Non Volatile Memory (NVM) Register. The
Table below shows the Initial Values of the DCP
WCR’s before the contents of the NVM is loaded
into the WCR.
DCP
Initial Values Before Recall
R0 / 64 TAP
VH / TAP = 63
R1 / 100 TAP
VL / TAP = 0
R2 / 256 TAP
VH / TAP = 255
Acknowledge Polling Sequence
7
FN8208.2
September 7, 2010
X9522
Vcc
Vcc (Max.)
VTRIP
ttrans
tpu
t
0
Maximum Wiper Recall time
Figure 7.
DCP Power-up
The data in the WCR is then decoded to select and
enable one of the respective FET switches. A
“make before break” sequence is used internally
for the FET switches when the wiper is moved
from one tap position to another.
Hot Pluggability
Figure 7 shows a typical waveform that the X9522
might experience in a Hot Pluggable situation. On
power-up, Vcc / V1 applied to the X9522 may
exhibit some amount of ringing, before it settles to
the required value.
The device is designed such that the wiper terminal (RWx) is recalled to the correct position (as per
the last stored in the DCP NVM), when the voltage
applied to Vcc / V1 exceeds VTRIP for a time
exceeding tpu.
“wiper position” setting is recalled into the WCR
after Vcc / V1 of the X9522 is powered down and
then powered back up.
A volatile write operation to a DCP however,
changes the “wiper position” by writing new data
to the associated WCR only. The contents of the
associated NVM register remains unchanged.
Therefore, when Vcc / V1 to the device is powered
down then back up, the “wiper position” reverts to
that last position written to the DCP using a
nonvolatile write operation.
Both volatile and nonvolatile write operations are
executed using a three byte command sequence:
(DCP) Slave Address Byte, Instruction Byte,
followed by a Data Byte (See Figure 9).
Therefore, if ttrans is defined as the time taken for
Vcc / V1 to settle above VTRIP (Figure 7): then the
desired wiper terminal position is recalled by (a
maximum) time: ttrans + tpu. It should be noted
that ttrans is determined by system hot plug conditions.
A DCP Read operation allows the user to “read
out” the current “wiper position” of the DCP, as
stored in the associated WCR. This operation is
executed using the Random Address Read
command sequence, consisting of the (DCP) Slave
Address Byte followed by an Instruction Byte and
the Slave Address Byte again (Refer to Figure 10.).
DCP Operations
Instruction Byte
In total there are three operations that can be
performed on any internal DCP structure:
—DCP Nonvolatile Write
—DCP Volatile Write
—DCP Read
A nonvolatile write to a DCP will change the “wiper
position” by simultaneously writing new data to
the associated WCR and NVM. Therefore, the new
8
While the Slave Address Byte is used to select the
DCP devices, an Instruction Byte is used to determine which DCP is being addressed.
The Instruction Byte (Figure 8) is valid only when
the Device Type Identifier and the Internal Device
Address bits of the Slave Address are set to
1010111. In this case, the two Least Significant
Bit’s (I1 - I0) of the Instruction Byte are used to
select the particular DCP (0 - 2). In the case of a
Write to any of the DCPs (i.e. the LSB of the Slave
FN8208.2
September 7, 2010
X9522
the new “wiper position” setting is recalled into
the WCR after Vcc / V1 of the X9522 has been powered down then powered back up.
Address is 0), the Most Significant Bit of the
Instruction Byte (I7), determines the Write Type
(WT) performed.
I7
WT
I6
I5
I4
I3
I2
0
0
0
0
0
I1
P1
WRITE TYPE
If WT is “0” then a DCP Volatile Write is performed.
This operation changes the DCP “wiper position”
by writing new data to the associated WCR only.
The contents of the associated NVM register
remains unchanged. Therefore, when Vcc / V1 to
the device is powered down then back up, the
“wiper position” reverts to that last written to the
DCP using a nonvolatile write operation.
I0
P0
DCP SELECT
WT†
Description
0
Select a Volatile Write operation to be performed
on the DCP pointed to by bits P1 and P0
1
Select a Nonvolatile Write operation to be performed on the DCP pointed to by bits P1 and P0
DCP Write Operation
A write to DCPx (x=0,1,2) can be performed using
the three byte command sequence shown in Figure 9.
†This bit has no effect when a Read operation is being performed.
Figure 8.
In order to perform a write operation on a particular DCP, the Write Enable Latch (WEL) bit of the
CONSTAT Register must first be set (See “WEL:
Write Enable Latch (Volatile)” on page 11.)
Instruction Byte Format
If WT is “1”, then a Nonvolatile Write to the DCP
occurs. In this case, the “wiper position” of the
DCP is changed by simultaneously writing new
data to the associated WCR and NVM. Therefore,
S 1
T
A
R
T
0
1
0
1
1
1
0
A WT
C
K
SLAVE ADDRESS BYTE
Figure 9.
9
0
0
0
The Slave Address Byte 10101110 specifies that a
Write to a DCP is to be conducted. An ACKNOWLEDGE is returned by the X9522 after the Slave
Address, if it has been received correctly.
0
0
P1 P0
A
C
K
D7 D6 D5 D4 D3 D2 D1 D0
INSTRUCTION BYTE
DATA BYTE
A
C
K
S
T
O
P
DCP Write Command Sequence
FN8208.2
September 7, 2010
X9522
Next, an Instruction Byte is issued on SDA. Bits P1
and P0 of the Instruction Byte determine which
WCR is to be written, while the WT bit determines
if the Write is to be volatile or nonvolatile. If the
Instruction Byte format is valid, another
ACKNOWLEDGE is then returned by the X9522.
Following the Instruction Byte, a Data Byte is
issued to the X9522 over SDA. The Data Byte contents is latched into the WCR of the DCP on the
first rising edge of the clock signal, after the LSB
of the Data Byte (D0) has been issued on SDA (See
Figure 25).
The Data Byte determines the “wiper position”
(which FET switch of the DCP resistive array is
switched ON) of the DCP. The maximum value for
the Data Byte depends upon which DCP is being
addressed (see Table below).
P1- P0
DCPx
# Taps
Max. Data Byte
0
0
x=0
64
3Fh
0
1
x=1
100
Refer to Appendix 1
1
0
x=2
256
FFh
1
1
Reserved
Using a Data Byte larger than the values specified
above results in the “wiper terminal” being set to
the highest tap position. The “wiper position”
does NOT roll-over to the lowest tap position.
For DCP0 (64 Tap) and DCP2 (256 Tap), the Data
Byte maps one to one to the “wiper position” of
the DCP “wiper terminal”. Therefore, the Data Byte
00001111 (1510) corresponds to setting the “wiper
terminal” to tap position 15. Similarly, the Data
Byte 00011100 (2810) corresponds to setting the
“wiper terminal” to tap position 28. The mapping
of the Data Byte to “wiper position” data for DCP1
(100 Tap), is shown in “APPENDIX 1”. An example
of a simple C language function which “translates” between the tap position (decimal) and the
Data Byte (binary) for DCP1, is given in “APPENDIX 2” .
10
It should be noted that all writes to any DCP of the
X9522 are random in nature. Therefore, the Data
Byte of consecutive write operations to any DCP
can differ by an arbitrary number of bits. Also, setting the bits P1=1, P0=1 is a reserved sequence,
and will result in no ACKNOWLEDGE after sending an Instruction Byte on SDA.
The factory default setting of all “wiper position”
settings is with 00h stored in the NVM of the DCPs.
This corresponds to having the “wiper teminal”
RWX (x = 0,1,2) at the “lowest” tap position, Therefore, the resistance between RWX and RLX is a minimum (essentially only the Wiper Resistance, RW).
DCP Read Operation
A read of DCPx (x = 0,1,2) can be performed using
the three byte random read command sequence
shown in Figure 10.
The master issues the START condition and the
Slave Address Byte 10101110 which specifies that
a “dummy” write” is to be conducted. This
“dummy” write operation sets which DCP is to be
read (in the preceding Read operation). An
ACKNOWLEDGE is returned by the X9522 after the
Slave Address if received correctly. Next, an
Instruction Byte is issued on SDA. Bits P1-P0 of
the Instruction Byte determine which DCP “wiper
position” is to be read. In this case, the state of the
WT bit is “don’t care”. If the Instruction Byte format is valid, then another ACKNOWLEDGE is
returned by the X9522.
FN8208.2
September 7, 2010
X9522
Signals from
the Master
SDA Bus
WRITE Operation
S
t
a
r
t
Slave
Address
Instruction
Byte
10101110
W 00000 P P
1 0
T
A
C
K
Signals from
the Slave
S
t
a
r
t
READ Operation
Slave
Address
S
t
o
p
Data Byte
10101111
A
C
K
A
C
K
DCPx
“Dummy” write
- -
x=0
-
x=1
x=2
LSB
MSB
“-” = DON’T CARE
Figure 10.
DCP Read Sequence
Following this ACKNOWLEDGE, the master immediately issues another START condition and a
valid Slave address byte with the R/W bit set to 1.
Then the X9522 issues an ACKNOWLEDGE followed by Data Byte, and finally, the master issues
a STOP condition. The Data Byte read in this operation, corresponds to the “wiper position” (value
of the WCR) of the DCP pointed to by bits P1 and
P0.
It should be noted that when reading out the data
byte for DCP0 (64 Tap), the upper two most significant bits are “unknown” bits. For DCP1 (100 Tap),
the upper most significant bit is an “unknown”. For
DCP2 (256 Tap) however, all bits of the data byte
are relevant (See Figure 10).
CONTROL AND STATUS REGISTER
The Control and Status (CONSTAT) Register provides the user with a mechanism for changing
and reading the status of various parameters of
the X9522 (See Figure 11).
The CONSTAT register is a combination of both
volatile and nonvolatile bits. The nonvolatile bits
of the CONSTAT register retain their stored values
even when Vcc / V1 is powered down, then powered back up. The volatile bits however, will
always power-up to a known logic state “0” (irrespective of their value at power-down).
11
CS7
0
CS6
CS5
CS4
CS3
V2OS
V3OS
0
DWLK
CS2
CS1
CS0
RWEL
WEL
0
NV
Bit(s)
Description
CS7
Always set to “0” (RESERVED)
V2OS
V2 Output Status flag
V3OS
V3 Output Status flag
CS4
Always set to “0” (RESERVED)
DWLK
Sets the DCP Write Lock
RWEL
Register Write Enable Latch bit
WEL
Write Enable Latch bit
CS0
Always set to “0” (RESERVED)
NOTE: Bits belled NV are nonvolatile (See “CONTROL AND STATUS REGISTER”).
Figure 11. CONSTAT Register Format
A detailed description of the function of each of
the CONSTAT register bits follows:
WEL: Write Enable Latch (Volatile)
The WEL bit controls the Write Enable status of
the entire X9522 device. This bit must first be
enabled before ANY write operation (to DCPs, or
the CONSTAT register). If the WEL bit is not first
enabled, then ANY proceeding (volatile or nonvolatile) write operation to DCPs, or the CONSTAT
register, is aborted and no ACKNOWLEDGE is
issued after a Data Byte.
FN8208.2
September 7, 2010
X9522
SCL
SDA
S
T
A
R
T
1
0
1
0
0
1
0
R/W A
C
K
1
1
SLAVE ADDRESS BYTE
1
1
1
1
1
1
ADDRESS BYTE
A
C
K
CS7 CS6 CS5 CS4 CS3 CS2 CS1 CS0
CONSTAT REGISTER DATA IN
A
C
K
S
T
O
P
Figure 12. CONSTAT Register Write Command Sequence
The WEL bit is a volatile latch that powers up in
the disabled, LOW (0) state. The WEL bit is
enabled / set by writing 00000010 to the CONSTAT
register. Once enabled, the WEL bit remains set to
“1” until either it is reset to “0” (by writing
00000000 to the CONSTAT register) or until the
X9522 powers down, and then up again.
Writes to the WEL bit do not cause an internal high
voltage write cycle. Therefore, the device is ready
for another operation immediately after a STOP
condition is executed in the CONSTAT Write command sequence (See Figure 12).
RWEL: Register Write Enable Latch (Volatile)
The RWEL bit controls the (CONSTAT) Register
Write Enable status of the X9522. Therefore, in
order to write to any of the bits of the CONSTAT
Register (except WEL), the RWEL bit must first be
set to “1”. The RWEL bit is a volatile bit that powers up in the disabled, LOW (“0”) state.
It must be noted that the RWEL bit can only be set,
once the WEL bit has first been enabled (See
"CONSTAT Register Write Operation").
The RWEL bit will reset itself to the default “0”
state, in one of two cases:
—After a successful write operation to any bits of
the CONSTAT register has been completed (See
Figure 12).
—When the X9522 is powered down.
DWLK: DCP Write Lock bit - (Nonvolatile)
The DCP Write Lock bit (DWLK) is used to inhibit a
DCP write operation (changing the “wiper position”).
12
When the DCP Write Lock bit of the CONSTAT register is set to “1”, then the “wiper position” of the
DCPs cannot be changed - i.e. DCP write operations cannot be conducted:
DWLK
DCP Write Operation Permissible
0
YES (Default)
1
NO
The factory default setting for this bit is DWLK = 0.
IMPORTANT NOTE: If the Write Protect (WP) pin of
the X9522 is active (HIGH), then nonvolatile write
operations to the DCPs are inhibited, irrespective
of the DCP Write Lock bit setting (See "WP: Write
Protection Pin").
V2OS, V3OS: Voltage Monitor Status Bits (Volatile)
Bits V2OS and V3OS of the CONSTAT register are
latched, volatile flag bits which indicate the status
of the Voltage Monitor reset output pins V2RO and
V3RO.
At power-up the VxOS (x=2,3) bits default to the
value “0”. These bits can be set to a “1” by writing
the appropriate value to the CONSTAT register. To
provide consistency between the VxRO and VxOS
however, the status of the VxOS bits can only be
set to a “1” when the corresponding VxRO output
is HIGH.
Once the VxOS bits have been set to “1”, they will
be reset to “0” if:
—The device is powered down, then back up,
—The corresponding VxRO output becomes LOW.
FN8208.2
September 7, 2010
X9522
CONSTAT Register Write Operation
and ended with a STOP bit. Since this is a nonvolatile
write cycle, it will typically take 5ms to complete. The
RWEL bit is reset by this cycle and the sequence must
be repeated to change the nonvolatile bits again. If bit
2 is set to ‘1’ in this third step (0xy0 t110) then the
RWEL bit is set, but the DWLK bit will remain
unchanged. Writing a second byte to the control register is not allowed. Doing so aborts the write operation
and the X9522 does not return an ACKNOWLEDGE.
The CONSTAT register is accessed using the
Slave Address set to 1010010 (Refer to Figure 4.).
Following the Slave Address Byte, access to the
CONSTAT register requires an Address Byte
which must be set to FFh. Only one data byte is
allowed to be written for each CONSTAT register
Write operation. The user must issue a STOP, after
sending this byte to the register, to initiate the
nonvolatile cycle that stores the DWLK bit. The
X9522 will not ACKNOWLEDGE any data bytes
written after the first byte is entered (Refer to Figure 12.).
For example, a sequence of writes to the device
CONSTAT register consisting of [02H, 06H, 02H]
will reset the nonvolatile (DWLK) bit in the CONSTAT Register to “0”.
When writing to the CONSTAT register, the bits
CS7, CS4 and CS0 must all be set to “0”. Writing
any other bit sequence to bits CS7, CS4 and CS0
of the CONSTAT register is reserved.
It should be noted that a write to nonvolatile bit
(DWLK) of CONSTAT register will be ignored if the
Write Protect pin of the X9522 is active (HIGH) (See
"WP: Write Protection Pin").
Prior to writing to the CONSTAT register, the WEL
and RWEL bits must be set using a two step process, with the whole sequence requiring 3 steps:
CONSTAT Register Read Operation
The contents of the CONSTAT Register can be
read at any time by performing a random read (See
Figure 13). Using the Slave Address Byte set to
10100101, and an Address Byte of FFh. Only one
byte is read by each register read operation. The
X9522 resets itself after the first byte is read. The
master should supply a STOP condition to be consistent with the bus protocol.
—Write a 02H to the CONSTAT Register to set the Write
Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation preceded
by a START and ended with a STOP).
—Write a 06H to the CONSTAT Register to set the
Register Write Enable Latch (RWEL) AND the WEL
bit. This is also a volatile cycle. The zeros in the data
byte are required. (Operation preceded by a START
and ended with a STOP).
After setting the WEL and / or the RWEL bit(s) to a
“1”, a CONSTAT register read operation may occur,
without interrupting a proceeding CONSTAT register write operation.
—Write a one byte value to the CONSTAT Register that
has all the bits set to the desired state. The CONSTAT
register can be represented as 0xy0t010 in binary,
where xy are the Voltage Monitor Output Status
(V2OS and V3OS) bits, and t is the DCP Write Lock
(DWLK) bit. This operation is proceeded by a START
Signals from
the Master
S
t
a
r
t
SDA Bus
When reading the contents of the CONSTAT register, the bits CS7, CS4 and CS0 will always return
“0”.
WRITE Operation
Slave
Address
S
t
Slave
a
r Address
t
Address
Byte
CS7 … CS0
S
t
o
p
10 1 0 0 1 01
10 1 0 0 1 0 0
A
C
K
Signals from
the Slave
READ Operation
A
C
K
A
C
K
Data
“Dummy” Write
Figure 13. CONSTAT Register Read Command Sequence
13
FN8208.2
September 7, 2010
X9522
DATA PROTECTION
There are a number of levels of data protection
features designed into the X9522. Any write to the
device first requires setting of the WEL bit in the
CONSTAT register. A write to the CONSTAT register itself, further requires the setting of the RWEL
bit. The DCP Write Lock of the device enables the
user to inhibit writes to all DCPs. One further level
of data protection in the X9522, is incorporated in
the form of the Write Protection pin.
VTRIPx
Vx
0V
VxRO
0V
Vcc / V1
VTRIP
0 Volts
WP: Write Protection Pin
When the Write Protection (WP) pin is active
(HIGH), it disables nonvolatile write operations to
the X9522.
The table below (X9522 Write Permission Status)
summarizes the effect of the WP pin (and DCP
Write Lock), on the write permission status of the
device.
Additional Data Protection Features
In addition to the preceding features, the X9522
also incorporates the following data protection
functionality:
—The proper clock count and data bit sequence is
required prior to the STOP bit in order to start a nonvolatile write cycle.
(x = 2,3)
Figure 14. Voltage Monitor Response
VOLTAGE MONITORING FUNCTIONS
V2 monitoring
The X9522 asserts the V2RO output HIGH if the
voltage V2 exceeds the corresponding VTRIP2
threshold (See Figure 14). The bit V2OS in the
CONSTAT register is then set to a “0” (assuming
that it has been set to “1” after system initilization).
The V2RO output may remain active HIGH with Vcc
down to 1V.
X9522 Write Permission Status
Write to CONSTAT Register
Permitted
DWLK
(DCP Write Lock
bit status)
WP
(Write Protect pin
status)
DCP Volatile Write
Permitted
DCP Nonvolatile
Write Permitted
Volatile Bits
Nonvolatile Bits
1
1
NO
NO
NO
NO
0
1
YES
NO
NO
NO
1
0
NO
NO
YES
YES
0
0
YES
YES
YES
YES
14
FN8208.2
September 7, 2010
X9522
VTRIPx
V2, V3
VP
WP
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
SCL
00h
SDA
S
T
A
R
T
A0h †
†
09h sets VTRIP1
†
0Dh sets VTRIP2
Data Byte †
† All others Reserved.
Figure 15. Setting VTRIPx to a higher level (x = 1,2).
V3 monitoring
The X9522 asserts the V3RO output HIGH if the
voltage V3 exceeds the corresponding VTRIP3
threshold (See Figure 14). The bit V3OS in the
CONSTAT register is then set to a “0” (assuming
that it has been set to “1” after system initilization).
The V3RO output may remain active HIGH with Vcc
down to 1V.
VTRIPX THRESHOLDS (X = 2,3)
The X9522 is shipped with pre-programmed
threshold (VTRIPx) voltages. In applications where
the required thresholds are different from the
default values, or if a higher precision / tolerance
is required, the X9522 trip points may be adjusted
by the user, using the steps detailed below.
Setting a VTRIPx Voltage (x = 2,3)
There are two procedures used to set the threshold voltages (VTRIPx), depending if the threshold
voltage to be stored is higher or lower than the
present value. For example, if the present VTRIPx
is 2.9 V and the new VTRIPx is 3.2 V, the new voltage can be stored directly into the VTRIPx cell. If
however, the new setting is to be lower than the
present setting, then it is necessary to “reset” the
VTRIPx voltage before setting the new value.
VP
WP
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
SCL
00h †
SDA
S
T
A
R
T
A0h†
†
†
0Fh Resets VTRIP3
0Bh Resets VTRIP2
Data Byte
Figure 16. Resetting the VTRIPx Level (x = 2,3)
15
† All others Reserved.
FN8208.2
September 7, 2010
X9522
Setting a Higher VTRIPx Voltage (x = 2,3)
To set a VTRIPx threshold to a new voltage which
is higher than the present threshold, the user must
apply the desired VTRIPx threshold voltage to the
corresponding input pin (V2 or V3). Then, a programming voltage (Vp) must be applied to the WP
pin before a START condition is set up on SDA.
Next, issue on the SDA pin the Slave Address A0h,
followed by the Byte Address 09h for VTRIP3, and
0Dh for VTRIP3, and a 00h Data Byte in order to
program VTRIPx. The STOP bit following a valid
write operation initiates the programming
sequence. Pin WP must then be brought LOW to
complete the operation (See Figure 16). The user
does not have to set the WEL bit in the CONSTAT
register before performing this write sequence.
Setting a Lower VTRIPx Voltage (x = 2,3)
In order to set VTRIPx to a lower voltage than the
present value, then VTRIPx must first be “reset”
according to the procedure described below. Once
VTRIPx has been “reset”, then VTRIPx can be set to
the desired voltage using the procedure described
in “Setting a Higher VTRIPx Voltage”.
Resetting the VTRIPx Voltage
To reset a VTRIPx voltage, apply the programming
voltage (Vp) to the WP pin before a START condition is set up on SDA. Next, issue on the SDA pin
the Slave Address A0h followed by the Byte
Address 0Bh for VTRIP2, and 0Fh for VTRIP3, followed by 00h for the Data Byte in order to reset
VTRIPx. The STOP bit following a valid write operation initiates the programming sequence. Pin WP
must then be brought LOW to complete the operation (See Figure 16).The user does not have to set
the WEL bit in the CONSTAT register before performing this write sequence.
After being reset, the value of VTRIPx becomes a
nominal value of 1.7V.
VTRIPx Accuracy (x = 2,3)
The accuracy with which the VTRIPx thresholds are
set, can be controlled using the iterative process
shown in Figure 17.
If the desired threshold is less that the present
threshold voltage, then it must first be “reset” (See
"Resetting the VTRIPx Voltage").
The desired threshold voltage is then applied to
the appropriate input pin (V2 or V3) and the procedure described in Section “Setting a Higher VTRIPx
Voltage“ must be followed.
16
Once the desired VTRIPx threshold has been set,
the error between the desired and (new) actual set
threshold can be determined. This is achieved by
applying Vcc / V1 to the device, and then applying
a test voltage higher than the desired threshold
voltage, to the input pin of the voltage monitor circuit whose VTRIPx was programmed. For example,
if VTRIP2 was set to a desired level of 3.0 V, then a
test voltage of 3.4 V may be applied to the voltage
monitor input pin V2. In all cases, care should be
taken not to exceed the maximum input voltage
limits.
After applying the test voltage to the voltage monitor input pin, the test voltage can be decreased
(either in discrete steps, or continuously) until the
output of the voltage monitor circuit changes
state. At this point, the error between the actual /
measured, and desired threshold levels is calculated.
For example, the desired threshold for VTRIP2 is
set to 3.0 V, and a test voltage of 3.4 V was applied
to the input pin V2 (after applying power to Vcc /
V1). The input voltage is decreased, and found to
trip the associated output level of pin V2RO from a
LOW to a HIGH, when V2 reaches 3.09 V. From
this, it can be calculated that the programming
error is 3.09 - 3.0 = 0.09 V.
If the error between the desired and measured
VTRIPx is less than the maximum desired error,
then the programming process may be terminated.
If however, the error is greater than the maximum
desired error, then another iteration of the VTRIPx
programming sequence can be performed (using
the calculated error) in order to further increase
the accuracy of the threshold voltage.
If the calculated error is greater than zero, then the
VTRIPx must first be “reset”, and then programmed to the a value equal to the previously set
VTRIPx minus the calculated error. If it is the case
that the error is less than zero, then the VTRIPx
must be programmed to a value equal to the previously set VTRIPx plus the absolute value of the calculated error.
Continuing the previous example, we see that the
calculated error was 0.09V. Since this is greater
than zero, we must first “reset” the VTRIP2 threshold, then apply a voltage equal to the last previously programmed voltage, minus the last
previously calculated error. Therefore, we must
apply VTRIP1 = 2.91 V to pin V2 and execute the
programming sequence (See "Setting a Higher
VTRIPx Voltage (x = 2,3)" ) .
FN8208.2
September 7, 2010
X9522
Note: X = 1,2,3.
VTRIPx Programming
NO
Let: MDE = Maximum Desired Error
MDE+
Desired VTRIPx <
present value?
Desired Value
MDE–
YES
Execute
VTRIPx Reset
Sequence
Acceptable
Error Range
Error = Actual – Desired
Set Vx = desired VTRIPx
Execute
Set Higher VTRIPx
Sequence
New Vx applied =
Old Vx applied + | Error |
New Vx applied =
Old Vx applied - | Error |
Execute
Reset VTRIPx
Sequence
Apply Vcc & Voltage
> Desired VTRIPx to Vx
Decrease Vx
NO
Output
switches?
YES
Error < MDE–
Actual VTRIPx
- Desired VTRIPx
Error >MDE+
= Error
| Error | < | MDE |
DONE
Figure 17. VTRIPx Setting / Reset Sequence (x = 1,2,3)
Using this process, the desired accuracy for a particular VTRIPx threshold may be attained using a successive number of iterations.
17
FN8208.2
September 7, 2010
X9522
ABSOLUTE MAXIMUM RATINGS
Parameter
Temperature under Bias
Storage Temperature
Voltage on WP pin (With respect to Vss)
Voltage on other pins (With respect to Vss)
| Voltage on RHx - Voltage on RLx | (x = 0,1,2. Referenced to Vss)
D.C. Output Current (SDA,V2RO,V3RO)
Lead Temperature (Soldering, 10 seconds)
Supply Voltage Limits (Applied Vcc / V1 voltage, referenced to Vss)
Min.
Max.
Units
-65
-65
-1.0
-1.0
+135
+150
+15
+7
Vcc / V1
5
300
5.5
°C
°C
V
V
V
mA
°C
V
0
2.7
RECOMMENDED OPERATING CONDITIONS
Temperature
Industrial
Min.
Max.
Units
-40
+85
°C
NOTE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and the functional operation of the device at these or any other conditions
above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability
Figure 18. Equivalent A.C. Circuit
Vcc / V1 = 5V
2300Ω
SDA
V2RO
V3RO
100pF
Figure 19. DCP SPICE Macromodel
RTOTAL
RHx
CH
CL
RW
RLx
10pF
CW
10pF
25pF
(x = 0,1,2)
RWx
18
FN8208.2
September 7, 2010
X9522
TIMING DIAGRAMS
Figure 20. Bus Timing
tHIGH
tF
SCL
tLOW
tR
tSU:DAT
tSU:SA
SDA IN
tHD:DAT
tHD:STA
tSU:STO
tA
tDH
tBUF
SDA OUT
Figure 21. WP Pin Timing
START
SCL
Clk 1
Clk 9
SDA IN
tSU:WP
WP
tHD:WP
Figure 22. Write Cycle Timing
SCL
SDA
8th bit of last byte
ACK
tWC
Stop
Condition
19
Start
Condition
FN8208.2
September 7, 2010
X9522
Figure 23. V2, V3 Timing Diagram
t
tFx
Rx
Vx
V TRIPx
tRPDx
tRPDx
tRPDx
tRPDx
0 Volts
VxRO
0 Volts
Vcc / V1
V
V TRIP
RVALID
0 Volts
Note : x = 2,3.
Figure 24. VTRIPX Programming Timing Diagram (x = 2,3)
V2, V3
VTRIPx
tTSU
tTHD
VP
WP
tVPS
tVPO
SCL
twc
00h
SDA
NOTE : Vcc / V1 must be greater than V2, V3 when programming.
20
tVPH
FN8208.2
September 7, 2010
X9522
Figure 25. DCP “Wiper Position” Timing
Rwx (x = 0,1,2)
Rwx(n + 1)
Rwx(n)
Rwx(n - 1)
twr
n = tap position
Time
SCL
SDA
S 1
T
A
R
T
0
1
0
1
1
1
SLAVE ADDRESS BYTE
21
0
A WT
C
K
0
0
0
0
0
INSTRUCTION BYTE
P1 P0
A
C
K
D7 D6 D5 D4 D3 D2 D1 D0
DATA BYTE
A
C
K
S
T
O
P
FN8208.2
September 7, 2010
X9522
D.C. OPERATING CHARACTERISTICS
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions / Notes
0.4
1.5
mA
fSCL = 400kHz
μA
VSDA = Vcc / V1
WP = Vss or Open/Floating
VSCL= Vcc / V1 (when no bus activity else fSCL = 400kHz)
10
μA
VIN (4) = GND to Vcc / V1.
10
μA
1
10
µA
0.1
10
μA
4.70
V
Current into Vcc / V1 Pin
(X9522: Active)
Read memory array (3)
Write nonvolatile memory
ICC1(1)
ICC2(2)
ILI
Current into Vcc / V1 Pin
(X9522:Standby)
With 2-Wire bus activity (3)
No 2-Wire bus activity
50
50
0.1
Input Leakage Current (SCL, SDA)
Input Leakage Current (WP)
Iai
Analog Input Leakage
ILO
Output Leakage Current (SDA, V2RO,
V3RO)
VIN = VSS to VCC with all other analog pins floating
VOUT (5) = GND to Vcc / V1.
X9522 is in Standby(2)
VTRIPxPR
VTRIPx Programming Range (x = 1,2)
1.8
VTRIP1 (6)
Pre - programmed VTRIP1 threshold
1.65
2.85
1.8
3.0
1.85
3.05
V
Factory shipped default option A
Factory shipped default option B
VTRIP2 (6)
Pre - programmed VTRIP2 threshold
1.65
2.85
1.8
3.0
1.85
3.05
V
Factory shipped default option A
Factory shipped default option B
IVx
V2 Input leakage current
V3 Input leakage current
1
1
μA
VIL (7)
Input LOW Voltage (SCL, SDA, WP)
-0.5
0.8
V
VIH (7)
Input HIGH Voltage (SCL,SDA, WP)
2.0
Vcc / V1
+0.5
V
VOLx
V2RO, V3RO, SDA Output Low Voltage
0.4
V
VSDA = VSCL = Vcc / V1
Others = GND or Vcc / V1
ISINK = 2.0mA
Notes: 1. The device enters the Active state after any START, and remains active until: 9 clock cycles later if the Device Select Bits in the Slave
Address Byte are incorrect; 200nS after a STOP ending a read operation; or tWC after a STOP ending a write operation.
Notes: 2.The device goes into Standby: 200nS after any STOP, except those that initiate a high voltage write cycle; tWC after a STOP that initiates
a high voltage cycle; or 9 clock cycles after any START that is not followed by the correct Device Select Bits in the Slave Address
Byte.
Notes: 3.Current through external pull up resistor not included.
Notes: 4.VIN = Voltage applied to input pin.
Notes: 5.VOUT = Voltage applied to output pin.
Notes: 6.See Ordering Information on page 2.
Notes: 7.VIL Min. and VIH Max. are for reference only and are not tested.
22
FN8208.2
September 7, 2010
X9522
A.C. CHARACTERISTICS (See Figure 20, Figure 21, Figure 22)
400kHz
Symbol
fSCL
tIN
(5)
Min
Max
Units
SCL Clock Frequency
Parameter
0
400
kHz
Pulse width Suppression Time at inputs
50
tAA(5)
tBUF(5)
SCL LOW to SDA Data Out Valid
0.1
Time the bus free before start of new transmission
1.3
μs
tLOW
Clock LOW Time
1.3
μs
tHIGH
Clock HIGH Time
0.6
μs
tSU:STA
Start Condition Setup Time
0.6
μs
tHD:STA
Start Condition Hold Time
0.6
μs
tSU:DAT
Data In Setup Time
100
ns
tHD:DAT
Data In Hold Time
0
μs
tSU:STO
Stop Condition Setup Time
0.6
μs
tDH(5)
tR(5)
Data Output Hold Time
50
ns
tF(5)
tSU:WP
WP Setup Time
tHD:WP
WP Hold Time
Cb(5)
Capacitive load for each bus line
ns
μs
0.9
SDA and SCL Rise Time
20 +.1Cb (2)
300
ns
SDA and SCL Fall Time
20 +.1Cb (2)
300
ns
μs
0.6
μs
0
400
pF
A.C. TEST CONDITIONS
Input Pulse Levels
0.1Vcc to 0.9Vcc
Input Rise and Fall Times
10ns
Input and Output Timing Levels
0.5Vcc
Output Load
See Figure 18
NONVOLATILE WRITE CYCLE TIMING
Symbol
tWC(4)
Parameter
Min.
Typ.(1)
Max.
Units
5
10
ms
Nonvolatile Write Cycle Time
CAPACITANCE (TA = 25°C, F = 1.0 MHZ, VCC / V1 = 5V)
Symbol
Parameter
Max
Units
Test Conditions
COUT (5)
Output Capacitance (SDA, V2RO, V3RO)
8
pF
VOUT = 0V
CIN (5)
Input Capacitance (SCL, WP)
6
pF
VIN = 0V
Notes: 1. Typical values are for TA = 25°C and Vcc / V1 = 5.0V
Notes: 2.Cb = total capacitance of one bus line in pF.
Notes: 3.Over recommended operating conditions, unless otherwise specified
Notes: 4.tWC is the time from a valid STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is
the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
Notes: 5.This parameter is not 100% tested.
23
FN8208.2
September 7, 2010
X9522
POTENTIOMETER CHARACTERISTICS
Limits
Symbol
Parameter
Min.
Typ.
Max.
Units
Test Conditions/Notes
RTOL
End to End Resistance Tolerance
-20
+20
%
VRHx
RH Terminal Voltage (x = 0,1,2)
Vss
Vcc /
V1
V
VRLx
RL Terminal Voltage (x = 0,1,2)
Vss
Vcc /
V1
V
PR
Power Rating (1)(6)
10
mW
RTOTAL = 10kΩ (DCP0,
DCP1)
5
mW
RTOTAL = 100kΩ (DCP2)
200
400
Ω
IW = 1mA, Vcc / V1 = 5 V,
VRHx = Vcc / V1, VRLx = Vss
(x = 0,1,2).
400
1200
Ω
IW = 1mA, Vcc / V1 = 2.7 V,
VRHx = Vcc / V1, VRLx = Vss
(x = 0,1,2)
4.4
mA
RW
IW
DCP Wiper Resistance
Wiper Current(6)
Noise
mV/
sqt(Hz)
RTOTAL = 10kΩ (DCP0,
DCP1)
mV/
sqt(Hz)
RTOTAL = 100kΩ (DCP2)
Absolute Linearity (2)
-1
+1
MI(4)
Rw(n)(actual) - Rw(n)(expected)
Relative Linearity (3)
-1
+1
MI(4)
Rw(n+1) - [Rw(n) + MI]
RTOTAL Temperature Coefficient
CH/CL/CW
Potentiometer Capacitances
twr
Wiper Response time(6)
VTRIP
Vcc / V1 power-up DCP recall
threshold
tPU
Vcc / V1 power-up DCP recall delay
time(6)
±300
ppm/°C
RTOTAL = 10kΩ (DCP0,
DCP1)
±300
ppm/°C
RTOTAL = 100kΩ (DCP2)
pF
10/10/25
200
μs
See Figure 19.
See Figure 25.
V
25
50
75
ms
Notes: 1. Power Rating between the wiper terminal RWX(n) and the end terminals RHX or RLX - for ANY tap position n, (x = 0,1,2).
Notes: 2.Absolute Linearity is utilized to determine actual wiper resistance versus, expected resistance = (Rwx(n)(actual) - Rwx(n)(expected)) = ±1 Ml
Maximum (x = 0,1,2).
Notes: 3.Relative Linearity is a measure of the error in step size between taps = RWx(n+1) - [Rwx(n) + Ml] = ±1 Ml (x = 0,1,2)
Notes: 4.1 Ml = Minimum Increment = RTOT / (Number of taps in DCP - 1).
Notes: 5.Typical values are for TA = 25°C and nominal supply voltage.
Notes: 6.This parameter is periodically sampled and not 100% tested.
24
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X9522
VTRIPX (X = 1,2) PROGRAMMING PARAMETERS (See Figure 24)
Parameter
Description
Min
Typ
Max
Units
tVPS
VTRIPx Program Enable Voltage Setup time
10
μs
tVPH
VTRIPx Program Enable Voltage Hold time
10
μs
tTSU
VTRIPx Setup time
10
μs
tTHD
VTRIPx Hold (stable) time
10
μs
tVPO
VTRIPx Program Enable Voltage Off time
(Between successive adjustments)
1
ms
twc
VTRIPx Write Cycle time
VP
Programming Voltage
Vta
Vtv
5
VTRIPx Program Voltage accuracy
(Programmed at 25°C.)
VTRIP Program variation after programming (-40 - 85°C).
(Programmed at 25°C.)
10
ms
10
15
V
-100
+100
mV
-25
+10
+25
mV
Min.
Typ.
Max.
Units
20
μs
Notes: These parameters are not 100% tested.
V2RO, V3RO OUTPUT TIMING. (See Figure 23)
Symbol
Description
Condition
tRPDx(4)
V2, V3 to V2RO, V3RO propagation
delay (respectively)
tFx(4)
V2, V3 Fall Time
20
mV/μs
tRx(4)
V2, V3 Rise Time
20
mV/μs
VRVALID(4)
Vcc / V1 for V2RO, V3RO Valid (3).
1
V
Notes: 1. See Figure 23 for timing diagram.
Notes: 2.See Figure 18 for equivalent load.
Notes: 3.This parameter describes the lowest possible Vcc / V1 level for which the outputs V2RO, and V3RO will be correct with respect to their
inputs ( V2, V3).
Notes: 4.The above parameters are not 100% tested.
25
FN8208.2
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X9522
APPENDIX 1
DCP1 (100 Tap) Tap position to Data Byte translation Table
Data Byte
Tap
Position
Decimal
Binary
0
0
0000 0000
1
1
0000 0001
.
.
.
.
.
.
23
23
0001 0111
24
24
0001 1000
25
56
0011 1000
26
55
0011 0111
.
.
.
.
.
.
48
33
0010 0001
49
32
0010 0000
50
64
0100 0000
51
65
0100 0001
.
.
.
.
.
.
73
87
0101 0111
74
88
0101 1000
75
120
0111 1000
76
119
0111 0111
.
.
.
.
.
.
98
97
0110 0001
99
96
0110 0000
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FN8208.2
September 7, 2010
X9522
APPENDIX 2
DCP1 (100 Tap) tap position to Data Byte translation algorithm example. (Example 1)
unsigned
{
int
int
int
int
DCP1_TAP_Position(int tap_pos)
block;
i;
offset;
wcr_val;
offset= 0;
block = tap_pos / 25;
if (block < 0) return ((unsigned)0);
else if (block <= 3)
{
switch(block)
{
case (0): return ((unsigned)tap_pos) ;
case (1):
{
wcr_val = 56;
offset = tap_pos - 25;
for (i=0; i<= offset; i++) wcr_val-- ;
return ((unsigned)++wcr_val);
}
case (2):
{
wcr_val = 64;
offset = tap_pos - 50;
for (i=0; i<= offset; i++) wcr_val++ ;
return ((unsigned)--wcr_val);
}
case (3):
{
wcr_val = 120;
offset = tap_pos - 75;
for (i=0; i<= offset; i++) wcr_val-- ;
return ((unsigned)++wcr_val);
}
}
}
return((unsigned)01100000);
}
27
FN8208.2
September 7, 2010
X9522
APPENDIX 2
DCP1 (100 Tap) tap position to Data Byte translation algorithm example. (Example 2)
unsigned DCP100_TAP_Position(int tap_pos)
{
/* optional range checking
*/ if (tap_pos < 0) return ((unsigned)0);
else if (tap_pos >99) return ((unsigned) 96);
/* set to min val */
/* set to max val */
/* 100 Tap DCP encoding formula */
if (tap_pos > 74)
return ((unsigned) (195 - tap_pos));
else if (tap_pos > 49)
return ((unsigned) (14 + tap_pos));
else if (tap_pos > 24)
return ((unsigned) (81 - tap_pos));
else return (tap_pos);
}
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FN8208.2
September 7, 2010
X9522
20-LEAD PLASTIC, TSSOP PACKAGE TYPE V
.025 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.252 (6.4)
.260 (6.6)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
(4.16) (7.72)
.010 (.25)
Gage Plane
0° - 8 °
Seating Plane
.019 (.50)
.029 (.75)
(1.78)
(0.42)
Detail A (20X)
(0.65)
ALL MEASUREMENTS ARE TYPICAL
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
29
FN8208.2
September 7, 2010
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