DATASHEET

X95840
®
Quad Digital Controlled Potentiometers (XDCP™)
Data Sheet
July 5, 2006
Low Noise/Low Power/I2C® Bus/256 Taps
The X95840 integrates four digitally controlled
potentiometers (XDCP) on a monolithic CMOS integrated
circuit.
The digitally controlled potentiometers are implemented with
a combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the
I2C bus interface. Each potentiometer has an associated
volatile Wiper Register (WR) and a non-volatile Initial Value
Register (IVR), that can be directly written to and read by the
user. The contents of the WR controls the position of the
wiper. At power up the device recalls the contents of the four
DCP’s IVR to the corresponding WRs.
The DCPs can be used as three-terminal potentiometers or
as two-terminal variable resistors in a wide variety of
applications including control, parameter adjustments, and
signal processing.
PART
MARKING
X95840WV20I-2.7*
X95840WV G
Features
• Four Potentiometers in One Package
• 256 Resistor Taps-0.4% Resolution
• I2C Serial Interface
- Three address pins, up to eight devices/bus
• Wiper Resistance: 70Ω Typical @ 3.3V
• Non-Volatile Storage of Wiper Position
• Standby Current < 5µA Max
• Power Supply: 2.7V to 5.5V
• 50kΩ, 10kΩ Total Resistance
• High Reliability
- Endurance: 150,000 data changes per bit per register
- Register data retention: 50 years @ T ≤ 75°C
• 20 Ld TSSOP
• Pb-Free Plus Anneal Available (RoHS Compliant)
Ordering Information
PART NUMBER
FN8213.2
Pinouts
RESISTANCE
OPTION
PACKAGE
10kΩ
20 Ld TSSOP
X95840WV20IZ-2.7* X95840WV Z G
(Note)
10kΩ
20 Ld TSSOP
(Pb-free)
RH3
1
20
RW0
X95840UV20I-2.7*
50kΩ
20 Ld TSSOP
RL3
2
19
RL0
20 Ld TSSOP
(Pb-free)
RW3
3
18
RH0
A2
4
17
WP
X95840UV G
X95840UV20IZ-2.7* X95840UV Z G
(Note)
50kΩ
*Add “T1” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
1
X95840
(20 LD TSSOP)
TOP VIEW
SCL
5
16
VCC
SDA
6
15
A1
GND
7
14
A0
RW2
8
13
RH1
RL2
9
12
RL1
RH2
10
11
RW1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X95840
Block Diagram
VCC
I2C
INTERFACE
SDA
SCL
POWER-UP,
INTERFACE,
CONTROL AND
StAtus LOGIC
WR3
DCP3
RH3
RW3
RL3
WR2
DCP2
RH2
RW2
RL2
WR1
DCP1
RH1
RW1
RL1
WR0
DCP0
RH0
RW0
RL0
A2
A1
A0
NON-VOLATILE
REGISTERS
WP
GND
Pin Descriptions
TSSOP PIN
SYMBOL
1
RH3
“High” terminal of DCP3
2
RL3
“Low” terminal of DCP3
3
RW3
“Wiper” terminal of DCP3
4
A2
5
SCL
I2C interface clock
6
SDA
Serial data I/O for the I2C interface
7
GND
Device ground pin
8
RW2
“Wiper” terminal of DCP2
9
RL2
“Low” terminal of DCP2
10
RH2
“High” terminal of DCP2
11
RW1
“Wiper” terminal of DCP1
12
RL1
“Low” terminal of DCP1
13
RH1
“High” terminal of DCP1
14
A0
Device address for the I2C interface
15
A1
Device address for the I2C interface
16
VCC
Power supply pin
17
WP
Hardware write protection pin. Active low. Prevents any “Write” operation of the I2C interface.
18
RH0
“High” terminal of DCP0
19
RL0
“Low” terminal of DCP0
20
RW0
“Wiper” terminal of DCP0
2
DESCRIPTION
Device address for the I2C interface
FN8213.2
July 5, 2006
X95840
Absolute Maximum Ratings
Recommended Operating Conditions
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage at any Digital Interface Pin
with Respect to GND . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC+0.3
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V
Voltage at any DCP Pin with Respect to GND. . . . . . . -0.3V to VCC
Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . . 300°C
IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
Temperature Range (Industrial) . . . . . . . . . . . . . . . . . . -40°C to 85°C
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Power Rating of Each DCP . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW
Wiper Current of Each DCP. . . . . . . . . . . . . . . . . . . . . . . . . . ±3.0mA
CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional
operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Analog Specifications
SYMBOL
RTOTAL
Over recommended operating conditions unless otherwise stated.
PARAMETER
RH to RL Resistance
TEST CONDITIONS
W, U versions respectively
RH to RL Resistance Tolerance
RW
CH/CL/CW
ILkgDCP
Wiper Resistance
MIN
MAX
10, 50
-20
VCC = 3.3V @ 25°C
Wiper current = VCC/RTOTAL
70
Potentiometer Capacitance (Note 15)
Leakage on DCP Pins (Note 15)
TYP
(Note 1)
kΩ
+20
%
200
Ω
10/10/25
Voltage at pin from GND to VCC
0.1
UNIT
pF
1
µA
-1
1
LSB
(Note 2)
-0.5
0.5
LSB
(Note 2)
LSB
(Note 2)
VOLTAGE DIVIDER MODE (0V @ RLi; VCC @ RHi; measured at RWi, unloaded; i = 0, 1, 2, or 3)
INL (Note 6)
Integral Non-linearity
DNL (Note 5) Differential Non-linearity
ZSerror
(Note 3)
Zero-scale Error
FSerror
(Note 4)
Full-scale Error
VMATCH
(Note 7)
DCP to DCP Matching
TCV (Note 8) Ratiometric Temperature Coefficient
Monotonic over all tap positions
U option
0
1
7
W option
0
0.5
2
U option
-7
-1
0
W option
-2
-1
0
Any two DCPs at same tap position, same
voltage at all RH terminals, and same voltage
at all RL terminals
-2
DCP Register set to 80 hex
2
±4
LSB
(Note 2)
LSB
(Note 2)
ppm/°C
RESISTOR MODE (Measurements between RWi and RLi with RHi not connected, or between RWi and RHi with RLi not connected. i = 0, 1, 2 or 3)
RINL
(Note 12)
Integral Non-linearity
RDNL
(Note 11)
Differential Non-linearity
Roffset
(Note 10)
Offset
DCP register set between 20 hex and
FF hex. Monotonic over all tap positions
1
MI
(Note 9)
-0.5
0.5
MI
(Note 9)
U option
0
1
7
MI
(Note 9)
W option
0
0.5
2
MI
(Note 9)
-2
2
MI
(Note 9)
RMATCH
(Note 13)
DCP to DCP Matching
Any two DCPs at the same tap position with
the same terminal voltages.
TCR
(Note 14)
Resistance Temperature Coefficient
DCP register set between 20 hex and FF hex
3
-1
±45
ppm/°C
FN8213.2
July 5, 2006
X95840
Operating Specifications Over the recommended operating conditions unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
(Note 1)
MAX
UNITS
= 400kHz; SDA = Open; (for I2C,
ICC1
VCC Supply Current
(Volatile write/read)
fSCL
Active, Read and Volatile Write States only)
1
mA
ICC2
VCC Supply Current
(nonvolatile write)
fSCL = 400kHz; SDA = Open; (for I2C,
Active, Nonvolatile Write State only)
3
mA
VCC Current (standby)
VCC = +5.5V, I2C Interface in Standby State
5
µA
= +3.6V, I2C Interface in Standby State
2
µA
10
µA
1
µs
2.6
V
ISB
VCC
ILkgDig
Leakage Current, at
Pins A0, A1, A2, SDA, SCL,
and WP Pins
Voltage at pin from GND to VCC
tDCP
(Note 15)
DCP Wiper Response Time
SCL falling edge of last bit of DCP Data Byte to wiper
change
Power-on Recall Voltage
Minimum VCC at which memory recall occurs
Vpor
VccRamp
VCC Ramp Rate
tD (Note 15)
Power-up Delay
-10
1.8
0.2
VCC above Vpor, to DCP Initial Value Register recall
completed, and I2C Interface in standby state
V/ms
3
ms
EEPROM SPECS
EEPROM Endurance
EEPROM Retention
Temperature ≤ 75°C
150,000
Cycles
50
Years
SERIAL INTERFACE SPECS
VIL
WP, A2, A1, A0, SDA, and
SCL Input Buffer LOW
Voltage
-0.3
0.3*VCC
V
VIH
WP, A2, A1, A0, SDA, and
SCL Input Buffer HIGH
Voltage
0.7*VCC
VCC+0.3
V
Hysteresis
(Note 15)
SDA and SCL Input Buffer
Hysteresis
0.05*
VCC
VOL (Note 15) SDA outPut Buffer LOW
Voltage, Sinking 4mA
Cpin
(Note 15)
fSCL
tIN (Note 15)
0.4
V
WP, A2, A1, A0, SDA, and
SCL Pin Capacitance
10
pF
SCL frEquency
400
kHz
Pulse Width Suppression
Any pulse narrower than the max spec is suppressed.
Time at SDA and SCL Inputs
50
ns
900
ns
tAA (Note 15) SCL Falling Edge to SDA
Output Data Valid
0
V
SCL falling edge crossing 30% of VCC, until SDA exits
the 30% to 70% of VCC window.
Time the Bus Must be Free
Before the Start of a New
Transmission
SDA crossing 70% of VCC during a STOP condition, to
SDA crossing 70% of VCC during the following START
condition.
1300
ns
tLOW
Clock LOW Time
Measured at the 30% of VCC crossing.
1300
ns
tHIGH
Clock HIGH Time
Measured at the 70% of VCC crossing.
600
ns
tSU:STA
START Condition Setup
Time
SCL rising edge to SDA falling edge. Both crossing
70% of VCC.
600
ns
tHD:STA
START Condition Hold Time
From SDA falling edge crossing 30% of VCC to SCL
falling edge crossing 70% of VCC.
600
ns
tBUF
(Note 15)
4
FN8213.2
July 5, 2006
X95840
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TYP
(Note 1)
TEST CONDITIONS
MIN
MAX
UNITS
100
ns
0
ns
tSU:DAT
Input Data Setup Time
From SDA exiting the 30% to 70% of VCC window, to
SCL rising edge crossing 30% of VCC
tHD:DAT
Input Data Hold Time
From SCL rising edge crossing 70% of VCC to SDA
entering the 30% to 70% of VCC window.
tSU:STO
STOP Condition Setup Time From SCL rising edge crossing 70% of VCC, to SDA
rising edge crossing 30% of VCC.
600
ns
tHD:STO
STOP Condition Setup Time From SDA rising edge to SCL falling edge. Both
crossing 70% of VCC.
600
ns
0
ns
tDH (Note 15) Output Data Hold Time
From SCL falling edge crossing 30% of VCC, until SDA
enters the 30% to 70% of VCC window.
tR (Note 15)
SDA and SCL Rise Time
From 30% to 70% of VCC
20 +
0.1 * Cb
250
ns
tF (Note 15)
SDA and SCL Fall Time
From 70% to 30% of VCC
20 +
0.1 * Cb
250
ns
Cb (Note 15)
Capacitive Loading of SDA
or SCL
Total on-chip and off-chip
10
400
pF
Maximum is determined by tR and tF.
For Cb = 400pF, max is about 2~2.5kΩ.
For Cb = 40pF, max is about 15~20kΩ
1
Rpu (Note 15) SDA and SCL Bus Pull-up
Resistor Off-chip
tWP
Non-volatile Write Cycle
(Notes 15, 16) Time
kΩ
12
20
ms
tSU:WPA
A2, A1, A0, and WP Setup
Time
Before START condition
600
ns
tHD:WPA
A2, A1, A0, and WP Hold
Time
After STOP condition
600
ns
SDA vs SCL Timing
tF
SCL
tHIGH
tLOW
tR
tSU:DAT
tSU:STA
tHD:DAT
tSU:STO
tHD:STA
SDA
(INPUT TIMING)
tAA
tDH
tBUF
SDA
(OUTPUT TIMING)
5
FN8213.2
July 5, 2006
X95840
WP, A0, A1, and A2 Pin Timing
STOP
START
SCL
Clk 1
SDA IN
tSU:WPA
tHD:WPA
WP, A0, A1, or A2
NOTES:
1. Typical values are for TA = 25°C and 3.3V supply voltage.
2. LSB: [V(RW)255 - V(RW)0] / 255. V(RW)255 and V(RW)0 are V(RW) for the DCP register set to FF hex and 00 hex respectively. LSB is the
incremental voltage when changing from one tap to an adjacent tap.
3. ZS error = V(RW)0 / LSB.
4. FS error = [V(RW)255 - VCC] / LSB.
5. DNL = [V(RW)i - V(RW)i-1] / LSB-1, for i = 1 to 255. i is the DCP register setting.
6. INL = [V(RW)i – (i • LSB – V(RW)0)]/LSB for i = 1 to 255.
7. VMATCH = [V(RWx)i - V(RWy)i] / LSB, for i = 0 to 255, x = 0 to 3 and y = 0 to 3.
Max ( V ( RW ) i ) – Min ( V ( RW ) i )
10 6
- × ----------------8. TC V = --------------------------------------------------------------------------------------------[ Max ( V ( RW ) i ) + Min ( V ( RW ) i ) ] ⁄ 2 125°C
for i = 16 to 240 decimal, T = -40°C to 85°C. Max( ) is the maximum value of the wiper voltage and Min ( ) is the minimum value of the wiper
voltage over the temperature range.
9. MI = |R255 - R0| / 255. R255 and R0 are the measured resistances for the DCP register set to FF hex and 00 hex respectively.
10. Roffset = R0 / MI, when measuring between RW and RL.
Roffset = R255 / MI, when measuring between RW and RH.
11. RDNL = (Ri - Ri-1) / MI, for i = 32 to 255.
12. RINL = [Ri - (MI • i) - R0] / MI, for i = 32 to 255.
13. RMATCH = (Ri,x - Ri,y) / MI, for i = 0 to 255, x = 0 to 3 and y = 0 to 3.
6
[ Max ( Ri ) – Min ( Ri ) ]
10
14. TC R = ---------------------------------------------------------------- × ----------------[ Max ( Ri ) + Min ( Ri ) ] ⁄ 2 125°C
for i = 32 to 255, T = -40°C to 85°C. Max( ) is the maximum value of the resistance and Min ( ) is the minimum value of the resistance over the
temperature range.
15. This parameter is not 100% tested.
16. tWC is the minimum cycle time to be allowed for any non-volatile Write by the user, unless Acknowledge Polling is used. It is the time from a
valid STOP condition at the end of a Write sequence of a I2C serial interface Write operation, to the end of the self-timed internal non-volatile
write cycle.
6
FN8213.2
July 5, 2006
X95840
Typical Performance Curves
1.8
160
VCC = 2.7, T = 85°C
VCC = 2.7, T = -40°C
1.6
VCC = 2.7, T = 25°C
1.4
120
100
80
60
40
20
0
1.2
STANDBY ICC (µA)
WIPER RESISTANCE (Ω)
140
VCC = 5.5, T = -40°C
0
50
1.0
0.8
150
200
85°C
0.6
0.4
VCC = 5.5, T = 85°C
VCC = 5.5, T = 25°C
100
-40°C
0.2
25°C
0.0
2.7
250
3.2
3.7
0.3
0.15
VCC = 5.5, T = -40°C
4.7
5.2
FIGURE 2. STANDBY ICC vs VCC
FIGURE 1. WIPER RESISTANCE vs TAP POSITION
[ I(RW) = VCC/RTOTAL ] FOR 50kΩ (U)
0.2
4.2
VCC (V)
TAP POSITION (DECIMAL)
VCC = 2.7, T = -40°C
VCC = 5.5, T = -40°C
VCC = 2.7, T = -40°C
VCC = 2.7, T = 25°C
0.2
VCC = 5.5, T = 85°C
0.1
0.05
INL (LSB)
DNL (LSB)
0.1
0
-0.05
-0.1
-0.15
-0.2
0
VCC = 5.5, T = 25°C
VCC = 2.7, T = 85°C
VCC = 5.5, T = 85°C
50
100
150
200
0
VCC = 2.7, T = 25°C
VCC = 2.7, T = 85°C
-0.1
VCC = 5.5, T = 25°C
-0.2
-0.3
250
0
50
100
150
200
250
TAP POSITION (DECIMAL)
TAP POSITION (DECIMAL)
FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER
MODE FOR 10kΩ (W)
FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER
MODE FOR 10kΩ (W)
0
0.4
-0.1
-0.2
0.35
VCC = 5.5V
FSerror (LSB)
ZSerror (LSB)
-0.3
0.3
2.7V
0.25
0.2
-0.4
VCC = 2.7V
-0.5
-0.6
-0.7
-0.8
5.5V
-0.9
0.15
-40
-20
0
20
40
60
TEMPERATURE (°C)
FIGURE 5. ZSerror vs TEMPERATURE
7
80
-1
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
FIGURE 6. FSerror vs TEMPERATURE
FN8213.2
July 5, 2006
X95840
Typical Performance Curves
(Continued)
0.3
0.5
VCC = 2.7, T = 25°C
0.4
VCC = 5.5, T = 25°C
0.2
INL (LSB)
DNL (LSB)
VCC = 5.5, T = -40°C
0.2
0.1
0
-0.1
0.1
VCC = 5.5, T = 85°C
0
-0.1
-0.2
VCC = 5.5, T = 85°C
-0.3
VCC = 2.7, T = 85°C
VCC = 2.7, T = -40°C
VCC = 5.5, T = -40°C
-0.2
-0.3
32
82
132
182
TAP POSITION (DECIMAL)
-0.4 VCC = 2.7, T = 85°C
VCC = 5.5, T = 25°C
-0.5
32
82
132
232
VCC = 2.7, T = -40°C
182
232
TAP POSITION (DECIMAL)
FIGURE 7. DNL vs TAP POSITION IN Rheostat MODE FOR
50kΩ (U)
FIGURE 8. INL vs TAP POSITION IN Rheostat MODE FOR
50kΩ (U)
1.50
20
1.00
10
0.50
0.00
2.7V
TC (ppm/°C)
END TO END RTOTAL CHANGE (%)
VCC = 2.7, T = 25°C
0.3
5.5V
-0.50
0
-10
-1.00
-1.50
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
-20
32
82
132
182
232
TAP POSITION (DECIMAL)
FIGURE 10. TC FOR VOLTAGE DIVIDER MODE IN ppm
FIGURE 9. END TO END RTOTAL % CHANGE vs
TEMPERATURE
35
INPUT
25
TC (ppm/°C)
15
5
OUTPUT
-5
Tap Position = Mid Point
RTOTAL = 9.4K
-15
-25
32
57
82
107
132
157
182
207
TAP POSITION (DECIMAL)
232
FIGURE 12. FREQUENCY RESPONSE (2.2MHz)
FIGURE 11. TC FOR Rheostat MODE IN ppm
8
FN8213.2
July 5, 2006
X95840
Typical Performance Curves
(Continued)
SCL
Signal at Wiper (Wiper Unloaded)
Signal at Wiper
(Wiper Unloaded Movement
From ffh to 00h)
Wiper Movement Mid Point
From 80h to 7fh
FIGURE 13. MIDSCALE GLITCH, CODE 80h TO 7Fh (WIPER 0)
FIGURE 14. LARGE SIGNAL SETTLING TIME
Principles of Operation
Memory Description
The X95840 in as integrated circuit incorporating four DCPs
with their associated registers, non-volatile memory, and a
I2C serial interface providing direct communication between
a host and the potentiometers and memory.
The X95840 contains eight non-volatile bytes. they are
accessed by I2C interface operations with Address Bytes 0
through 7 decimal. The first four non-volatile bytes at
addresses 0, 1, 2, and 3, contain the initial value loaded at
power-up into the volatile Wiper Registers (WRs) of DCP0,
DCP1, DCP2, and DCP3 respectively. Bytes at addresses 4,
5, and 6 are available to the user as general purpose
registers. The byte at address 7 is reserved; the user should
not write to it, and its value should be ignored if read.
DCP Description
Each DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each
DCP are equivalent to the fixed terminals of a mechanical
potentiometer (RH and RL pins). The RW pin of each DCP is
connected to intermediate nodes, and is equivalent to the
wiper terminal of a mechanical potentiometer. The position
of the wiper terminal within the DCP is controlled by an 8-bit
volatile Wiper Register (WR). Each DCP has its own WR.
When the WR of a DCP contains all zeroes (WR<7:0>: 00h),
its wiper terminal (RW) is closest to its “Low” terminal (RL).
When the WR of a DCP contains all ones (WR<7:0>: FFh),
its wiper terminal (RW) is closest to its “High” terminal (RH).
As the value of the WR increases from all zeroes (00h) to all
ones (255 decimal), the wiper moves monotonically from the
position closest to RL to the closest to RH. At the same time,
the resistance between RW and RL increases monotonically,
while the resistance between RH and RW decreases
monotonically.
While the X95840 is being powered up, all four WRs are
reset to 80h (128 decimal), which locates RW roughly at the
center between RL and RH. Soon after the power supply
voltage becomes large enough for reliable non-volatile
memory reading, the X95840 reads the value stored on four
different non-volatile Initial Value Registers (IVRs) and loads
them into their corresponding WRs.
The volatile WR, and the non-volatile Initial Value Register
(IVR) of a DCP are accessed with the same Address Byte.
A volatile byte at address 8 decimal, controls what byte is
read or written when accessing DCP registers: the WR, the
IVR, or both.
When the byte at address 8 is all zeroes, which is the default
at power up:
• A read operation to addresses 0, 1, 2 or 3 outputs the
value of the non-volatile IVRs.
• A write operation to addresses 0, 1, 2, or 3 writes the
same value to the WR and IVR of the corresponding DCP.
When the byte at address 8 is 80h (128 decimal):
• A read operation to addresses 0, 1, 2, or 3 outputs the
value of the volatile WR.
• A write operation to addresses 0, 1, 2, or 3 only writes to
the corresponding volatile WR.
It is not possible to write to an IVR without writing the same
value to its corresponding WR.
The WRs and IVRs can be read or written directly using the
I2C serial interface as described in the following sections.
00h and 80h are the only values that should be written to
address 8. All other values are reserved and must not be
written to address 8.
To access the general purpose bytes at addresses 4, 5, or 6,
the value at address 8 must be all zeros.
9
FN8213.2
July 5, 2006
X95840
Figure 15). A START condition is ignored during the power
up sequence and during internal non-volatile write cycles.
The X95840 is pre-programed with 80h in the four IVRs.
TABLE 1. MEMORY MAP
ADDRESS
NON-VOLATILE
VOLATILE
8
—
Access Control
7
All I2C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (See Figure 15). A STOP condition at the end
of a read operation, or at the end of a write operation to
volatile bytes only places the device in its standby mode. A
STOP condition during a write operation to a non-volatile
byte, initiates an internal non-volatile write cycle. The device
enters its standby state when the internal non-volatile write
cycle is completed.
Reserved
6
5
4
General Purpose
Not Available
3
2
1
0
IVR3
IVR2
IVR1
IVR0
WR3
WR2
WR1
WR0
WR: Wiper Register, IVR: Initial value Register.
I2C Serial Interface
The X95840 supports a bidirectional I2C bus oriented
protocol. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device as the
receiver. The device controlling the transfer is a master and
the device being controlled is the slave. The master always
initiates data transfers and provides the clock for both
transmit and receive operations. Therefore, the X95840
operates as a slave device in all applications.
All communication over the I2C interface is conducted by
sending the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line can change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (See
Figure 15). On power up of the X95840 the SDA pin is in the
input mode.
All I2C interface operations must begin with a START
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The X95840 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met (See
An ACK, Acknowledge, is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (See Figure 16).
The X95840 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
X95840 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation
A valid Identification Byte contains 1010 as the four MSBs,
and the following three bits matching the logic values
present at pins A2, A1, and A0. The LSB in the Read/Write
bit. Its value is “1” for a Read operation, and “0” for a Write
operation. See Table 2.
TABLE 2. IDENTIFICATION BYTE FORMAT
Logic values at pins A2, A1, and A0 respectively
1
0
1
0
(MSB)
A2
A1
A0
R/W
(LSB)
SCL
SDA
START
DATA
STABLE
DATA
CHANGE
DATA
STABLE
STOP
FIGURE 15. VALID DATA CHANGES, START, AND STOP CONDITIONS
10
FN8213.2
July 5, 2006
X95840
SCL from Master
1
8
9
SDA Output from
Transmitter
High Impedance
High Impedance
SDA Output from
Receiver
START
ACK
FIGURE 16. ACKNOWLEDGE RESPONSE FROM RECEIVER
Write
Signals from the
Master
Signal at SDA
S
t
a
r
t
1 0 1 0 A2A1A00
Signals from the
X95840
S
t
o
p
Data
Byte
Address
Byte
Identification
Byte
0 0 0 0
A
C
K
A
C
K
A
C
K
FIGURE 17. BYTE WRITE SEQUENCE
Write Operation
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
X95840 responds with an ACK. At this time, if the Data Byte
is to be written only to volatile registers, then the device
enters its standby state. If the Data Byte is to be written also
to non-volatile memory, the X95840 begins its internal write
cycle to non-volatile memory. During the internal non-volatile
write cycle, the device ignores transitions at the SDA and
SCL pins, and the SDA output is at a high impedance state.
When the internal non-volatile write cycle is completed, the
X95840 enters its standby state (See Figure 17).
The byte at address 00001000 bin (8 decimal) determines if
the Data Byte is to be written to volatile and/or non-volatile
memory. See “Memory Description” on page 9.
Data Protection
The WP pin has to be at logic HIGH to perform any Write
operation to the device. When the WP is active (LOW) the
device ignores Data Bytes of a Write Operation, does not
respond to the Data Bytes with an ACK, and instead, goes to
its standby state waiting for a new START condition.
11
A STOP condition also acts as a protection of non-volatile
memory. A valid Identification Byte, Address Byte, and total
number of SCL pulses act as a protection of both volatile
and non-volatile registers. During a Write sequence, the
Data Byte is loaded into an internal shift register as it is
received. If the Address Byte is 0, 1, 2, 3, or 8 decimal, the
Data Byte is transferred to the appropriate Wiper Register
(WR) or to the Access Control Register, at the falling edge of
the SCL pulse that loads the last bit (LSB) of the Data Byte.
If the Address Byte is between 0 and 6 (inclusive), and the
Access Control Register is all zeros (default), then the STOP
condition initiates the internal write cycle to non-volatile
memory.
Read Operation
A Read operation consist of a three byte instruction followed
by one or more Data Bytes (See Figure 18). The master
initiates the operation issuing the following sequence: a
START, the Identification byte with the R/W bit set to “0”, an
Address Byte, a second START, and a second Identification
byte with the R/W bit set to “1”. After each of the three bytes,
the X95840 responds with an ACK. Then the X95840
transmits Data Bytes as long as the master responds with an
ACK during the SCL cycle following the eight bit of each
byte. The master terminates the read operation (issuing a
FN8213.2
July 5, 2006
X95840
STOP condition) following the last bit of the last Data Byte
(See Figure 18).
pointer “rolls over” to 00h, and the device continues to output
data for each ACK received.
The Data Bytes are from the memory location indicated by
an internal pointer. This pointer initial value is determined by
the Address Byte in the Read operation instruction, and
increments by one during transmission of each Data Byte.
After reaching the memory location 08h (8 decimal) the
The byte at address 00001000 bin (8 decimal) determines if
the Data Bytes being read are from volatile or non-volatile
memory. See “Memory Description” on page 9.
Signals
from the
Master
S
t
a
r
t
Signal at SDA
Identification
Byte
with
R/W=0
10 10
S
t
a
r
t
Address
Byte
10 10
0
A
C
K
Signals from the
Slave
Identification
Byte
with
R/W=1
A
C
K
A
C
K
S
t
o
p
A
C
K
1
A
C
K
First Read Data
Byte
Last Read Data
Byte
FIGURE 18. READ SEQUENCE
12
FN8213.2
July 5, 2006
X95840
Thin Shrink Small Outline Package Family (TSSOP)
MDP0044
0.25 M C A B
D
THIN SHRINK SMALL OUTLINE PACKAGE FAMILY
A
SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE
(N/2)+1
N
PIN #1 I.D.
E
E1
0.20 C B A
1
(N/2)
B
2X
N/2 LEAD TIPS
TOP VIEW
0.05
e
C
H
A
1.20
1.20
1.20
1.20
1.20
Max
A1
0.10
0.10
0.10
0.10
0.10
±0.05
A2
0.90
0.90
0.90
0.90
0.90
±0.05
b
0.25
0.25
0.25
0.25
0.25
+0.05/-0.06
c
0.15
0.15
0.15
0.15
0.15
+0.05/-0.06
D
5.00
5.00
6.50
7.80
9.70
±0.10
E
6.40
6.40
6.40
6.40
6.40
Basic
E1
4.40
4.40
4.40
4.40
4.40
±0.10
e
0.65
0.65
0.65
0.65
0.65
Basic
L
0.60
0.60
0.60
0.60
0.60
±0.15
L1
1.00
1.00
1.00
1.00
1.00
Reference
Rev. E 12/02
NOTES:
SEATING
PLANE
0.10 M C A B
b
0.10 C
N LEADS
SIDE VIEW
1. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15mm per side.
2. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm per
side.
3. Dimensions “D” and “E1” are measured at dAtum Plane H.
SEE DETAIL “X”
c
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
END VIEW
L1
A
A2
GAUGE
PLANE
0.25
L
A1
0° - 8°
DETAIL X
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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13
FN8213.2
July 5, 2006
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