DATASHEET

ESIGNS
R NEW D NT
O
F
D
E
ND
L ACEM E
COMME
N OT R E
DED REP rt Center at
N
E
M
M
ECOSheet ical Suppo
NO R
/tsc
Data
5, 2008
mDecember
n
tersil.co
our Tech
c
ta
con t ERSIL or www.in
T
1-888-IN
10-Bit, 275/210/170/105MSPS A/D
Converter
• On-Chip Reference
• Internal Sample and Hold
• 1.5VP-P Differential Input Voltage
• 600MHz Analog Input Bandwidth
• Two’s Complement or Binary Output
• Over-Range Indicator
• Selectable 2 Clock Input
• LVCMOS Outputs
• Pb-Free (RoHS Compliant)
Applications
• High-Performance Data Acquisition
• Portable Oscilloscope
OVDD
CLKDIV
AVDD3
FN6814.0
Features
The KAD2710C is the industry’s lowest power, 10-bit,
275MSPS, high performance Analog-to-Digital converter. It
is designed with Intersil’s proprietary FemtoCharge™
technology on a standard CMOS process. The KAD2710C
offers high dynamic performance (55.6dBFS SNR @
fIN = 138MHz) while consuming less than 265mW. Features
include an over-range indicator and a selectable divide-by-2
input clock divider. The KAD2710C is one member of a
pin-compatible family offering 8 and 10-bit ADCs with
sample rates from 105 to 350MSPS and LVDS-compatible or
LVCMOS outputs (Table 1). This family of products is
available in 68-pin RoHS-compliant QFN packages with
exposed paddle. Performance is specified over the full
industrial temperature range (-40°C to +85°C).
AVDD2
KAD2710C
• Medical Imaging
• Cable Head Ends
CLK_P
Clock
Generation
CLK_N
CLKOUTP
• Power-Amplifier Linearization
CLKOUTN
• Radar and Satellite Antenna Array Processing
D9 – D0
• Broadband Communications
• Point-to-Point Microwave Systems
10-bit 10
275MSPS
ADC
INP
S/H
INN
OR
LVCMOS
Drivers
Key Specs
VREF
1.21V
VREFSEL
• Communications Test Equipment
2SC
+
–
• SNR = 55.6dBFS at fS = 275MSPS, fIN = 138MHz
• SFDR = 68.5dBc at fS = 275MSPS, fIN = 138MHz
• Power consumption <265mW at fS = 275MSPS
AVSS
OVSS
VCM
Pin-Compatible Family
TABLE 1. PIN-COMPATIBLE PRODUCTS
RESOLUTION, SPEED LVDS OUTPUTS LVCMOS OUTPUTS
1
8 Bits 350MSPS
KAD2708L-35
8 Bits 275MSPS
KAD2708L-27
KAD2708C-27
8 Bits 210MSPS
KAD2708L-21
KAD2708C-21
8 Bits 170MSPS
KAD2708L-17
KAD2708C-17
8 Bits 105MSPS
KAD2708L-10
KAD2708C-10
10 Bits 275MSPS
KAD2710L-27
KAD2710C-27
10 Bits 210MSPS
KAD2710L-21
KAD2710C-21
10 Bits 170MSPS
KAD2710L-17
KAD2710C-17
10 Bits 105MSPS
KAD2710L-10
KAD2710C-10
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
FemtoCharge is a trademark of Kenet Inc. Copyright Intersil Americas Inc. 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
KAD2710C
Ordering Information
PART NUMBER
(Note)
SPEED
(MSPS)
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
KAD2710C-27Q68
275
-40 to +85
68 Ld QFN
L68.10x10B
KAD2710C-21Q68
210
-40 to +85
68 Ld QFN
L68.10x10B
KAD2710C-17Q68
170
-40 to +85
68 Ld QFN
L68.10x10B
KAD2710C-10Q68
105
-40 to +85
68 Ld QFN
L68.10x10B
PKG. DWG. #
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2
FN6814.0
December 5, 2008
KAD2710C
Table of Contents
Absolute Maximum Ratings ......................................... 4
Thermal Information...................................................... 4
Electrical Specifications ............................................... 4
Digital Specifications .................................................... 5
Timing Diagram ............................................................. 6
Timing Specifications ................................................... 6
Thermal Impedance....................................................... 6
ESD ................................................................................. 6
Pin Descriptions ............................................................ 7
Pinout ............................................................................. 8
Typical Performance Curve .......................................... 9
Functional Description ................................................. 12
Reset ..........................................................................
Voltage Reference......................................................
Analog Input ...............................................................
Clock Input .................................................................
Jitter............................................................................
Digital Outputs ............................................................
12
12
12
13
13
14
Equivalent Circuits........................................................ 14
Layout Considerations ................................................. 15
Split Ground and Power Planes .................................
Clock Input Considerations.........................................
Bypass and Filtering ...................................................
LVCMOS Outputs.......................................................
Unused Inputs ............................................................
15
15
15
15
15
Definitions...................................................................... 15
Package Outline Drawing ............................................. 16
L68.10x10B ..................................................................... 16
3
FN6814.0
December 5, 2008
KAD2710C
Absolute Maximum Ratings
Thermal Information
AVDD2 to AVSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 2.1V
AVDD3 to AVSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 3.7V
OVDD2 to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 2.1V
Analog Inputs to AVSS. . . . . . . . . . . . . . . . . -0.4V to AVDD3 + 0.3V
Clock Inputs to AVSS. . . . . . . . . . . . . . . . . . -0.4V to AVDD2 + 0.3V
Logic Inputs to AVSS (VREFSEL, CLKDIV) -0.4V to AVDD3 + 0.3V
Logic Inputs to OVSS (RST, 2SC) . . . . . . . . -0.4V to OVDD2 + 0.3V
VREF to AVSS . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD3 + 0.3V
Analog Output Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
Logic Output Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
LVDS Output Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD2 = 1.8V, AVDD3 = 3.3V,
OVDD = 1.8V, TA = -40°C to +85°C (typical specifications at +25°C), fSAMPLE = 350MSPS, 270MSPS,
210MSPS, 170MSPS and 105MSPS, fIN = Nyquist at -0.5dBFS.
KAD2710C-27
PARAMETER
SYMBOL
CONDITIONS
KAD2710C-21
KAD2710C-17
KAD2710C-10
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
DC SPECIFICATIONS
Analog Input
Full-Scale Analog Input
Range
VFS
Full Scale Range Temp.
Drift
AVTC
Common-Mode Output
Voltage
VCM
1.4
Full Temp
1.5
1.6
1.4
1.5
1.6
1.4
1.5
1.6
1.4
1.5
1.6
VP-P
230
210
198
178
ppm/°C
860
860
860
860
mV
Power Requirements
1.8V Analog Supply
Voltage
AVDD2
1.7
1.8
1.9
1.7
1.8
1.9
1.7
1.8
1.9
1.7
1.8
1.9
V
3.3V Analog Supply
Voltage
AVDD3
3.15
3.3
3.45 3.15
3.3
3.45 3.15
3.3
3.45 3.15
3.3
3.45
V
1.8V Digital Supply Voltage
OVDD
1.7
1.8
1.9
1.8
1.9
1.8
1.9
1.8
1.9
V
1.8V Analog Supply
Current
IAVDD2
44
51
38
42
35
39
29
33
mA
3.3V Analog Supply
Current
IAVDD3
41
45
33
37
28
32
21
24
mA
1.8V Digital Supply Current
I
Power Dissipation
1.7
1.7
1.7
OVDD
26
30
25
28
24
27
23
26
mA
PD
261
294
222
248
199
224
163
185
mW
AC SPECIFICATIONS
Maximum Conversion
Rate
fS MAX
Minimum Conversion Rate
fS MIN
Differential Nonlinearity
275
INL
Signal-to-Noise Ratio
SNR
SINAD
50
MSPS
50
50
MSPS
LSB
-1.0 ±0.8
1.5
-1.0 ±0.8
1.5
-1.0 ±0.8
1.5
-1.0 ±0.8
1.5
-2.5 ±1.0
2.0
-2.5 ±1.0
1.5
-2.5 ±1.0
1.5
-2.5 ±1.0
1.5
LSB
55.7
56.4
56.6
56.6
dBFS
fIN = Nyquist
53.5 55.6
53.5 56.2
53.5 56.5
53.5 56.5
dBFS
55.2
54.8
54.6
54.5
dBFS
fIN = 10MHz
55.3
56.1
56.3
56.3
dBFS
fIN = Nyquist
52.5 55.2
52.5 56.0
52.5 56.2
52.5 56.2
dBFS
54.4
53.7
53.4
53.2
dBFS
fIN = 430MHz
4
105
fIN = 10MHz
fIN = 430MHz
Signal-to-Noise and
Distortion
170
50
DNL
Integral Nonlinearity
210
FN6814.0
December 5, 2008
KAD2710C
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD2 = 1.8V, AVDD3 = 3.3V,
OVDD = 1.8V, TA = -40°C to +85°C (typical specifications at +25°C), fSAMPLE = 350MSPS, 270MSPS,
210MSPS, 170MSPS and 105MSPS, fIN = Nyquist at -0.5dBFS. (Continued)
KAD2710C-27
PARAMETER
SYMBOL
Effective Number of Bits
ENOB
CONDITIONS
Two-Tone SFDR
SFDR
KAD2710C-17
KAD2710C-10
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
fIN = 10MHz
8.9
fIN = Nyquist
Spurious-Free Dynamic
Range
KAD2710C-21
8.4
8.9
9.0
8.4
9.0
9.1
8.4
9.0
8.4
9.1
Bits
9.0
Bits
fIN = 430MHz
8.7
8.6
8.6
8.5
Bits
fIN = 10MHz
68.5
70
71
71
dBc
fIN = Nyquist
72
dBc
fIN = 430MHz
62
63.8
68.5
62.6
60.1
60.9
dBc
2TSFDR fIN = 133MHz, 135MHz
68
70
70
71
dBc
10-12
10-12
10-12
600
600
600
Word Error Rate
WER
10-12
Full Power Bandwidth
FPBW
600
62
71.1
62
71
62
MHz
Digital Specifications
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
INPUTS
Input Voltage High (VREFSEL)
VIH
Input Voltage Low (VREFSEL)
VIL
0.8*AVDD3
Input Current High (VREFSEL)
IIH
VIN = AVDD3
Input Current Low (VREFSEL)
IIL
VIN = AVSS
Input Voltage High (CLKDIV)
VIH
Input Voltage Low (CLKDIV)
VIL
Input Current High (CLKDIV)
IIH
VIN = AVDD3
Input Current Low (CLKDIV)
IIL
VIN = AVSS
Input Voltage High (RST,2SC)
VIH
Input Voltage Low (RST,2SC)
VIL
-90
V
0.2*AVDD3
V
0
10
µA
-65
-30
µA
0.8*AVDD3
100
V
0.2*AVDD3
V
65
10
µA
0
-10
µA
0.8*OVDD2
Input Current High (RST,2SC)
IIH
VIN = OVDD
Input Current Low (RST,2SC)
IIL
VIN = OVSS
Input Capacitance
CDI
-50
V
0.2*OVDD2
V
0
10
µA
-30
-5
µA
3
pF
CLKP, CLKN P-P Differential Input Voltage
VCDI
CLKP, CLKN Differential Input Resistance
RCDI
10
M
CLKP, CLKN Common-Mode Input Voltage
VCCI
0.9
V
Output Voltage High
VOH
1.8
V
Output Voltage Low
0.5
3.6
VP-P
LVCMOS OUTPUTS
VOL
0
V
Output Rise Time
tR
1.8
ns
Output Fall Time
tF
1.4
ns
5
FN6814.0
December 5, 2008
KAD2710C
Timing Diagram
Sample N
INP
INN
tA
CLKN
CLKP
L
tPID
CLKOUT
tPCD
tPH
D[9:0]
Data N-L
Data N-L+1
Data N
invalid
FIGURE 1. LVCMOS TIMING DIAGRAM
Timing Specifications
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
Aperture Delay
tA
1.7
ns
RMS Aperture Jitter
jA
200
fs
Input Clock to Data Propagation Delay
tPID
3.5
Data Hold Time
tPH
-300
Output Clock to Data Propagation Delay
6.5
ns
ps
tPCD
2.8
L
28
cycles
tOVR
1
cycle
Latency (Pipeline Delay)
Overvoltage Recovery
5.0
3.7
ns
Thermal Impedance
PARAMETER
SYMBOL
TYP
UNIT
JP
30
°C/W
Junction to Paddle (Note 1)
NOTE:
1. Paddle soldered to ground plane.
ESD
Electrostatic charge accumulates on humans, tools and
equipment and may discharge through any metallic package
contacts (pins, balls, exposed paddle, etc.) of an integrated
circuit. Industry-standard protection techniques have been
utilized in the design of this product. However, reasonable
care must be taken in the storage and handling of ESD
sensitive products. Contact Intersil for the specific ESD
sensitivity rating of this product.
6
FN6814.0
December 5, 2008
KAD2710C
Pin Descriptions
PIN NUMBER
NAME
1, 14, 18, 20
AVDD2
2, 7, 10, 19, 21, 24
AVSS
Analog Supply Return
3
VREF
Reference Voltage Out/In
4
VREFSEL
5
VCM
6, 15, 16, 25
AVDD3
3.3V Analog Supply
8, 9
INP, INN
Analog Input Positive, Negative
11-13, 29-33, 35, 37, 39, 42, 46, 48, 50,
52, 54, 56, 58, 62, 63, 67
DNC
17
CLKDIV
22, 23
CLKN, CLKP
26, 45, 61
OVSS
Output Supply Return
27, 41, 44, 60
OVDD2
1.8V LVCMOS Supply
28
RST
Power On Reset (Active Low)
34
D0
LVCMOS Bit 0 (LSB) Output
36
D1
LVCMOS Bit 1 Output
38
D2
LVCMOS Bit 2 Output
40
D3
LVCMOS Bit 3 Output
43
CLKOUT
LVCMOS Clock Output
47
D4
LVCMOS Bit 4 Output
49
D5
LVCMOS Bit 5 Output
51
D6
LVCMOS Bit 6 Output
53
D7
LVCMOS Bit 7 Output
55
D8
LVCMOS Bit 8 Output
57
D9
LVCMOS Bit 9 (MSB) Output
59
OR
Over-Range
64-66
FUNCTION
1.8V Analog Supply
Reference Voltage Select (0:Int 1:Ext)
Common-Mode Voltage Output
Do Not Connect
Clock Divide by Two (Active Low)
Clock Input Complement, True
Connect to OVDD2
68
2SC
Exposed Paddle
AVSS
7
Two’s Complement Select (Active Low)
Analog Supply Return
FN6814.0
December 5, 2008
KAD2710C
Pinout
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
2SC
DNC
OVDD2
OVDD2
OVDD2
DNC
DNC
OVSS
OVDD2
OR
DNC
D9
DNC
D8
DNC
D7
DNC
KAD2710C
(68 LD QFN)
TOP VIEW
KAD2710C
68 QFN
Top View
Not to Scale
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
D6
DNC
D5
DNC
D4
DNC
OVSS
OVDD2
CLKOUT
DNC
OVDD2
D3
DNC
D2
DNC
D1
DNC
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
AVDD2
AVSS
AVDD2
AVSS
CLKN
CLKP
AVSS
AVDD3
OVSS
OVDD2
RST
DNC
DNC
DNC
DNC
DNC
D0
AVDD2
AVSS
VREF
VREFSEL
VCM
AVDD3
AVSS
INP
INN
AVSS
DNC
DNC
DNC
AVDD2
AVDD3
AVDD3
CLKDIV
FIGURE 2. PIN CONFIGURATION
8
FN6814.0
December 5, 2008
KAD2710C
Typical Performance Curves
AVDD2 = OVDD2 = 1.8V, AVDD3 = 3.3V, TA = +25°C, fSAMPLE = 275MSPS, fIN = 137MHz,
AIN = -0.5dBFS unless noted.
80
-50
-55
-60
SFDR
70
HD2, HD3 (dBc )
SNR(dBFS), SFDR(dBc)
75
65
60
SNR
-65
HD3
-70
-75
-80
HD2
-85
-90
55
-95
50
-100
0
50
100 150 200 250 300 350 400 450 500 550
fIN (MHz)
0
50
100
75
-40
70
-45
250 300 350 400 450 500 550
fIN (MHz)
HD3
-50
65
60
HD2, HD3 (dBc)
SNR(dBFS), SFDR(dBc)
200
FIGURE 4. HD2 AND HD3 vs fIN
FIGURE 3. SNR AND SFDR vs fIN
SNR
55
SFDR
50
-55
-60
HD2
-65
-70
-75
-80
45
-85
40
-30
-25
-20
-15
AIN (dBFS)
-10
-5
-90
-30
0
-25
FIGURE 5. SNR AND SFDR vs AIN
-15
A IN (dBFS)
-10
-5
0
-70
SFDR
-75
70
-80
HD2, HD3(dBc)
75
65
60
-20
FIGURE 6. HD2 AND HD3 vs AIN
80
SNR(dBFS), SFDR(dBc)
150
SNR
HD3
-85
HD2
-90
-95
55
-100
50
50
100
150
200
fSAMPLE (fS ) (MSPS)
250
FIGURE 7. SNR AND SFDR vs fSAMPLE
9
300
50
100
150
200
f SAMPLE (fS) (MSPS)
250
300
FIGURE 8. HD2 AND HD3 vs fSAMPLE
FN6814.0
December 5, 2008
KAD2710C
Typical Performance Curves
AVDD2 = OVDD2 = 1.8V, AVDD3 = 3.3V, TA = +25°C, fSAMPLE = 275MSPS, fIN = 137MHz,
AIN = -0.5dBFS unless noted. (Continued)
280
1
Power Dissipation (PD) (mW)
260
0.75
240
0.5
200
0.25
DNL (LSBs)
220
180
160
0
-0.25
140
-0.5
120
-0.75
100
50
100
150
200
250
300
-1
0
128
256
fSAMPLE (fS) (MSPS)
384
512
CODE
640
768
896
1023
FIGURE 10. DIFFERENTIAL NONLINEARITY vs OUTPUT CODE
FIGURE 9. POWER DISSIPATION vs fSAMPLE
1
INL (LSBs)
0.5
0
-0.5
-1
0
128
256
384
512
CODE
640
768
896
1023
FIGURE 11. INTEGRAL NONLINEARITY vs OUTPUT CODE
FIGURE 12. NOISE HISTOGRAM
0
0
Ai n = -0.49dBFS
A in = -0.49dBFS
-20
SNR = 56.5dBF S
-20
S NR = 56.5dBFS
SF DR = 71.0dBc
AMPLITUDE (dB)
AMPLITUDE (dB)
S FDR = 70.0dBc
-40
S INAD = 55.7dBc
HD2 = -94.3dBc
-60
HD3 = -70.5dBc
-80
-100
-120
0
-40
SINAD = 55.7dBc
HD 2 = -84.8dBc
-60
HD 3 = -71.0dBc
-80
-100
20
40
60
80
FREQUENCY (MHz)
100
FIGURE 13. OUTPUT SPECTRUM; fIN = 10MHz
10
120
-120
0
20
40
60
80
FREQUE NCY (MHz)
100
120
FIGURE 14. OUTPUT SPECTRUM; fIN = 134MHz
FN6814.0
December 5, 2008
KAD2710C
Typical Performance Curves
AVDD2 = OVDD2 = 1.8V, AVDD3 = 3.3V, TA = +25°C, fSAMPLE = 275MSPS, fIN = 137MHz,
AIN = -0.5dBFS unless noted. (Continued)
0
0
Ain = -0.50dBFS
-20
Ain = -7dBFS
SNR = 56.0dBFS
-20
-40
RELATIVE POWER (dB)
AMPLITUDE (dB)
SFD R = 63.6dBc
SINAD = 55.1dBc
HD2 = -67.8dBc
-60
HD3 = - 63.6dBc
-80
-120
0
-60
-80
20
40
60
80
FREQ UENCY (MHz)
100
-120
0
120
FIGURE 15. OUTPUT SPECTRUM; fIN = 300MHz
40
60
80
FREQUENCY (MHz)
100
120
0
Ain = -7dBFS
-20
IMD3 = -84.5dBFS
-40
Ain = -7dBFS
-20
2TSFDR = 74.7dBc
RELATIVE POWER (dB)
RELATIVE POWER (dB)
20
FIGURE 16. TWO-TONE SPECTRUM; fIN = 69MHz, 70MHz
0
-60
-80
-100
2TSFDR = 63dBc
IMD3 = -75dBFS
-40
-60
-80
-100
0
20
40
60
80
FREQUENCY (MHz)
100
-120
120
FIGURE 17. TWO-TONE SPECTRUM; fIN = 140MHz, 141MHz
0
20
40
60
80
FREQUENCY (MHz)
100
120
FIGURE 18. TWO-TONE SPECTRUM; fIN = 300MHz, 305MHz
75
800
70
700
SFDR
600
65
tCAL(ms)
SNR(dBFS), SFDR(dBc)
IMD3 = -78dBFS
-40
-100
-100
-120
2TSFDR = 71dBc
500
60
400
SNR
55
50
-40
300
-20
0
20
40
Ambient Temperature deg.C
FIGURE 19. SNR vs TEMPERATURE
11
60
80
200
100
125
150
175
200
f SAMPLE (f S ) (MSPS)
225
250
275
FIGURE 20. CALIBRATION TIME vs fS
FN6814.0
December 5, 2008
KAD2710C
Functional Description
Voltage Reference
The KAD2710 is a ten bit, 275MSPS A/D converter in a
pipelined architecture. The input voltage is captured by a
sample and hold circuit and converted to a unit of charge.
Proprietary charge-domain techniques are used to compare
the input to a series of reference charges. These
comparisons determine the digital code for each input value.
The converter pipeline requires 24 sample clocks to produce
a result. Digital error correction is also applied, resulting in a
total latency of 28 clock cycles. This is evident to the user as
a latency between the start of a conversion and the data
being available on the digital outputs.
The VREF pin is the reference voltage which sets the fullscale input voltage for the chip. This pin requires a bypass
capacitor of 0.1uF at a minimum. The internally generated
bandgap reference voltage is provided by an on-chip voltage
buffer.buffer can sink or source up to 50µA externally.
At power-up, a self-calibration is performed to minimize gain
and offset errors. The reset pin (RST) is held low internally at
power-up and will remain in that state until the calibration is
complete. The clock frequency should remain fixed during
this time.
Calibration accuracy is maintained for the sample rate at
which it is performed, and therefore should be repeated if the
clock frequency is changed by more than 10%. Recalibration
can be initiated via the RST pin, or power cycling, at any
time.
Reset
Recalibration of the ADC can be initiated at any time by
driving the RST pin low for a minimum of one clock cycle. An
open-drain driver is recommended.
The calibration sequence is initiated on the rising edge of
RST, as shown in Figure 21. The over-range output (OR) is
set high once RST is pulled low, and remains in that state
until calibration is complete. The OR output returns to
normal operation at that time, so it is important that the
analog input be within the converter’s full-scale range in
order to observe the transition. If the input is in an
over-range state the OR pin will stay high and it will not be
possible to detect the end of the calibration cycle.
While RST is low, the output clock (CLKOUT) stops toggling
and is set low. Normal operation of the output clock resumes
at the next input clock edge (CLKP/CLKN) after RST is
deasserted. At 275MSPS the nominal calibration time is
~240ms.
CLKN
CLKP
Calibration Time
RST
An external voltage may be applied to this pin to provide a
more accurate reference than the internally generated
bandgap voltage, or to match the full-scale reference for
multiple KAD2710C chips.One option in the latter
configuration is to use one KAD2710C's internally generated
reference as the external reference voltage for the other
chips in the system. Additionally, an externally provided
reference can be changed from the nominal value to adjust
the full-scale input voltage within a limited range.
To select whether the full-scale reference is internally
generated or externally provided, the digital input VREFSEL
is set low for internal, or high for external.This pin has
internal pull-up.use the internally generated reference
VREFSEL can be tied directly to AVSS, and to use an
external reference VREFSEL can be left unconnected.
Analog Input
The ADC core contains a fully differential input (INP/INN) to
the sample and hold circuit. The ideal full-scale input voltage
is 1.50V, centered at the VCM voltage of 0.86V as shown in
Figure 22.
V
1.8
1.4
0.75V
INN
INP
VCM
1.0
0.86V
0.6
-0.75V
0.2
t
FIGURE 22. ANALOG INPUT RANGE
Best performance is obtained when the analog inputs are
driven differentially. The common-mode output voltage,
VCM, should be used to properly bias the inputs as shown in
Figures 23 and 24. An RF transformer will give the best
noise and distortion performance for wideband and/or high
intermediate frequency (IF) inputs. Two different transformer
input schemes are shown in Figures 23 and 24.
Calibration Begins
ORP
Calibration Complete
CLKOUTP
FIGURE 21. CALIBRATION TIMING
12
FN6814.0
December 5, 2008
KAD2710C
0.01µF
Analog
In

50O
KAD2710
The recommended drive circuit is shown in Figure 26. The
clock can be driven single-ended, but this will reduce the
edge rate and may impact SNR performance.
VCM
ADT1-1WT

1kO

1kO
AVDD2
ADT1-1WT
0.1µF
CLKP
1nF
1nF
Clock
Input
FIGURE 23. TRANSFORMER INPUT FOR GENERAL
APPLICATIONS
200O

CLKN
TC4-1W
ADTL1-12
Analog
Input
FIGURE 26. RECOMMENDED CLOCK DRIVE
ADTL1-12
1nF
KAD2710
1nF
VCM
0.1µF
FIGURE 24. TRANSMISSION-LINE TRANSFORMER INPUT
FOR HIGH IF APPLICATIONS
A back-to-back transformer scheme is used to improve
common-mode rejection, which keeps the common-mode
level of the input matched to VCM. The value of the shunt
resistor should be determined based on the desired load
impedance.
The sample and hold circuit design uses a switched
capacitor input stage, which creates current spikes when the
sampling capacitance is reconnected to the input voltage.
This creates a disturbance at the input which must settle
before the next sampling point. Lower source impedance will
result in faster settling and improved performance. Therefore
a 1:1 transformer and low shunt resistance are
recommended for optimal performance.
A differential amplifier can be used in applications that
require dc coupling. In this configuration the amplifier will
typically determine the achievable SNR and distortion. A
typical differential amplifier circuit is shown in Figure 25.
TABLE 2. CLKDIV PIN SETTINGS
CLKDIV PIN
DIVIDE RATIO
AVSS
2
AVDD
1
CLKDIV is internally pulled low, so a pull-up resistor or logic
driver must be connected for undivided clock.
Jitter
In a sampled data system, clock jitter directly impacts the
achievable SNR performance. The theoretical relationship
between clock jitter (tJ) and SNR is shown in Equation 1 and
is illustrated in Figure 27.
1
SNR = 20 log 10  --------------------
 2f t 
(EQ. 1)
IN J
Where tJ is the RMS uncertainty in the sampling instant.

348O

69.8O
Use of the clock divider is optional. The KAD2710C's ADC
requires a clock with 50% duty cycle for optimum
performance. If such a clock is not available, one option is to
generate twice the desired sampling rate and use the
KAD2710C's divide-by-2 setting. This frequency divider uses
the rising edge of the clock, so 50% clock duty cycle is
assured. Table 2 describes the CLKDIV connection.

25O
10 0
100O

95
Analog
Input
217O

0.22µF
CM
tj=0.1p s
KAD2710
90

100O
85

25O

69.8O

348O
0.1µF
FIGURE 25. DIFFERENTIAL AMPLIFIER INPUT
SNR - dB
49.9O

1 4 Bits
VCM
80
tj=1 ps
1 2 Bits
75
70
tj=1 0p s
65
60
10 Bits
tj=10 0p s
55
Clock Input
50
The sample clock input circuit is a differential pair (see
Figure 29). Driving these inputs with a high level (up to
1.8VP-P on each input) sine or square wave will provide the
lowest jitter performance.
13
1
10
100
10 00
Input Frequency - MHz
FIGURE 27. SNR vs CLOCK JITTER
FN6814.0
December 5, 2008
KAD2710C
This relationship shows the SNR that would be achieved if
clock jitter were the only non-ideal factor. In reality,
achievable SNR is limited by internal factors such as
linearity, aperture jitter and thermal noise. Internal aperture
jitter is the uncertainty in the sampling instant shown in
Figure 1. The internal aperture jitter combines with the input
clock jitter in a root-sum-square fashion, since they are not
statistically correlated, and this determines the total jitter in
the system. The total jitter, combined with other noise
sources, then determines the achievable SNR.
Digital Outputs
Data is output on a parallel bus with LVCMOS drivers.
The output format (Binary or Two’s Complement) is selected
via the 2SC pin as shown in Table 3.
TABLE 3. 2SC PIN SETTINGS
2SC PIN
MODE
AVSS
Two’s Complement
AVDD (or unconnected)
Binary
Equivalent Circuits
AVDD2
AVDD3
INP
2pF

F1
Csamp
0.3pF

F2
To
Charge
Pipeline
AVDD2
To Clock
Generation
CLKP
AVDD3
INN
2pF

F1
Csamp
0.3pF

F2
To
Charge
Pipeline
AVDD2
CLKN
FIGURE 28. ANALOG INPUTS
FIGURE 29. CLOCK INPUTS
OVDD
OVDD
DATA
D[9:0]
FIGURE 30. LVCMOS OUTPUTS
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
14
FN6814.0
December 5, 2008
KAD2710C
Layout Considerations
Split Ground and Power Planes
Data converters operating at high sampling frequencies
require extra care in PC board layout. If analog and digital
ground planes are separate, analog supply and ground
planes should be laid out under signal and clock inputs and
digital planes under outputs and logic pins. Grounds should
be joined under the chip.
Clock Input Considerations
Use matched transmission lines to the inputs for the analog
input and clock signals. Locate transformers, drivers and
terminations as close to the chip as possible.
Bypass and Filtering
Bulk capacitors should have low equivalent series
resistance. Tantalum is recommended. Keep ceramic
bypass capacitors very close to device pins. Longer traces
will increase inductance, resulting in diminished dynamic
performance and accuracy. Make sure that connections to
ground are direct, and low impedance.
LVCMOS Outputs
Output traces and connections must be designed for 50
characteristic impedance. Keep trace lengths equal, and
minimize bends where possible. Avoid crossing ground and
power-plane breaks with signal traces.
Unused Inputs
The RST and 2SC inputs are internally pulled up, and can be
left open-circuit if not used.
CLKDIV is internally pulled low, which divides the input clock
by two.
VREFSEL must be held low for internal reference, but can
be left open for external reference.
Definitions
Analog Input Bandwidth is the analog input frequency at
which the spectral output power at the fundamental
frequency (as determined by FFT analysis) is reduced by
3dB from its full-scale low-frequency value. This is also
referred to as Full Power Bandwidth.
Aperture Delay or Sampling Delay is the time required
after the rise of the clock input for the sampling switch to
open, at which time the signal is held for conversion.
Aperture Jitter is the RMS variation in aperture delay for a
set of samples.
Clock Duty Cycle is the ratio of the time the clock wave is at
logic high to the total time of one clock period.
Differential Non-Linearity (DNL) is the deviation of any
code width from an ideal 1 LSB step.
15
Effective Number of Bits (ENOB) is an alternate method of
specifying Signal to Noise-and-Distortion Ratio (SINAD). In
dB, it is calculated as: ENOB = (SINAD - 1.76)/6.02
Gain Error is the ratio of the difference between the voltages
that cause the lowest and highest code transitions to the
full-scale voltage (less 2 LSB). It is typically expressed in
percent.
Integral Non-Linearity (INL) is the deviation of each
individual code from a line drawn from negative full-scale
(1/2 LSB below the first code transition) through positive
full-scale (1/2 LSB above the last code transition). The
deviation of any given code from this line is measured from
the center of that code.
Least Significant Bit (LSB) is the bit that has the smallest
value or weight in a digital word. Its value in terms of input
voltage is VFS/(2N - 1) where N is the resolution in bits.
Missing Codes are output codes that are skipped and will
never appear at the ADC output. These codes cannot be
reached with any input value.
Most Significant Bit (MSB) is the bit that has the largest
value or weight.
Pipeline Delay is the number of clock cycles between the
initiation of a conversion and the appearance at the output
pins of the data.
Power Supply Rejection Ratio (PSRR) is the ratio of a
change in input voltage necessary to correct a change in
output code that results from a change in power supply
voltage.
Signal to Noise-and-Distortion (SINAD) is the ratio of the
RMS signal amplitude to the RMS sum of all other spectral
components below one half the clock frequency, including
harmonics but excluding DC.
Signal-to-Noise Ratio (SNR) (without Harmonics) is the
ratio of the RMS signal amplitude to the RMS sum of all
other spectral components below one-half the sampling
frequency, excluding harmonics and DC.
SNR and SINAD are either given in units of dBc (dB to
carrier) when the power level of the fundamental is used as
the reference, or dBFS (dB to full scale) when the
converter’s full-scale input power is used as the reference.
Spurious-Free-Dynamic Range (SFDR) is the ratio of the
RMS signal amplitude to the RMS value of the peak spurious
spectral component. The peak spurious spectral component
may or may not be a harmonic.
Two-Tone SFDR is the ratio of the RMS value of the lowest
power input tone to the RMS value of the peak spurious
component, which may or may not be an IMD product.
FN6814.0
December 5, 2008
KAD2710C
Package Outline Drawing
L68.10x10B
68 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 11/08
PIN 1
INDEX AREA
6
10.00
A
4X 8.00
B
52
PIN 1
INDEX AREA
6
68
51
1
35
17
64X 0.50
Exp. DAP
7.70 Sq.
10.00
0.15 (4X)
34
18
68X 0.55
TOP VIEW
68X 0.25
4
0.10 M C A B
BOTTOM VIEW
SEE DETAIL "X"
0.90 Max
8.00 Sq
0.10 C
C
0.08 C
SEATING PLANE
64X 0.50
SIDE VIEW
68X 0.25
9.65 Sq
C
7.70 Sq
0 . 2 REF
5
0 . 00 MIN.
0 . 05 MAX.
68X 0.75
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSEY14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
16
FN6814.0
December 5, 2008
Similar pages