DATASHEET

High Performance Dual 14-Bit, 125MSPS ADC
ISLA224P12
Features
The ISLA224P12 is a high performance dual 14-bit 125MSPS
analog-to-digital converter offering very high dynamic range and
low power consumption. It carries the export control
classification number 3A991.c.3 and can be exported without a
license to most countries, including China and Russia. It is part of
a pin-compatible family of 12- to 16-bit A/Ds with maximum
sample rates ranging from 125 to 500MSPS. This allows a design
using the ISLA224P12 to accommodate any of the other
pin-compatible A/Ds with minimal changes.
• License-free Import for most countries including China and
Russia (ECCN 3A991.c.3)
The ISLA224P12 is very flexible and can be designed into a wide
variety of systems. A serial peripheral interface (SPI) port allows
access to its extensive configurability as well as provides digital
control over various analog parameters such as input gain and
offset. Digital output data is presented in selectable LVDS or
CMOS formats in half-width, double data rate (DDR). Operating
from a 1.8V supply, performance is specified over the full
industrial temperature range (-40°C to +85°C).
• Programmable Built-in Test Patterns
Applications
• SNR @ 125MSPS
• Software Defined Radio
• High Performance Data Acquisition
CLKOUTP
CLOCK
MANAGEMENT
VREF
VCM
14-BIT
125 MSPS
ADC
VREF
+
1.25V
–
RESETN
AVSS
August 17, 2012
FN7983.3
NAPSLP
SHA
VINAP
D[13:0]P
D[13:0]N
DIGITAL
ERROR
CORRECTION
1
ORP
ORN
MODEL
RESOLUTION
SPEED
(MSPS)
ISLA224P25
14
250
ISLA224P20
14
200
ISLA224P13
14
130
ISLA222P25
12
250
ISLA222P20
12
200
ISLA222P13
12
130
OUTFMT
OUTMODE
SPI
CONTROL
CSB
SCLK
SDIO
SDO
VINAN
CLKOUTN
14-BIT
125 MSPS
ADC
SHA
Key Specifications
OVSS
VINBP
• Data Output Clock
Pin-Compatible Family
OVDD
CLKDIVRSTN
CLKDIVRSTP
AVDD
CLKDIV
• Communications Test Equipment
VINBN
• DDR LVDS-Compatible or LVCMOS Outputs
- 86dBc fIN = 30MHz
- 79dBc fIN = 363MHz
• Total Power Consumption = 590mW
• Broadband Communications
CLKN
• Nap and Sleep Modes
- 74.7dBFS fIN= 30MHz
- 70.2dBFS fIN = 363MHz
• SFDR @ 125MSPS
• Radar Array Processing
CLKP
• Multi-ADC Support
- SPI Programmable Fine Gain and Offset Control
- Multiple ADC Synchronization
- Optimized Output Timing
• Clock Duty Cycle Stabilizer
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2012. All Rights Reserved
Intersil (and design) and FemtoCharge are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISLA224P12
Pin Configuration- LVDS Mode
AVDD
AVDD
AVDD
SDIO
SCLK
CSB
SDO
OVSS
ORP
ORN
OVDD
OVSS
D0P
D0N
D1P
D1N
D2P
D2N
ISLA224P12
(72 LD QFN)
TOP VIEW
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
DNC
1
54 D3P
DNC
2
53 D3N
NAPSLP
3
52 D4P
VCM
4
51 D4N
AVSS
5
50 D5P
VINBP
6
49 D5N
VINBN
7
48 CLKOUTP
AVSS
8
47 CLKOUTN
AVDD
9
46 RLVDS
AVDD
10
45 OVSS
AVSS
11
44 D6P
VINAN
12
43 D6N
VINAP
13
42 D7P
AVSS
14
41 D7N
CLKDIV
15
40 D8P
DNC
16
38 D9P
Connect Thermal Pad to AVSS
18
30
31
32
D12P
OVDD
33
34
35
36
D10P
29
D10N
28
D11P
27
D11N
26
D12N
CLKN
25
D13P
CLKP
24
D13N
23
OVDD
22
OVSS
21
CLKDIVRSTN
20
CLKDIVRSTP
19
AVDD
37 D9N
AVDD
RESETN
17
AVDD
DNC
39 D8N
Thermal Pad Not Drawn to Scale.
Consult Mechanical Drawing for
Physical Dimensions.
Pin Descriptions - 72 Ld QFN, LVDS Mode
PIN NUMBER
LVDS PIN NAME
LVDS PIN FUNCTION
1, 2, 16, 17
DNC
Do Not Connect
9, 10, 19, 20, 21, 70, 71, 72
AVDD
1.8V Analog Supply
5, 8, 11, 14
AVSS
Analog Ground
27, 32, 62
OVDD
1.8V Output Supply
26, 45, 61, 65
OVSS
Output Ground
3
NAPSLP
4
VCM
6, 7
VINBP, VINBN
2
Tri-Level Power Control (Nap, Sleep modes)
Common Mode Output
Channel B Analog Input Positive, Negative
FN7983.3
August 17, 2012
ISLA224P12
Pin Descriptions - 72 Ld QFN, LVDS Mode
(Continued)
PIN NUMBER
LVDS PIN NAME
LVDS PIN FUNCTION
12, 13
VINAN, VINAP
15
CLKDIV
Tri-Level Clock Divider Control
18
RESETN
Power On Reset (Active Low)
22, 23
CLKP, CLKN
Channel A Analog Input Negative, Positive
Clock Input True, Complement
24, 25
CLKDIVRSTP, CLKDIVRSTN
28, 29
D13N, D13P
LVDS Bit 13 (MSB) Output Complement, True
30, 31
D12N, D12P
LVDS Bit 12 Output Complement, True
33, 34
D11N, D11P
LVDS Bit 11 Output Complement, True
35, 36
D10N, D10P
LVDS Bit 10 Output Complement, True
37, 38
D9N, D9P
LVDS Bit 9 Output Complement, True
39, 40
D8N, D8P
LVDS Bit 8 Output Complement, True
41, 42
D7N, D7P
LVDS Bit 7 Output Complement, True
43, 44
D6N, D6P
LVDS Bit 6 Output Complement, True
46
RLVDS
47, 48
CLKOUTN, CLKOUTP
LVDS Clock Output Complement, True
49, 50
D5N, D5P
LVDS Bit 5 Output Complement, True
51, 52
D4N, D4P
LVDS Bit 4 Output Complement, True
53, 54
D3N, D3P
LVDS Bit 3 Output Complement, True
55, 56
D2N, D2P
LVDS Bit 2 Output Complement, True
57, 58
D1N, D1P
LVDS Bit 1 Output Complement, True
59, 60
D0N, D0P
LVDS Bit 0 (LSB) Output Complement, True
63, 64
ORN, ORP
LVDS Over Range Complement, True
66
SDO
SPI Serial Data Output
67
CSB
SPI Chip Select (active low)
68
SCLK
SPI Clock
69
SDIO
SPI Serial Data Input/Output
Exposed Paddle
AVSS
Analog Ground
3
Synchronous Clock Divider Reset True, Complement
LVDS Bias Resistor (connect to OVSS with 1%10kΩ)
FN7983.3
August 17, 2012
ISLA224P12
Pin Configuration- CMOS Mode
AVDD
AVDD
AVDD
SDIO
SCLK
CSB
SDO
OVSS
OR
DNC
OVDD
OVSS
D0
DNC
D1
DNC
D2
DNC
ISLA224P12
(72 LD QFN)
TOP VIEW
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
DNC
1
54 D3
DNC
2
53 DNC
NAPSLP
3
52 D4
VCM
4
51 DNC
AVSS
5
50 D5
VINBP
6
49 DNC
VINBN
7
48 CLKOUT
AVSS
8
47 DNC
AVDD
9
46 RLVDS
AVDD
10
45 OVSS
AVSS
11
44 D6
VINAN
12
43 DNC
VINAP
13
42 D7
AVSS
14
41 DNC
CLKDIV
15
40 D8
DNC
16
38 D9
Connect Thermal Pad to AVSS
18
26
27
28
29
30
31
32
33
34
35
36
DNC
D12
OVDD
DNC
D11
DNC
D10
CLKN
25
D13
CLKP
24
DNC
23
OVDD
22
OVSS
21
CLKDIVRSTN
20
CLKDIVRSTP
19
AVDD
37 DNC
AVDD
RESETN
17
AVDD
DNC
39 DNC
Thermal Pad Not Drawn to Scale.
Consult Mechanical Drawing for
Physical Dimensions.
Pin Descriptions - 72 Ld QFN, CMOS Mode
PIN NUMBER
CMOS PIN NAME
1, 2, 16, 17, 28, 30, 33, 35, 37,
39, 41, 43, 47, 49, 51, 53, 55,
57, 59, 63
DNC
Do Not Connect
9, 10, 19, 20, 21, 70, 71, 72
AVDD
1.8V Analog Supply
5, 8, 11, 14
AVSS
Analog Ground
27, 32, 62
OVDD
1.8V Output Supply
26, 45, 61, 65
OVSS
Output Ground
3
NAPSLP
4
VCM
4
CMOS PIN FUNCTION
Tri-Level Power Control (Nap, Sleep modes)
Common Mode Output
FN7983.3
August 17, 2012
ISLA224P12
Pin Descriptions - 72 Ld QFN, CMOS Mode
(Continued)
PIN NUMBER
CMOS PIN NAME
CMOS PIN FUNCTION
6, 7
VINBP, VINBN
Channel B Analog Input Positive, Negative
12, 13
VINAN, VINAP
Channel A Analog Input Negative, Positive
15
CLKDIV
Tri-Level Clock Divider Control
18
RESETN
Power On Reset (Active Low)
22, 23
CLKP, CLKN
24, 25
CLKDIVRSTP, CLKDIVRSTN
Clock Input True, Complement
29
D13
CMOS Bit 13 (MSB) Output
31
D12
CMOS Bit 12 Output
34
D11
CMOS Bit 11 Output
36
D10
CMOS Bit 10 Output
38
D9
CMOS Bit 9 Output
40
D8
CMOS Bit 8 Output
42
D7
CMOS Bit 7 Output
44
D6
CMOS Bit 6 Output
46
RLVDS
LVDS Bias Resistor (connect to OVSS with 1%10kΩ)
48
CLKOUT
CMOS Clock Output
50
D5
CMOS Bit 5 Output
52
D4
CMOS Bit 4 Output
54
D3
CMOS Bit 3 Output
56
D2
CMOS Bit 2 Output
Synchronous Clock Divider Reset True, Complement
58
D1
CMOS Bit 1 Output
60
D0
CMOS Bit 0 (LSB) Output
64
OR
CMOS Over Range
66
SDO
SPI Serial Data Output
67
CSB
SPI Chip Select (active low)
68
SCLK
SPI Clock
69
SDIO
SPI Serial Data Input/Output
Exposed Paddle
AVSS
Analog Ground
Ordering Information
PART NUMBER
(Notes 1, 2)
PART
MARKING
TEMP. RANGE
(°C)
-40°C to +85°C
PACKAGE
(Pb-free)
ISLA224P12IRZ
ISLA224P12 IRZ
72 Ld QFN
ISLA224IR72EV1Z
Evaluation Board - Supports 125/130/200/250 Speed Grades
KMB-001LEVALZ
LVDS Motherboard (Interfaces with ISLA224IR72EV1Z operating in LVDS Output Mode)
KMB-001CEVALZ
CMOS Motherboard (Interfaces with ISLA224IR72EV1Z operating in CMOS Output Mode)
PKG.
DWG. #
L72.10x10E
NOTES:
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate-e4
termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. For Moisture Sensitivity Level (MSL), please see device information page for ISLA224P12. For more information on MSL please see techbrief TB363.
5
FN7983.3
August 17, 2012
ISLA224P12
Table of Contents
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Digital Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Switching Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Typical Performance Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power-On Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
User Initiated Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Temperature Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Over-Range Indicator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Nap/Sleep. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Clock Divider Synchronous Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
SPI Physical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
SPI Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Device Configuration/Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Global Device Configuration/Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
SPI Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Equivalent Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
A/D Evaluation Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Split Ground and Power Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Clock Input Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Exposed Paddle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Bypass and Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
LVDS Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
LVCMOS Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Unused Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6
FN7983.3
August 17, 2012
ISLA224P12
Absolute Maximum Ratings
Thermal Information
AVDD to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.4V to 2.1V
OVDD to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.4V to 2.1V
AVSS to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V
Analog Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V
Clock Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V
Logic Input to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V
Logic Inputs to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V
Latchup (Tested per JESD-78C; Class 2, Level A) . . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
72 Ld QFN (Notes 3, 4) . . . . . . . . . . . . . . . .
23
0.9
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
3. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
4. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V,
TA = -40°C to +85°C (typical specifications at +25°C), AIN = -1dBFS, fSAMPLE = 125MSPS. Boldface limits apply over the operating temperature range,
-40°C to +85°C.
ISLA224P12
PARAMETER
SYMBOL
CONDITIONS
MIN
(Note 5)
TYP
MAX
(Note 5)
UNITS
1.95
2.0
2.2
VP-P
DC SPECIFICATIONS (Note 6)
Analog Input
Full-Scale Analog Input Range
VFS
Differential
Input Resistance
RIN
Differential
600
Ω
Input Capacitance
CIN
Differential
4.5
pF
Full Temp
75
ppm/°C
Full Scale Range Temp. Drift
AVTC
Input Offset Voltage
VOS
Common-Mode Output Voltage
VCM
0.94
V
Common-Mode Input Current
(per pin)
ICM
2.6
µA/MSPS
Inputs Common Mode Voltage
0.9
V
CLKP,CLKN Input Swing
1.8
V
-5.0
-1.7
5.0
mV
Clock Inputs
Power Requirements
1.8V Analog Supply Voltage
AVDD
1.7
1.8
1.9
V
1.8V Digital Supply Voltage
OVDD
1.7
1.8
1.9
V
1.8V Analog Supply Current
IAVDD
293
312
mA
1.8V Digital Supply Current (Note 6)
IOVDD
3mA LVDS
75
83
mA
Power Supply Rejection Ratio
PSRR
30MHz, 50mVP-P signal on AVDD
-65
dB
CMOS
590
mW
2mA LVDS
640
mW
3mA LVDS
662
711
mW
77
85
mW
6
10
mW
Total Power Dissipation
Normal Mode
PD
Nap Mode
PD
Sleep Mode
PD
7
CSB at logic high
FN7983.3
August 17, 2012
ISLA224P12
Electrical Specifications
All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V,
TA = -40°C to +85°C (typical specifications at +25°C), AIN = -1dBFS, fSAMPLE = 125MSPS. Boldface limits apply over the operating temperature range,
-40°C to +85°C. (Continued)
ISLA224P12
PARAMETER
SYMBOL
Nap/Sleep Mode Wakeup Time
CONDITIONS
MIN
(Note 5)
TYP
MAX
(Note 5)
UNITS
Sample Clock Running
630
µs
AC SPECIFICATIONS
Differential Nonlinearity
DNL
fIN = 105MHz
±0.4
LSB
Integral Nonlinearity
INL
fIN = 105MHz
±3.0
LSB
Minimum Conversion Rate (Note 7)
fS MIN
Maximum Conversion Rate
fS MAX
Signal-to-Noise Ratio
(Note 8)
SNR
40
125
fIN = 30MHz
SINAD
dBFS
74.3
dBFS
fIN = 190MHz
72.9
dBFS
fIN = 363MHz
70.2
dBFS
fIN = 461MHz
68.8
dBFS
fIN = 605MHz
68.0
dBFS
fIN = 30MHz
74.2
dBFS
72.8
dBFS
fIN = 190MHz
71.4
dBFS
fIN = 363MHz
69.5
dBFS
fIN = 461MHz
65.7
dBFS
fIN = 605MHz
60.3
dBFS
fIN = 30MHz
12.03
Bits
11.80
Bits
fIN = 190MHz
11.57
Bits
fIN = 363MHz
11.25
Bits
fIN = 461MHz
10.62
Bits
fIN = 605MHz
9.72
Bits
fIN = 30MHz
86
dBc
79
dBc
fIN = 190MHz
76
dBc
fIN = 363MHz
79
dBc
fIN = 461MHz
70
dBc
fIN = 605MHz
62
dBc
fIN = 30MHz
99
dBc
fIN = 105MHz
96
dBc
fIN = 190MHz
92
dBc
fIN = 363MHz
89
dBc
fIN = 461MHz
87
dBc
fIN = 605MHz
83
dBc
fIN = 105MHz
Effective Number of Bits
(Note 8)
ENOB
fIN = 105MHz
Spurious-Free Dynamic Range
(Note 8)
SFDR
fIN = 105MHz
SFDRX23
Spurious-Free Dynamic Range
Excluding H2, H3
(Note 8)
8
MSPS
74.7
fIN = 105MHz
Signal-to-Noise and Distortion
(Note 8)
MSPS
72.7
70.0
11.34
71
FN7983.3
August 17, 2012
ISLA224P12
Electrical Specifications
All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V,
TA = -40°C to +85°C (typical specifications at +25°C), AIN = -1dBFS, fSAMPLE = 125MSPS. Boldface limits apply over the operating temperature range,
-40°C to +85°C. (Continued)
ISLA224P12
PARAMETER
SYMBOL
Intermodulation Distortion
IMD
Channel-to-Channel Isolation
MIN
(Note 5)
CONDITIONS
TYP
MAX
(Note 5)
UNITS
fIN = 70MHz
-84
dBFS
fIN = 170MHz
-107
dBFS
fIN = 10MHz
100
dBFS
fIN = 121MHz
97
dBFS
Word Error Rate
WER
10-12
Full Power Bandwidth
FPBW
700
MHz
NOTES:
5. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
6. Digital Supply Current is dependent upon the capacitive loading of the digital outputs. IOVDD specifications apply for 10pF load on each digital output.
7. The DLL Range setting must be changed for low-speed operation.
8. Minimum specification guaranteed when calibrated at +85°C.
Digital Specifications
Boldface limits apply over the operating temperature range, -40°C to +85°C.
PARAMETER
SYMBOL
CONDITIONS
MIN
(Note 5)
TYP
MAX
(Note 5) UNITS
0
1
10
µA
-25
-12
-7
µA
4
12
µA
-415
-300
µA
INPUTS
Input Current High (RESETN)
IIH
VIN = 1.8V
Input Current Low (RESETN)
IIL
VIN = 0V
Input Current High (SDIO)
IIH
VIN = 1.8V
Input Current Low (SDIO)
IIL
VIN = 0V
Input Voltage High (SDIO, RESETN)
VIH
Input Voltage Low (SDIO, RESETN)
VIL
Input Current High (CLKDIV) (Note 9)
IIH
16
Input Current Low (CLKDIV)
IIL
-34
Input Capacitance
CDI
9
-600
1.17
V
0.63
V
25
34
µA
-25
-16
µA
3
pF
FN7983.3
August 17, 2012
ISLA224P12
Digital Specifications
Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
SYMBOL
CONDITIONS
MIN
(Note 5)
TYP
MAX
(Note 5) UNITS
LVDS INPUTS (CLKDIVRSTP, CLKDIVRSTN)
Input Common Mode Range
VICM
825
1575
mV
Input Differential Swing (Peak-to-peak, Single-ended)
VID
250
450
mV
CLKDIVRSTP Input Pull-down Resistance
RIpd
100
kΩ
CLKDIVRSTN Input Pull-up Resistance
RIpu
100
kΩ
612
mVP-P
LVDS OUTPUTS
Differential Output Voltage (Note 10)
Output Offset Voltage
VT
3mA Mode
VOS
3mA Mode
1120
1150
1200
mV
Output Rise Time
tR
240
ps
Output Fall Time
tF
240
ps
OVDD - 0.1
V
CMOS OUTPUTS
Voltage Output High
VOH
IOH = -500µA
Voltage Output Low
VOL
IOL = 1mA
OVDD - 0.3
0.1
0.3
V
Output Rise Time
tR
1.8
ns
Output Fall Time
tF
1.4
ns
NOTES:
9. The Tri-Level Inputs internal switching thresholds are approximately. 0.43V and 1.34V. It is advised to float the inputs, tie to ground or AVDD depending
on desired function.
10. The voltage is expressed in peak-to-peak differential swing. The peak-to-peak singled-ended swing is 1/2 of the differential swing.
Timing Diagrams
INP
INN
tA
CLKN
CLKP
LATENCY = L CYCLES
tCPD
CLKOUTN
CLKOUTP
tDC
tPD
D[13:0]N
D[13:0]P
A DATA
N-L
B DATA
N-L
A DATA
N-L+1
B DATA
N-L+1
B DATA
N-1
A DATA
N
B DATA
N
FIGURE 3. LVDS
10
FN7983.3
August 17, 2012
ISLA224P12
Timing Diagrams (Continued)
INP
INN
tA
CLKN
CLKP
LATENCY = L CYCLES
tCPD
CLKOUT
tDC
tPD
A DATA
N-L
D[13:0]
B DATA
N-L
A DATA
N-L+1
B DATA
N-L+1
B DATA
N-1
A DATA
N
B DATA
N
FIGURE 4. CMOS
Switching Specifications
PARAMETER
Boldface limits apply over the operating temperature range, -40°C to +85°C.
SYMBOL
CONDITION
MIN
(Note 5)
TYP
MAX
(Note 5)
UNITS
ADC OUTPUT
Aperture Delay
tA
114
ps
RMS Aperture Jitter
jA
75
fs
Input Clock to Output Clock Propagation
Delay
Relative Input Clock to Output Clock
Propagation Delay (Note 13)
tCPD
AVDD, OVDD = 1.7V to 1.9V,
TA = -40°C to +85°C
1.65
2.4
3
ns
tCPD
AVDD, OVDD = 1.8V, TA = +25°C
1.9
2.3
2.75
ns
dtCPD
AVDD, OVDD = 1.7V to 1.9V,
TA = -40°C to +85°C
-450
450
ps
Input Clock to Data Propagation Delay
tPD
Output Clock to Data Propagation Delay,
LVDS Mode
tDC
Output Clock to Data Propagation Delay,
CMOS Mode
tDC
Synchronous Clock Divider Reset Setup
Time (with Respect to the Positive Edge of
CLKP)
tRSTS
Synchronous Clock Divider Reset Hold Time
(with Respect to the Positive Edge of CLKP)
tRSTH
Synchronous Clock Divider Reset Recovery
Time
tRSTRT
Latency (Pipeline Delay)
L
11
1.65
2.4
3.5
ns
Rising/Falling Edge
-0.1
0.16
0.5
ns
Rising/Falling Edge
-0.1
0.2
0.65
ns
0.4
0.06
0.02
DLL recovery time after
Synchronous Reset
ns
0.35
ns
52
µs
10
cycles
FN7983.3
August 17, 2012
ISLA224P12
Switching Specifications
Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
SYMBOL
Overvoltage Recovery
MIN
(Note 5)
CONDITION
MAX
(Note 5)
TYP
tOVR
UNITS
1
cycles
SPI INTERFACE (Notes 11, 12)
t
SCLK Period
CLK
Write Operation
16
cycles
tCLK
Read Operation
16
cycles
CSB↓ to SCLK↑ Setup Time
tS
Read or Write
28
cycles
CSB↑ after SCLK↑ Hold Time
tH
Write
5
cycles
CSB↑ after SCLK↓ Hold Time
tHR
Read
16
cycles
Data Valid to SCLK↑ Setup Time
tDS
Write
6
cycles
Data Valid after SCLK↑ Hold Time
tDH
Read or Write
4
cycles
Data Valid after SCLK↓ Time
tDVR
Read
5
cycles
NOTES:
11. SPI Interface timing is directly proportional to the ADC sample period (tS). Values above reflect multiples of a 16ns sample period, and must be scaled
proportionally for lower sample rates. ADC sample clock must be running for SPI communication.
12. The SPI may operate asynchronously with respect to the ADC sample clock.
13. The relative propagation delay is the difference in propagation time between any two devices that are matched in temperature and voltage, and is
specified over the full operating temperature and voltage range.
Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C, AIN = -1dBFS,
fIN = 105MHz, fSAMPLE = 125MSPS.
HD2 AND HD3 MAGNITUDE (dBc)
SNR (dBFS) AND SFDR (dBc)
90
85
SFDR
80
75
70
SNR
65
60
0
100
200
300
400
500
600
-60
-65
-70
HD3
-75
-80
-85
HD2
-90
-95
-100
-105
0
100
INPUT FREQUENCY (MHz)
100
-40
SNR (dBfs)
SFDR (dBfs)
SNR AND SFDR
SNR AND SFDR
400
500
600
-30
110
80
70
60
50
SFDR (dBc)
40
SNR (dBc)
30
HD2 (dBc)
-50
-60
-70
HD3 (dBc)
-80
-90
HD2 (dBfs)
HD3 (dBfs)
-100
20
10
-60
300
FIGURE 6. HD2 AND HD3 vs fIN
FIGURE 5. SNR AND SFDR vs fIN
90
200
INPUT FREQUENCY (MHz)
-50
-40
-30
-20
-10
INPUT AMPLITUDE (dBFS)
FIGURE 7. SNR AND SFDR vs AIN
12
0
-110
-60
-50
-40
-30
-20
-10
INPUT AMPLITUDE (dBFS)
0
FIGURE 8. HD2 AND HD3 vs AIN
FN7983.3
August 17, 2012
ISLA224P12
Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C, AIN = -1dBFS,
fIN = 105MHz, fSAMPLE = 125MSPS. (Continued)
HD2 AND HD3 MAGNITUDE (dBc)
SNR (dBFS) AND SFDR (dBC)
90
85
80
SFDR
75
SNR
70
40
60
80
100
SAMPLE RATE (MSPS)
120
-75
-80
H3
-85
-90
-95
H2
-100
-105
40
50
60
70
80
90
100
110
120
SAMPLE RATE (MSPS)
FIGURE 9. SNR AND SFDR vs fSAMPLE
FIGURE 10. HD2 AND HD3 vs fSAMPLE
1.0
675
0.8
0.6
DNL (LSBs)
TOTAL POWER (mW)
625
575
LVDS
525
0.4
0.2
0
-0.2
-0.4
-0.6
475
-0.8
CMOS
425
40
60
80
100
-1.0
0
120
2000 4000 6000 8000 10000 12000 14000 16000
SAMPLE RATE (MSPS)
CODES
FIGURE 11. POWER vs fSAMPLE IN 3mA LVDS AND CMOS MODES
FIGURE 12. DIFFERENTIAL NONLINEARITY
80
SNR (dBFS) AND SFDR (dBc)
4
3
INL (LSBs)
2
1
0
-1
-2
-3
-4
0
2000 4000 6000 8000 10000 12000 14000 16000
CODES
FIGURE 13. INTEGRAL NONLINEARITY
13
78
76
74
72
70
68
66
64
62
60
0.75
0.85
0.95
1.05
1.15
INPUT COMMON MODE (V)
FIGURE 14. SNR AND SFDR vs VCM
FN7983.3
August 17, 2012
ISLA224P12
Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C, AIN = -1dBFS,
fIN = 105MHz, fSAMPLE = 125MSPS. (Continued)
90000
70000
65410
60000
50000
40000
32221
30000
19239
20000
0
10
20
30
40
FREQUENCY (MHz)
50
60
0
AIN = -1.0 dBFS
-20 SNR = 73.2 dBFS
SFDR = 78.2 dBc
-40 SINAD = 71.6 dBFS
AIN = -1.1 dBFS
SNR = 70.2 dBFS
SFDR = 77.1 dBc
SINAD = 69.4 dBFS
-20
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
-80
FIGURE 16. SINGLE-TONE SPECTRUM @ 105MHz
0
-60
-80
-100
-40
-60
-80
-100
0
10
20
30
40
FREQUENCY (MHz)
50
-120
60
FIGURE 17. SINGLE-TONE SPECTRUM @ 190MHz
0
10
20
30
40
FREQUENCY (MHz)
50
60
FIGURE 18. SINGLE-TONE SPECTRUM @ 363MHz
0
0
IMD2
IMD3
2nd HARMONICS
3rd HARMONICS
-20
-40
AMPLITUDE(dBFS)
AMPLITUDE (dBFS)
-60
-120
FIGURE 15. NOISE HISTOGRAM
-60
IMD3 =-84dBFS
-80
-100
-120
-40
-100
4046
2046
207 6 1
0
0 102
0
8165 8166 8167 8168 8169 8170 8171 8172 8173 8174 8175 8176
CODE
10000
-120
AIN = -1.0 dBFS
SNR = 74.7 dBFS
SFDR = 79.0 dBc
SINAD = 73.4 dBFS
-20
AMPLITUDE (dBFS)
NUMBER OF HITS
0
STDEV = 0.97 LSB
76722
80000
IMD2
IMD3
2nd HARMONICS
3rd HARMONICS
-20
-40
-60
IMD3 =-107dBFS
-80
-100
0
10
20
30
40
FREQUENCY (MHz)
50
FIGURE 19. TWO-TONE SPECTRUM
(F1 = 70MHz, F2 = 71MHz AT -7dBFS)
14
60
-120
0
10
20
30
40
50
60
FREQUENCY (MHz)
FIGURE 20. TWO-TONE SPECTRUM
(F1 = 170MHz, F2 = 171MHz AT -7dBFS)
FN7983.3
August 17, 2012
ISLA224P12
Theory of Operation
A user-initiated reset can subsequently be invoked in the event
that the above conditions cannot be met at power-up.
Functional Description
The ISLA224P12 is based upon a 14-bit, 125MSPS A/D converter
core that utilizes a pipelined successive approximation
architecture (see Figure 21). The input voltage is captured by a
Sample-Hold Amplifier (SHA) and converted to a unit of charge.
Proprietary charge-domain techniques are used to successively
compare the input to a series of reference charges. Decisions
made during the successive approximation operations determine
the digital code for each input value. Digital error correction is also
applied, resulting in a total latency of 10 clock cycles. This is
evident to the user as a latency between the start of a conversion
and the data being available on the digital outputs.
Power-On Calibration
As mentioned previously, the cores perform a self-calibration at
start-up. An internal power-on-reset (POR) circuit detects the
supply voltage ramps and initiates the calibration when the
analog and digital supply voltages are above a threshold. The
following conditions must be adhered to for the power-on
calibration to execute successfully:
After the power supply has stabilized, the internal POR releases
RESETN and an internal pull-up pulls it high, which starts the
calibration sequence. If a subsequent user-initiated reset is
desired, the RESETN pin should be connected to an open-drain
driver with an off-state/high impedance state leakage of less
than 0.5mA to assure exit from the reset state so calibration can
start.
The calibration sequence is initiated on the rising edge of
RESETN, as shown in Figure 22. Calibration status can be
determined by reading the cal_status bit (LSB) at 0xB6. This bit is
‘0’ during calibration and goes to a logic ‘1’ when calibration is
complete. The data outputs produce 0xCCCC during calibration;
this can also be used to determine calibration status.
While RESETN is low, the output clock (CLKOUTP/CLKOUTN) is
set low. Normal operation of the output clock resumes at the
next input clock edge (CLKP/CLKN) after RESETN is de-asserted.
At 125MSPS the nominal calibration time is 560ms, while the
maximum calibration time is 1000ms.
• A frequency-stable conversion clock must be applied to the
CLKP/CLKN pins
• DNC pins must not be connected
• SDO has an internal pull-up and should not be driven externally
• RESETN is pulled low by the ADC internally during POR
• External driving of RESETN is optional
• SPI communications must not be attempted
CLOCK
GENERATION
INP
2.5-BIT
FLASH
SHA
INN
1.25V
+
–
2.5-BIT
FLASH
6- STAGE
1.5-BIT/ STAGE
3- STAGE
1-BIT/ STAGE
3-BIT
FLASH
DIGITAL
ERROR
CORRECTION
LVDS/LVCMOS
OUTPUTS
FIGURE 21. A/D CORE BLOCK DIAGRAM
15
FN7983.3
August 17, 2012
ISLA224P12
The performance of the ISLA224P12 changes with variations in
temperature, supply voltage or sample rate. The extent of these
changes may necessitate recalibration, depending on system
performance requirements. Best performance will be achieved
by recalibrating the A/D under the environmental conditions at
which it will operate.
CLKN
CLKP
CALIBRATION
TIME
RESETN
CALIBRATION
BEGINS
CAL_STATUS
BIT
A supply voltage variation of <100mV will generally result in an
SNR change of <0.5dBFS and SFDR change of <3dBc.
CALIBRATION
COMPLETE
In situations where the sample rate is not constant, best results
will be obtained if the device is calibrated at the highest sample
rate. Reducing the sample rate by less than 80MSPS will typically
result in an SNR change of <0.5dBFS and an SFDR change of
<3dBc.
CLKOUTP
FIGURE 22. CALIBRATION TIMING
User Initiated Reset
Recalibration of the A/D can be initiated at any time by driving
the RESETN pin low for a minimum of one clock cycle. An
open-drain driver with a drive strength in its high impedance
state of less than 0.5mA is recommended, as RESETN has an
internal high impedance pull-up to OVDD. As is the case during
power-on reset, RESETN and DNC pins must be in the proper
state for the calibration to successfully execute.
Figures 23 through 28 show the effect of temperature on SNR
and SFDR performance with power on calibration performed at
-40°C, +25°C, and +85°C. Each plot shows the variation of
SNR/SFDR across temperature after a single power on
calibration at -40°C, +25°C and +85°C. Best performance is
typically achieved by a user-initiated power on calibration at the
operating conditions, as stated earlier. However, it can be seen
that performance drift with temperature is not a very strong
function of the temperature at which the power on calibration is
performed.
Temperature Calibration
85
75.00
-2dBFS ANALOG INPUT
-1dBFS ANALOG INPUT
74.50
SFDR (dBc)
SNR (dBFS)
74.75
74.25
74.00
73.75
80
-2dBFS ANALOG INPUT
-1dBFS ANALOG INPUT
73.50
-40
-35
-30
-25
75
-40
-20
-35
FIGURE 23. TYPICAL SNR PERFORMANCE vs TEMPERATURE,
DEVICE CALIBRATED AT -40°C, fIN = 105MHz
-25
-20
FIGURE 24. TYPICAL SFDR PERFORMANCE vs TEMPERATURE,
DEVICE CALIBRATED AT -40°C, fIN = 105MHz
75.00
85
-2dBFS ANALOG INPUT
-1dBFS ANALOG INPUT
74.75
74.50
SFDR (dBc)
SNR (dBFS)
-30
TEMPERATURE (°C)
TEMPERATURE (°C)
74.25
74.00
73.75
80
-2dBFS ANALOG INPUT
-1dBFS ANALOG INPUT
73.50
75
5
10
15
20
25
30
35
40
45
TEMPERATURE (°C)
FIGURE 25. TYPICAL SNR PERFORMANCE vs TEMPERATURE,
DEVICE CALIBRATED AT +25°C, fIN = 105MHz
16
5
10
15
20
25
30
35
40
45
TEMPERATURE (°C)
FIGURE 26. TYPICAL SFDR PERFORMANCE vs TEMPERATURE,
DEVICE CALIBRATED AT +25°C, fIN = 105MHz
FN7983.3
August 17, 2012
ISLA224P12
Temperature Calibration (Continued)
85
75.00
-2dBFS ANALOG INPUT
-1dBFS ANALOG INPUT
74.50
SFDR (dBc)
SNR (dBFS)
74.75
-2dBFS ANALOG INPUT
-1dBFS ANALOG INPUT
74.25
74.00
80
73.75
73.50
65
70
75
80
85
75
65
70
TEMPERATURE (°C)
75
80
85
TEMPERATURE (°C)
FIGURE 27. TYPICAL SNR PERFORMANCE vs TEMPERATURE,
DEVICE CALIBRATED AT +85°C, fIN = 105MHz
FIGURE 28. TYPICAL SFDR PERFORMANCE vs TEMPERATURE,
DEVICE CALIBRATED AT +85°C, fIN = 105MHz
Analog Input
ADTL1-12
A single fully differential input (VINP/VINN) connects to the
sample and hold amplifier (SHA) of each unit A/D. The ideal
full-scale input voltage is 2.0V, centered at the VCM voltage of
0.94V, as shown in Figure 29.
TX-2-5-1
1000pF
A/D
VCM
1000pF
VINN
1.8
FIGURE 31. TRANSMISSION-LINE TRANSFORMER INPUT FOR
HIGH IF APPLICATIONS
VINP
1.4
VCM
0.94V
1.0V
1.0
This dual transformer scheme is used to improve common-mode
rejection, which keeps the common-mode level of the input
matched to VCM. The value of the shunt resistor should be
determined based on the desired load impedance. The
differential input resistance of the ISLA224P12 is 600Ω.
0.6
0.2
FIGURE 29. ANALOG INPUT RANGE
Best performance is obtained when the analog inputs are driven
differentially. The common-mode output voltage, VCM, should be
used to properly bias the inputs, as shown in Figures 30 through
32. An RF transformer will give the best noise and distortion
performance for wideband and/or high intermediate frequency
(IF) inputs. Two different transformer input schemes are shown in
Figures 30 and 31.
ADT1-1WT
The SHA design uses a switched capacitor input stage (see
Figure 45), which creates current spikes when the sampling
capacitance is reconnected to the input voltage. This causes a
disturbance at the input, which must settle before the next
sampling point. Lower source impedance will result in faster
settling and improved performance. Therefore a 2:1 or 1:1
transformer and low shunt resistance are recommended for
optimal performance.
ADT1-1WT
1000pF
A/D
A/D
VCM
0.1µF
FIGURE 30. TRANSFORMER INPUT FOR GENERAL PURPOSE
APPLICATIONS
17
FIGURE 32. DIFFERENTIAL AMPLIFIER INPUT
A differential amplifier, as shown in the simplified block diagram
in Figure 32, can be used in applications that require
DC-coupling. In this configuration, the amplifier will typically
dominate the achievable SNR and distortion performance.
Intersil’s new ISL552xx differential amplifier family can also be
used in certain AC applications with minimal performance
degradation. Contact the factory for more information.
FN7983.3
August 17, 2012
ISLA224P12
The clock input circuit is a differential pair (see Figure 46).
Driving these inputs with a high level (up to 1.8VP-P on each
input) sine or square wave will provide the lowest jitter
performance. A transformer with 4:1 impedance ratio will
provide increased drive levels. The clock input is functional with
AC-coupled LVDS, LVPECL, and CML drive levels. To maintain the
lowest possible aperture jitter, it is recommended to have high
slew rate at the zero crossing of the differential clock input
signal.
The recommended drive circuit is shown in Figure 33. A duty
range of 40% to 60% is acceptable. The clock can be driven
single-ended, but this will reduce the edge rate and may impact
SNR performance. The clock inputs are internally self-biased to
AVDD/2 to facilitate AC-coupling.
1000pF
TC4-19G2+
between clock jitter (tJ) and SNR is shown in Equation 1 and is
illustrated in Figure 34.
1
NR = 20 log 10 ⎛ --------------------⎞
⎝ 2πf t ⎠
IN J
(EQ. 1)
100
95
tj = 0.1ps
90
14 BITS
85
SNR (dB)
Clock Input
80
tj = 1ps
75
12 BITS
70
tj = 10ps
65
60
10 BITS
tj = 100ps
55
50
1M
10M
100M
INPUT FREQUENCY (Hz)
CLKP
1G
FIGURE 34. SNR vs CLOCK JITTER
0.01µF
200
CLKN
1000pF
1000pF
FIGURE 33. RECOMMENDED CLOCK DRIVE
A selectable 2x or 4x frequency divider is provided in series with
the clock input. The divider can be used in the 2x mode with a
sample clock equal to twice the desired sample rate or in 4x
mode with a sample clock equal to four times the desired
sample rate. This allows the use of the Phase Slip feature, which
enables synchronization of multiple ADCs. The Phase Slip feature
can be used as an alternative to using the CLKDIVRST pins to
synchronize ADCs in a multiple ADC system.
This relationship shows the SNR that would be achieved if clock
jitter were the only non-ideal factor. In reality, achievable SNR is
limited by internal factors, such as linearity, aperture jitter and
thermal noise. Internal aperture jitter is the uncertainty in the
sampling instant shown in Figure 3. The internal aperture jitter
combines with the input clock jitter in a root-sum-square fashion,
since they are not statistically correlated, and this determines
the total jitter in the system. The total jitter, combined with other
noise sources, then determines the achievable SNR.
Voltage Reference
A temperature compensated internal voltage reference provides
the reference charges used in the successive approximation
operations. The full-scale range of each A/D is proportional to the
reference voltage. The nominal value of the voltage reference is
1.25V.
Digital Outputs
TABLE 1. CLKDIV PIN SETTINGS
CLKDIV PIN
DIVIDE RATIO
AVSS
2
Float
1
AVDD
4
The clock divider can also be controlled through the SPI port,
which overrides the CLKDIV pin setting. See “SPI Physical
Interface” on page 22. A delay-locked loop (DLL) generates
internal clock signals for various stages within the charge
pipeline. If the frequency of the input clock changes, the DLL may
take up to 100μs to regain lock at 125MSPS. The lock time is
inversely proportional to the sample rate.
The DLL has two ranges of operation; slow and fast. The slow
range can be used for sample rates between 40MSPS and
100MSPS, while the default fast range can be used from
80MSPS to the maximum specified sample rate.
Output data is available as a parallel bus in LVDS-compatible
(default) or CMOS modes. In either case, the data is presented in
double data rate (DDR) format. Figures 3 and 4 show the timing
relationships for LVDS and CMOS modes, respectively.
Additionally, the drive current for LVDS mode can be set to a
nominal 3mA (default) or a power-saving 2mA. The lower current
setting can be used in designs where the receiver is in close
physical proximity to the A/D. The applicability of this setting is
dependent upon the PCB layout, therefore the user should
experiment to determine if performance degradation is
observed.
The output mode can be controlled through the SPI port, by
writing to address 0x73, see “Serial Peripheral Interface” on
page 22.
An external resistor creates the bias for the LVDS drivers. A 10kΩ,
1% resistor must be connected from the RLVDS pin to OVSS.
Jitter
In a sampled data system, clock jitter directly impacts the
achievable SNR performance. The theoretical relationship
18
FN7983.3
August 17, 2012
ISLA224P12
Over-Range Indicator
The over-range (OR) bit is asserted when the output code reaches
positive full-scale (e.g. 0xFFF in offset binary mode). The output
code does not wrap around during an over-range condition. The
OR bit is updated at the sample rate.
BINARY
13
12
11
••••
1
0
••••
Power Dissipation
The power dissipated by the ISLA224P12 is primarily dependent
on the sample rate and the output modes: LVDS vs CMOS and
DDR vs SDR. There is a static bias in the analog supply, while the
remaining power dissipation is linearly related to the sample
rate. The output supply dissipation changes to a lesser degree in
LVDS mode, but is more strongly related to the clock frequency in
CMOS mode.
Nap/Sleep
GRAY CODE
13
12
••••
11
1
0
FIGURE 35. BINARY TO GRAY CODE CONVERSION
Converting back to offset binary from Gray code must be done
recursively, using the result of each bit for the next lower bit as
shown in Figure 36.
GRAY CODE
13
12
11
••••
1
0
Portions of the device may be shut down to save power during
times when operation of the A/D is not required. Two power saving
modes are available: Nap, and Sleep. Nap mode reduces power
dissipation to <103mW while Sleep mode reduces power
dissipation to <19mW.
••••
All digital outputs (Data, CLKOUT and OR) are placed in a high
impedance state during Nap or Sleep. The input clock should
remain running and at a fixed frequency during Nap or Sleep, and
CSB should be high. Recovery time from Nap mode will increase
if the clock is stopped, since the internal DLL can take up to
104µs to regain lock at 125MSPS.
••••
By default after the device is powered on, the operational state is
controlled by the NAPSLP pin as shown in Table 2.
TABLE 2. NAPSLP PIN SETTINGS
NAPSLP PIN
MODE
AVSS
Normal
Float
Sleep
AVDD
Nap
The power-down mode can also be controlled through the SPI
port, which overrides the NAPSLP pin setting. Details on this are
contained in “Serial Peripheral Interface” on page 22.
Data Format
Output data can be presented in three formats: two’s
complement(default), Gray code and offset binary. The data
format can also be controlled through the SPI port, by writing to
address 0x73. Details on this are contained in “Serial Peripheral
Interface” on page 22.
Offset binary coding maps the most negative input voltage to
code 0x000 (all zeros) and the most positive input to 0xFFF (all
ones). Two’s complement coding simply complements the MSB
of the offset binary representation.
When calculating Gray code the MSB is unchanged. The
remaining bits are computed as the XOR of the current bit
position and the next most significant bit. Figure 35 shows this
operation.
19
BINARY
13
12
11
••••
1
0
FIGURE 36. GRAY CODE TO BINARY CONVERSION
Mapping of the input voltage to the various data formats is
shown in Table 3.
TABLE 3. INPUT VOLTAGE TO OUTPUT CODE MAPPING
INPUT
VOLTAGE
OFFSET BINARY
TWO’S
COMPLEMENT
GRAY CODE
–Full Scale 00 0000 0000 0000 10 0000 0000 0000 00 0000 0000 0000
–Full Scale 00 0000 0000 0001 10 0000 0000 0001 00 0000 0000 0001
+ 1LSB
Mid–Scale 10 0000 0000 0000 00 0000 0000 0000 11 0000 0000 0000
+Full Scale 11 1111 1111 1110 01 1111 1111 1110 10 0000 0000 0001
– 1LSB
+Full Scale 11 1111 1111 1111 01 1111 1111 1111 10 0000 0000 0000
Clock Divider Synchronous Reset
An output clock (CLKOUTP, CLKOUTN) is provided to facilitate
latching of the sampled data. The output clock frequency is
equal to the input clock frequency divided by the internal clock
divider setting (see “Clock Input” on page 18).
FN7983.3
August 17, 2012
ISLA224P12
For clock divide settings > ‘1’, the absolute phase of the output
clocks for multiple A/Ds is indeterminate - there will be a phase
ambiguity between the output clocks of ADCs in a multiple ADC
system. The CLKDIVRST feature allows the phase of multiple
A/Ds to be synchronized (see Figure 37) when the internal clock
divider is used, greatly simplifying data capture in systems
employing multiple A/Ds. For clock divide setting = ’1’, there is
no phase ambiguity between clock outputs in a multiple ADC
system and CLKDIVRST can be left as a DNC (do not connect)
The CLKDIVRST signal must be well-timed with respect to the
sample clock (see “Switching Specifications” on page 11).
Figure 37 shows assertion of CLKDIVRSTP by a positive edge
(CLKDIVRSTN must be driven but is not shown); CLKDIVRSTP can
remain high indefinitely after a synchronization event.
CLKDIVRSTP can also be a pulse if needed, with CLKDIVRSTP
returning to a logic ‘0’ after assertion; in this case the CLKDIVRST
pulse width should be a minimum of 3 input sample clock
periods. In applications where multiple CLKDIVRST pulse events
are required, a user should wait a minimum of 30 clock cycles
before starting a second CLKDIVRST pulse event.
It will take a maximum of 30 input clock cycles to attain
synchronization (tRSTRT) in applications where the input clock is
not interrupted; if the input clock is interrupted CLKOUT will be
static or indeterminate until synchronization is attained.
In some applications, interrupting the input sample clock briefly
(~ 150 cycles max) can simplify the timing requirements for
synchronization using CLKDIVRST), in this case the total
CLKDIVRST recovery time will increase by the number of input
clock cycles the sample clock is held static. Valid data is
available (after recovery) in all cases after the normal pipeline
latency.
Intersil Application Note 1604 describes the synchronization of
multiple ISLA1xxP50s. This document discusses the topic of
synchronization in more detail and can be used to better
understand the ISLA2XXPxx ADCs’ operation.
SAMPLE CLOCK
INPUT
(CLKDIV = 2)
s1
L+td
ANALOG INPUT
(Note 14)
s2
tRSTH
CLKDIVRSTP (Note 15)
tRSTS
tRSTRT
ADC1 OUTPUT DATA
s0
s1
s2
s3
s0
s1
s2
s3
ADC1 CLKOUTP
ADC2 OUTPUT DATA
ADC2 CLKOUTP
(phase 1) (Note 15)
ADC2 CLKOUTP
(phase 2) (Note 16)
NOTES:
14. Delay equals fixed pipeline latency (L cycles) plus fixed analog propagation delay td.
15. CLKDIVRSTP setup and hold times are with respect to input sample clock rising edge.
CLKDIVRSTN is not shown, but must be driven, and is the compliment of CLKDIVRSTP.
16. Either Output Clock Phase (Phase 1 or Phase 2 ) equally likely prior to synchronization.
FIGURE 37. SYNCHRONOUS RESET OPERATION
20
FN7983.3
August 17, 2012
ISLA224P12
CSB
SCLK
SDIO
R/W
W1
W0
A12
A11
A1
A10
A0
D7
D6
D5
D4
D3
D2
D1
D0
D2
D3
D4
D5
D6
D7
FIGURE 38. MSB-FIRST ADDRESSING
CSB
SCLK
SDIO
A0
A1
A11
A2
A12
W0
W1
R/W
D1
D0
FIGURE 39. LSB-FIRST ADDRESSING
tDSW
CSB
tCLK
tHI
tDHW
tS
tH
tLO
SCLK
SDIO
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
D4
D3
D2
D1
D0
SPI WRITE
FIGURE 40. SPI WRITE
tDSW
CSB
tCLK
tHI
tDHW
tHR
tDVR
tS
tLO
SCLK
WRITING A READ COMMAND
READING DATA ( 3 WIRE MODE )
SDIO
R/W
W1
W0
A12
A11
A10
A9
A2
A1
A0
D7
SDO
D6
D3
D2
D1 D0
( 4 WIRE MODE)
D7
D3
D2
D1 D0
SPI READ
FIGURE 41. SPI READ
21
FN7983.3
August 17, 2012
ISLA224P12
CSB STALLING
CSB
SCLK
SDIO
INSTRUCTION/ADDRESS
DATA WORD 1
DATA WORD 2
FIGURE 42. 2-BYTE TRANSFER
LAST LEGAL
CSB STALLING
CSB
SCLK
SDIO
INSTRUCTION/ADDRESS
DATA WORD 1
DATA WORD N
FIGURE 43. N-BYTE TRANSFER
Serial Peripheral Interface
A serial peripheral interface (SPI) bus is used to facilitate
configuration of the device and to optimize performance. The SPI
bus consists of chip select (CSB), serial clock (SCLK) serial data
output (SDO), and serial data input/output (SDIO). The maximum
SCLK rate is equal to the A/D sample rate (fSAMPLE) divided by 16
for both write operations and read operations. At
fSAMPLE = 125MHz, maximum SCLK is 7.8125MHz for writing and
read operations. There is no minimum SCLK rate.
The following sections describe various registers that are used to
configure the SPI or adjust performance or functional parameters.
Many registers in the available address space (0x00 to 0xFF) are
not defined in this document. Additionally, within a defined
register there may be certain bits or bit combinations that are
reserved. Undefined registers and undefined values within defined
registers are reserved and should not be selected. Setting any
reserved register or value may produce indeterminate results.
SPI Physical Interface
The serial clock pin (SCLK) provides synchronization for the data
transfer. By default, all data is presented on the serial data
input/output (SDIO) pin in three-wire mode. The state of the SDIO
pin is set automatically in the communication protocol
(described in the following). A dedicated serial data output pin
(SDO) can be activated by setting 0x00[7] high to allow operation
in four-wire mode.
The SPI port operates in a half duplex master/slave
configuration, with the ISLA224P12 functioning as a slave.
Multiple slave devices can interface to a single master in
three-wire mode only, since the SDO output of an unaddressed
device is asserted in four wire mode.
The chip-select bar (CSB) pin determines when a slave device is
being addressed. Multiple slave devices can be written to
concurrently, but only one slave device can be read from at a
given time (again, only in three-wire mode). If multiple slave
22
devices are selected for reading at the same time, the results will
be indeterminate.
The communication protocol begins with an instruction/address
phase. The first rising SCLK edge following a high-to-low
transition on CSB determines the beginning of the two-byte
instruction/address command; SCLK must be static low before
the CSB transition. Data can be presented in MSB-first order or
LSB-first order. The default is MSB-first, but this can be changed
by setting 0x00[6] high. Figures 38 and 39 show the appropriate
bit ordering for the MSB-first and LSB-first modes, respectively. In
MSB-first mode, the address is incremented for multi-byte
transfers, while in LSB-first mode it’s decremented.
In the default mode, the MSB is R/W, which determines if the
data is to be read (active high) or written. The next two bits, W1
and W0, determine the number of data bytes to be read or
written (see Table 4). The lower 13 bits contain the first address
for the data transfer. This relationship is illustrated in Figure 40,
and timing values are given in “Switching Specifications” on
page 11.
After the instruction/address bytes have been read, the
appropriate number of data bytes are written to or read from the
A/D (based on the R/W bit status). The data transfer will
continue as long as CSB remains low and SCLK is active. Stalling
of the CSB pin is allowed at any byte boundary
(instruction/address or data) if the number of bytes being
transferred is three or less. For transfers of four bytes or more,
CSB is allowed to stall in the middle of the instruction/address
bytes or before the first data byte. If CSB transitions to a high
state after that point, the state machine will reset and terminate
the data transfer.
TABLE 4. BYTE TRANSFER SELECTION
[W1:W0]
BYTES TRANSFERRED
00
1
01
2
FN7983.3
August 17, 2012
ISLA224P12
TABLE 4. BYTE TRANSFER SELECTION (Continued)
[W1:W0]
BYTES TRANSFERRED
10
3
11
4 or more
Figures 42 and 43 illustrate the timing relationships for 2-byte
and N-byte transfers, respectively. The operation for a 3-byte
transfer can be inferred from these diagrams.
SPI Configuration
ADDRESS 0X00: CHIP_PORT_CONFIG
Bit ordering and SPI reset are controlled by this register. Bit order
can be selected as MSB to LSB (MSB first) or LSB to MSB (LSB
first) to accommodate various micro controllers.
Bit 7 SDO Active
Bit 6 LSB First
Setting this bit high configures the SPI to interpret serial data
as arriving in LSB to MSB order.
Bit 5 Soft Reset
Setting this bit high resets all SPI registers to default values.
Bit 4 Reserved
ADDRESS 0X20: OFFSET_COARSE_ADC0
ADDRESS 0X21: OFFSET_FINE_ADC0
The input offset of the A/D core can be adjusted in fine and
coarse steps. Both adjustments are made via an 8-bit word as
detailed in Table 5. The data format is twos complement.
The default value of each register will be the result of the
self-calibration after initial power-up. If a register is to be
incremented or decremented, the user should first read the
register value then write the incremented or decremented value
back to the same register. Bit 0 in register 0xFE must be set high
to enable updates written to 0x20 and 0x21 to be used by the
ADC (see description for 0xFE).
TABLE 5. OFFSET ADJUSTMENTS
PARAMETER
0x20[7:0]
COARSE OFFSET
0x21[7:0]
FINE OFFSET
Steps
255
255
–Full Scale (0x00)
-133LSB (-47mV)
-5LSB (-1.75mV)
Mid–Scale (0x80)
0.0LSB (0.0mV)
0.0LSB
+Full Scale (0xFF)
+133LSB (+47mV)
+5LSB (+1.75mV)
Nominal Step Size
1.04LSB (0.37mV)
0.04LSB (0.014mV)
ADDRESS 0X22: GAIN_COARSE_ADC0
This bit should always be set high.
Bits 3:0 These bits should always mirror bits 4:7 to avoid
ambiguity in bit ordering.
ADDRESS 0X02: BURST_END
If a series of sequential registers are to be set, burst mode can
improve throughput by eliminating redundant addressing. The
burst is ended by pulling the CSB pin high. Setting the burst_end
address determines the end of the transfer. During a write
operation, the user must be cautious to transmit the correct
number of bytes based on the starting and ending addresses.
Bits 7:0 Burst End Address
This register value determines the ending address of the burst
data.
Device Information
ADDRESS 0X23: GAIN_MEDIUM_ADC0
ADDRESS 0X24: GAIN_FINE_ADC0
Gain of the A/D core can be adjusted in coarse, medium and fine
steps. Coarse gain is a 4-bit adjustment while medium and fine
are 8-bit. Multiple Coarse Gain Bits can be set for a total
adjustment range of ±4.2%. (‘0011’ @ -4.2% and ‘1100’ @ +4.2%)
It is recommended to use one of the coarse gain settings (-4.2%,
-2.8%, -1.4%, 0, 1.4%, 2.8%, 4.2%) and fine-tune the gain using the
registers at 0x0023 and 0x24.
The default value of each register will be the result of the
self-calibration after initial power-up. If a register is to be
incremented or decremented, the user should first read the
register value then write the incremented or decremented value
back to the same register. Bit 0 in register 0xFE must be set high
to enable updates written to 0x23 and 0x24 to be used by the
ADC (see description for 0xFE).
ADDRESS 0X08: CHIP_ID
ADDRESS 0X09: CHIP_VERSION
The generic die identifier and a revision number, respectively, can
be read from these two registers.
Device Configuration/Control
A common SPI map, which can accommodate single-channel or
multi-channel devices, is used for all Intersil A/D products.
23
TABLE 6. COARSE GAIN ADJUSTMENT
0x22[3:0] core 0
0x26[3:0] core 1
NOMINAL COARSE GAIN ADJUST
(%)
Bit3
+2.8
Bit2
+1.4
Bit1
-2.8
Bit0
-1.4
FN7983.3
August 17, 2012
ISLA224P12
TABLE 7. MEDIUM AND FINE GAIN ADJUSTMENTS
PARAMETER
0x23[7:0]
MEDIUM GAIN
0x24[7:0]
FINE GAIN
Steps
256
256
–Full Scale (0x00)
-2%
-0.20%
Mid–Scale (0x80)
0.00%
0.00%
+Full Scale (0xFF)
+2%
+0.2%
Nominal Step Size
0.016%
0.0016%
ADDRESS 0X25: MODES
Two distinct reduced power modes can be selected. By default,
the tri-level NAPSLP pin can select normal operation, nap or
sleep modes (refer to“Nap/Sleep” on page 19). This functionality
can be overridden and controlled through the SPI. This is an
indexed function when controlled from the SPI, but a global
function when driven from the pin. This register is not changed by
a Soft Reset.
TABLE 8. POWER-DOWN CONTROL
VALUE
0x25[2:0]
POWER DOWN MODE
000
Pin Control
001
Normal Operation
010
Nap Mode
100
Sleep Mode
ADDRESS 0X26: OFFSET_COARSE_ADC1
ADDRESS 0X27: OFFSET_FINE_ADC1
The input offset of A/D core #1 can be adjusted in fine and
coarse steps in the same way that offset for core #0 can be
adjusted. Both adjustments are made via an 8-bit word as
detailed in Table 5. The data format is two’s complement.
The default value of each register will be the result of the
self-calibration after initial power-up. If a register is to be
incremented or decremented, the user should first read the
register value then write the incremented or decremented value
back to the same register. Bit 0 in register 0xFE must be set high
to enable updates written to 0x26 and 0x27 to be used by the
ADC (see description for 0xFE).
ADDRESS 0X28: GAIN_COARSE_ADC1
ADDRESS 0X29: GAIN_MEDIUM_ADC1
ADDRESS 0X2A: GAIN_FINE_ADC1
Gain of A/D core #1 can be adjusted in coarse, medium and fine
steps in the same way that core #0 can be adjusted. Coarse gain is
a 4-bit adjustment while medium and fine are 8-bit. Multiple
Coarse Gain Bits can be set for a total adjustment range of ±4.2%.
Bit 0 in register 0xFE must be set high to enable updates written
to 0x29 and 0x2A to be used by the ADC (see description for
0xFE).
24
Global Device Configuration/Control
ADDRESS 0X71: PHASE_SLIP
The output data clock is generated by dividing down the A/D
input sample clock. Some systems with multiple A/Ds can more
easily latch the data from each A/D by controlling the phase of
the output data clock. This control is accomplished through the
use of the phase_slip SPI feature, which allows the rising edge of
the output data clock to be advanced by one input clock period,
as shown in the Figure 44. The clock divider (CLKDIV>=2) is
required to use PHASE_SLIP. Execution of a phase_slip
command is accomplished by first writing a '0' to bit 0 at address
0x71, followed by writing a '1' to bit 0 at address 0x71.
ADC Input
Clock (250MHz)
4ns
Output Data
Clock (125MHz)
No clock_slip
8ns
4ns
Output Data
Clock (125MHz)
1 clock_slip
Output Data
Clock (125MHz)
2 clock_slip
CLKDIV=2
FIGURE 44. PHASE SLIP
ADDRESS 0X72: CLOCK_DIVIDE
The ISLA224P12 has a selectable clock divider that can be set to
divide by four, two or one (no division). By default, the tri-level
CLKDIV pin selects the divisor This functionality can be
overridden and controlled through the SPI, as shown in Table 9.
This register is not changed by a Soft Reset.
TABLE 9. CLOCK DIVIDER SELECTION
VALUE
0x72[2:0]
CLOCK DIVIDER
000
Pin Control
001
Divide by 1
010
Divide by 2
100
Divide by 4
other
Not Allowed
ADDRESS 0X73: OUTPUT_MODE_A
The output_mode_A register controls the physical output format
of the data, as well as the logical coding. The ISLA224P12 can
present output data in two physical formats: LVDS(default) or
LVCMOS. Additionally, the drive strength in LVDS mode can be set
high (default, 3mA or low (2mA).
Data can be coded in three possible formats: two’s complement
(default), Gray code or offset binary. See Table 11.
FN7983.3
August 17, 2012
ISLA224P12
This register is not changed by a Soft Reset.
pattern depth value to [2:0] at 0xC0. See the “SPI Memory
Map” on page 27.
TABLE 10. OUTPUT MODE CONTROL
VALUE
0x73[7:5]
OUTPUT MODE
000
LVDS 3mA (Default)
001
LVDS 2mA
100
LVCMOS
Bits 2:0 User Test Mode
The three LSBs in this register determine the test pattern in
combination with registers 0xC1 through 0xD0. Refer to the
“SPI Memory Map” on page 27.
TABLE 13. OUTPUT TEST MODES
TABLE 11. OUTPUT FORMAT CONTROL
VALUE
0xC0[7:4]
OUTPUT TEST MODE
0000
Off
WORD 1
WORD 2
VALUE
0x73[2:0]
OUTPUT FORMAT
0001
Midscale
0x8000
N/A
000
Two’s Complement (Default)
0010
Positive Full-Scale
0xFFFF
N/A
010
Gray Code
0011
Negative Full-Scale
0x0000
N/A
100
Offset Binary
0100
Reserved
N/A
N/A
ADDRESS 0X74: OUTPUT_MODE_B
0101
Reserved
N/A
N/A
Bit 6 DLL Range
0110
Reserved
N/A
N/A
This bit sets the DLL operating range to fast (default) or slow.
0111
Reserved
Internal clock signals are generated by a delay-locked loop (DLL),
which has a finite operating range. Table 12 shows the allowable
sample rate ranges for the slow and fast settings.
1000
User Pattern
user_patt1
user_patt2
1001
Reserved
N/A
N/A
1010
Ramp
N/A
N/A
TABLE 12. DLL RANGES
ADDRESS 0XC1: USER_PATT1_LSB
DLL RANGE
MIN
MAX
UNIT
Slow
40
100
MSPS
ADDRESS 0XC2: USER_PATT1_MSB
Fast
80
125
MSPS
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 1.
ADDRESS 0XB6: CALIBRATION STATUS
The LSB at address 0xB6 can be read to determine calibration
status. The bit is ‘0’ during calibration and goes to a logic ‘1’
when calibration is complete. This register is unique in that it can
be read after POR at calibration, unlike the other registers on
chip, which can’t be read until calibration is complete.
DEVICE TEST
ADDRESS 0XC3: USER_PATT2_LSB
ADDRESS 0XC4: USER_PATT2_MSB
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 2
ADDRESS 0XC5: USER_PATT3_LSB
The ISLA224P12 can produce preset or user defined patterns on
the digital outputs to facilitate in-situ testing. A user can pick
from preset built-in patterns by writing to the output test mode
field [7:4] at 0xC0 or user defined patterns by writing to the user
test mode field [2:0] at 0xC0. The user defined patterns should
be loaded at address space 0xC1 through 0xD0, see the “SPI
Memory Map” on page 27 for more detail. The predefined
patterns are shown in Table 13. The test mode is enabled
asynchronously to the sample clock, therefore several sample
clock cycles may elapse before the data is present on the output
bus.
ADDRESS 0XC6: USER_PATT3_MSB
ADDRESS 0XC0: TEST_IO
ADDRESS 0XCA: USER_PATT5_MSB
Bits 7:4 Output Test Mode
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 5.
These bits set the test mode according to Table 13. Other
values are reserved. User test patterns loaded at 0xC1 through
0xD0 are also available by writing ‘1000’ to [7:4] at 0xC0 and a
25
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 3
ADDRESS 0XC7: USER_PATT4_LSB
ADDRESS 0XC8: USER_PATT4_MSB
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 4.
ADDRESS 0XC9: USER_PATT5_LSB
FN7983.3
August 17, 2012
ISLA224P12
ADDRESS 0XCB: USER_PATT6_LSB
ADDRESS 0XCC: USER_PATT6_MSB
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 6
ADDRESS 0XCD: USER_PATT7_LSB
ADDRESS 0XCE: USER_PATT7_MSB
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 7.
ADDRESS 0XFE: OFFSET/GAIN_ADJUST_ENABLE
Bit 0 at this register must be set high to enable adjustment of
offset coarse and fine adjustments ADC0 (0x20 and 0x21), ADC1
(0x26 and 0x27) and gain medium and gain fine adjustments
ADC0 (0x23 and 0x24), ADC1 (0x29 and 0x2A). It is
recommended that new data be written to the offset and gain
adjustment registers ADC0(0x20, 0x21, 0x23, 0x24) and
ADC1(0x26, 0x27, 0x29, 0x2A) while Bit 0 is a ‘0’. Subsequently,
Bit 0 should be set to ‘1’ to allow the values written to the
aforementioned registers to be used by the ADC. Bit 0 should be
set to a ‘0’ upon completion
ADDRESS 0XCF: USER_PATT8_LSB
ADDRESS 0XD0: USER_PATT8_MSB
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 8.
26
FN7983.3
August 17, 2012
ISLA224P12
Device Config/Control
DUT Info
SPI Config/Control
SPI Memory Map
ADDR.
(Hex)
PARAMETER NAME
BIT 7
(MSB)
00
port_config
01
Reserved
Reserved
02
burst_end
Burst end address [7:0]
03-07
Reserved
Reserved
BIT 6
BIT 5
BIT 4
BIT 3
SDO Active LSB First Soft Reset
BIT 2
BIT 1
BIT 0
(LSB)
DEF. VALUE
(HEX)
Mirror
(bit5)
Mirror
(bit6)
Mirror
(bit7)
00h
00h
08
chip_id
Chip ID #
Read only
09
chip_version
Chip Version #
Read only
0A-0F
Reserved
Reserved
10-1F
Reserved
Reserved
20
offset_coarse_adc0
Coarse Offset
cal. value
21
offset_fine_adc0
Fine Offset
cal. value
22
gain_coarse_adc0
23
gain_medium_adc0
24
gain_fine_adc0
25
modes_adc0
26
offset_coarse_adc1
27
offset_fine_adc1
28
gain_coarse_adc1
Reserved
Coarse Gain
cal. value
Medium Gain
cal. value
Fine Gain
Reserved
cal. value
Power Down Mode ADC0 [2:0]
000 = Pin Control
001 = Normal Operation
010 = Nap
100 = Sleep
Other codes = Reserved
Coarse Offset
cal. value
Fine Offset
Reserved
00h
NOT reset by
Soft Reset
cal. value
Coarse Gain
cal. value
29
gain_medium_adc1
Medium Gain
cal. value
2A
gain_fine_adc1
Fine Gain
cal. value
2B
modes_adc1
2C-2F
Reserved
Reserved
33-4A
Reserved
Reserved
4B
Reserved
4C
Reserved
4D
Reserved
4E-6F
Reserved
Reserved
Power Down Mode ADC1 [2:0]
000 = Pin Control
001 = Normal Operation
010 = Nap
100 = Sleep
Other codes = Reserved
Reserved
Read only
Reserved
Enable
PD
Reset
00h
NOT reset by
Soft Reset
Read only
Divider [2:0]
Select
00h
Reserved
70
skew_diff
71
phase_slip
Differential Skew
72
clock_divide
Reserved
27
80h
Next Clock
Edge
Clock Divide [2:0]
000 = Pin Control
001 = divide by 1
010 = divide by 2
100 = divide by 4
Other codes = Reserved
00h
00h
NOT reset by
Soft Reset
FN7983.3
August 17, 2012
ISLA224P12
Device Config/Control
SPI Memory Map (Continued)
ADDR.
(Hex)
PARAMETER NAME
73
output_mode_A
Output Mode [7:5]
000 = LVDS 3mA (Default)
001 = LVDS 2mA
100 = LVCMOS
Other codes = Reserved
74
output_mode_B
DLL Range
0 = Fast
1 = Slow
Default=’0
’
75-B5
Reserved
B6
cal_status
B7-BF
Reserved
C0
test_io
BIT 7
(MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 1
BIT 0
(LSB)
DEF. VALUE
(HEX)
00h
Output Format [2:0]
000 = Two’s Complement (Default) NOT reset by
Soft Reset
010 = Gray Code
100 = Offset Binary
Other codes = Reserved
00h
NOT reset by
Soft Reset
Reserved
Calibration
Done
Output Test Mode [7:4]
User Test Mode [2:0]
0 = user pattern 1-2
1 = cycle pattern 1 through 4
2 = cycle pattern 1 through 6
3 = cycle pattern 1 through 8
4-7 = NA
0 = Off (Note 14)
1 = Midscale Short
2 = +FS Short
3 = -FS Short
4 = Checkerboard (Note 15)
5-6 = Reserved
7 = All on/ off (Note 16)
8 = User Pattern (1 to 8 deep)
9 = Reserved
10 = Ramp
11-15 = Reserved
Device Test
BIT 2
Read Only
00h
C1
user_patt1_lsb
B7
B6
B5
B4
B3
B2
B1
B0
0x00
C2
user_patt1_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
C3
user_patt2_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
C4
user_patt2_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
C5
user_patt3_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
C6
user_patt3_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
C7
user_patt4_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
C8
user_patt4_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
C9
user_patt5_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
CA
user_patt5_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
CB
user_patt6_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
CC
user_patt6_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
CD
user_patt7_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
CE
user_patt7_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
CF
user_patt8_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
D0
user_patt8_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
Enable
‘1’=Enable
00h
D1-FD
Reserved
FE
Offset/Gain_Adjust_Enable
Reserved
FF
Reserved
NOTES:
14. During Calibration xCCCC (MSB justified) is presented at the output data bus, toggling on the LSB (and higher) data bits occurs at completion of
calibration. This behavior can be used as an option to determine calibration state.
15. Use test_io = 0x41 for Checkerboard outputs on DDR Outputs.
16. Use test_io = 0x71 for all ones/zeroes outputs on DDR Outputs.
28
FN7983.3
August 17, 2012
ISLA224P12
Equivalent Circuits
AVDD
TO
CLOCK-PHASE
GENERATION
AVDD
CLKP
AVDD
AVDD
CSAMP
4pF
TO
CHARGE
PIPELINE
INP
E2
E1
600
AVDD
TO
CHARGE
PIPELINE
INN
E2
E1
18k
E3
CSAMP
4pF
AVDD
11k
CLKN
E3
FIGURE 45. ANALOG INPUTS
AVDD
18k
11k
FIGURE 46. CLOCK INPUTS
AVDD
(20k PULL-UP
ON RESETN
ONLY)
AVDD
75k
AVDD
OVDD
TO
SENSE
LOGIC
75k
280
INPUT
OVDD
OVDD
20k
INPUT
75k
TO
LOGIC
280
75k
FIGURE 48. DIGITAL INPUTS
FIGURE 47. TRI-LEVEL DIGITAL INPUTS
OVDD
2mA OR
3mA
OVDD
DATA
DATA
OVDD
OVDD
D[13:0]P
OVDD
DATA
D[13:0]
D[13:0]N
DATA
DATA
2mA OR
3mA
FIGURE 49. LVDS OUTPUTS
29
FIGURE 50. CMOS OUTPUTS
FN7983.3
August 17, 2012
ISLA224P12
Equivalent Circuits (Continued)
AVDD
VCM
0.94V
+
–
FIGURE 51. VCM_OUT OUTPUT
A/D Evaluation Platform
LVCMOS Outputs
Intersil offers an A/D Evaluation platform, which can be used to
evaluate any of Intersil’s high speed A/D products. The platform
consists of a FPGA based data capture motherboard and a family
of A/D daughtercards. This USB based platform allows a user to
quickly evaluate the A/D’s performance at a user’s specific
application frequency requirements. More information is
available at
http://www.intersil.com/converters/adc_eval_platform/
Output traces and connections must be designed for 50W
characteristic impedance.
Unused Inputs
Layout Considerations
Standard logic inputs (RESETN, CSB, SCLK, SDIO, SDO) that will
not be operated do not require connection to ensure optimal A/D
performance. These inputs can be left floating if they are not
used. Tri-level inputs (NAPSLP) accept a floating input as a valid
state, and therefore should be biased according to the desired
functionality.
Split Ground and Power Planes
Definitions
Data converters operating at high sampling frequencies require
extra care in PC board layout. Many complex board designs
benefit from isolating the analog and digital sections. Analog
supply and ground planes should be laid out under signal and
clock inputs. Locate the digital planes under outputs and logic
pins. Grounds should be joined under the chip.
Analog Input Bandwidth is the analog input frequency at which
the spectral output power at the fundamental frequency (as
determined by FFT analysis) is reduced by 3dB from its full-scale
low-frequency value. This is also referred to as Full Power
Bandwidth.
Clock Input Considerations
Use matched transmission lines to the transformer inputs for the
analog input and clock signals. Locate transformers and
terminations as close to the chip as possible.
Exposed Paddle
The exposed paddle must be electrically connected to analog
ground (AVSS) and should be connected to a large copper plane
using numerous vias for optimal thermal performance.
Bypass and Filtering
Bulk capacitors should have low equivalent series resistance.
Tantalum is a good choice. For best performance, keep ceramic
bypass capacitors very close to device pins. Longer traces will
increase inductance, resulting in diminished dynamic
performance and accuracy. Make sure that connections to
ground are direct and low impedance. Avoid forming ground
loops.
LVDS Outputs
Output traces and connections must be designed for 50W (100W
differential) characteristic impedance. Keep traces direct and
minimize bends where possible. Avoid crossing ground and
power-plane breaks with signal traces.
30
Aperture Delay or Sampling Delay is the time required after the
rise of the clock input for the sampling switch to open, at which
time the signal is held for conversion.
Aperture Jitter is the RMS variation in aperture delay for a set of
samples.
Clock Duty Cycle is the ratio of the time the clock wave is at logic
high to the total time of one clock period.
Differential Non-Linearity (DNL) is the deviation of any code width
from an ideal 1 LSB step.
Effective Number of Bits (ENOB) is an alternate method of
specifying Signal to Noise-and-Distortion Ratio (SINAD). In dB, it
is calculated as: ENOB = (SINAD - 1.76)/6.02
Gain Error is the ratio of the difference between the voltages that
cause the lowest and highest code transitions to the full-scale
voltage less than 2 LSB. It is typically expressed in percent.
I2E The Intersil Interleave Engine. This highly configurable
circuitry performs estimates of offset, gain, and sample time
skew mismatches between the core converters, and updates
analog adjustments for each to minimize interleave spurs.
Integral Non-Linearity (INL) is the maximum deviation of the
A/D’s transfer function from a best fit line determined by a least
squares curve fit of that transfer function, measured in units of
LSBs.
FN7983.3
August 17, 2012
ISLA224P12
Least Significant Bit (LSB) is the bit that has the smallest value or
weight in a digital word. Its value in terms of input voltage is
VFS/(2N-1) where N is the resolution in bits.
Missing Codes are output codes that are skipped and will never
appear at the A/D output. These codes cannot be reached with
any input value.
Most Significant Bit (MSB) is the bit that has the largest value or
weight.
Pipeline Delay is the number of clock cycles between the
initiation of a conversion and the appearance at the output pins
of the data.
Power Supply Rejection Ratio (PSRR) is the ratio of the observed
magnitude of a spur in the A/D FFT, caused by an AC signal
superimposed on the power supply voltage.
Signal to Noise-and-Distortion (SINAD) is the ratio of the RMS
signal amplitude to the RMS sum of all other spectral
components below one half the clock frequency, including
harmonics but excluding DC.
Signal-to-Noise Ratio (without Harmonics) is the ratio of the RMS
signal amplitude to the RMS sum of all other spectral
components below one-half the sampling frequency, excluding
harmonics and DC.
SNR and SINAD are either given in units of dB when the power of
the fundamental is used as the reference, or dBFS (dB to full
scale) when the converter’s full-scale input power is used as the
reference.
Spurious-Free-Dynamic Range (SFDR) is the ratio of the RMS
signal amplitude to the RMS value of the largest spurious
spectral component. The largest spurious spectral component
may or may not be a harmonic.
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest Rev.
DATE
REVISION
CHANGE
July 12, 2012
FN7983.3
Features: Removed duplicate “Nap and Sleep Modes”.
June 26, 2012
FN7983.2
Initial Release
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on
intersil.com: ISLA224P12
To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff
FITs are available from our website at: http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
31
FN7983.3
August 17, 2012
ISLA224P12
Package Outline Drawing
L72.10x10E
72 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 11/09
A
X
10.00
9.75
72
Z
EXPOSED
PAD AREA
B
6
PIN #1
INDEX AREA
72
1
1
6
PIN 1
INDEX AREA
8.500 REF. (4X)
9.75
3.000
REF.
6.000 REF.
10.00
0.100 M C A B
(4X)
0.15
4.150 REF.
TOP VIEW
7.150 REF.
0.100 M C A B
BOTTOM VIEW
11°
ALL AROUND
9.75 ±0.10
Y
C0.400X45° (4X)
10.00 ±0.10
(0.350)
0.450
R0.200
SIDE VIEW
25
.1
(0
(4X 9.70)
LL
A
A
O
R
D
N
)
1
C0.190X45°
(4.15 REF)
U
(1.500)
(7.15)
0.500 ±0.100
72
R0.115 TYP.
(3.00 )
(4X 8.50)
(6.00)
DETAIL "Z"
R0.200 MAX.
ALL AROUND
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ANSI Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.10
Angular ±2.50°
4.
Dimension applies to the metallized terminal and is measured
between 0.015mm and 0.30mm from the terminal tip.
5.
Tiebar shown (if present) is a non-functional feature.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
7.
Package outline compliant to JESD-M0220.
0.190~0.245
SEATING
PLANE
0.080 C
0.50
0.025 ±0.020
0.23 ±0.050
0.85 ±0.050
0.100 C
( 72X 0 .70)
0.650 ±0.050
( 72X 0 .23)
DETAIL "X"
C
0.100 M C A B
0.050 M C
DETAIL "Y"
either a mold or mark feature.
32
FN7983.3
August 17, 2012
Similar pages