an9518

Using The HI7188 Evaluation Kit
Application Note
June 1996
AN9518.1
Authors: John J. Kornblum and David C. Jarman
Evaluation Kit Description
Hardware Description
The HI7188 Evaluation Kit (evaluation board and evaluation
software) can be used to evaluate the performance of the
HI7188 16-bit Sigma Delta Analog-to-Digital Converter (ADC).
The evaluation board includes a reference circuit, a crystal, an
oscillator, and digital circuitry used to interface to a personal
computer running the evaluation software. Also included are
two single ended to differential converter circuits and two
resistor ladder networks which can be used to provide inputs
to the HI7188. In addition, the board provides means for the
user to supply an external reference and an external clock.
The HI7188 Evaluation Board provides the user with a very
simple way of interfacing to, and evaluating the Intersil
HI7188 16-channel sigma delta ADC. The board features two
reference voltage generators, a crystal oscillator, and digital
line drivers and receivers for interfacing to a PC running the
evaluation software. The board consists of 4 layers with separate analog and digital ground planes for obtaining optimum
noise performance.
HI7188 Description
The HI7188 is a Monolithic 8-Channel Sigma-Delta A/D
Converter which operates from ±5V supplies and is intended
for use in applications such as industrial weight scales, process controls, and process measurement systems. The
block diagram shows that the device consists of an 8-channel multiplexer, Programmable Gain Instrumentation Amplifier (PGIA), Sigma-Delta modulator, digital filter, bidirectional
serial port (compatible with many industry standard protocols), clock oscillator, a controller, and static RAMs used for
calibration coefficients and conversion scan buffer.
The 8 to 1 multiplexer at the input, combined with the
resetable modulator on the HI7188, allow for conversions of
up to 8 channels of data with each channel being updated at a
rate of 240 samples per second (with 60Hz line noise rejection enabled). After the signal has passed through the multiplexer it moves into the PGIA where it is gained up by a factor
of 1 to 8 and then it passes to the sigma delta modulator. The
data emerges from the modulator as a pulse train whose code
density contains the analog signal information. The output of
the modulator is fed into the digital integrating filter. Data out
of the filter is available after 201 bits are received from the
modulator. If the part is in line noise rejection mode, the integrator filter data is routed to one of eight averaging filters. The
averaged data is then calibrated and stored in the data RAM.
If line noise rejection is disabled, the averaging filters are
bypassed, calibration is performed on the data from the integrating filter, and the result is stored in the data RAM.
After all active channels are converted, the HI7188 generates an End-of-Scan interrupt, EOS, that indicates all active
channels have been updated and valid data is available to be
read.
Converted data is read via the HI7188 serial I/O port which
is compatible with most synchronous transfer formats including both the Motorola SPI and Intel 8051 series SSR protocols. Data is read from the HI7188 in “burst” mode. That is,
the data for all active channels is read out of the HI7188 in a
single read communication cycle.
1
Layout and Power Supplies
The HI7188 Evaluation Board consists of 4 layers laid out to
optimize performance of the ADC. The figures at the end of
this document include the various layers of the board and
their layout, a list of the board components, and schematics.
Users should feel free to copy this layout for use in their
applications.
The power supplies are provided to the board via the edge
connector located at the top of the board. It is recommended
that twisted pair wires be used to connect the power supplies
to the connector and that analog and digital grounds be tied
together back at the power supplies. The separate supplies
are necessary to keep the digital noise from coupling into the
analog portions of the circuit. One of the internal layers of the
board is the ground plane layer. This layer is roughly divided in
half, with one half being digital ground and the other half being
analog ground. The other internal layer is the power plane. It
is divided into three sections; AVDD, AVSS, and DVDD. Nominal values for the supplies are AVDD = +5V, AVSS = -5V, and
DVDD = +5V. In some cases (for instance, if there is a substantial offset between AGND and DGND) it may be necessary to tie the two grounds together on the board. Resistors
R2, R4, and R5 provide a means of connecting the two ground
planes together via a low impedance.
A prototype area is provided on the left side of the board.
This area has a small section of analog ground plane in the
center and may be useful for input signal conditioning in front
of the HI7188.
Reference Circuit
The reference inputs of the HI7188, VRHI and VRLO, provide
a differential reference input capability. The reference inputs
provide a high impedance dynamic load similar to the analog
inputs. For proper circuit operation these pins must be driven
by low impedance circuitry. Reference noise outside of the
band of interest will be removed by the on-chip digital filter,
but excessive reference noise inside the band of interest will
degrade performance of the HI7188.
1-888-INTERSIL or 321-724-7143 | Copyright
© Intersil Corporation 1999
HI7188 Functional Block Diagram
VREF HI VREF LO
50/60Hz REJECT
2
VIN1H, VIN1L 2
VIN2H, VIN2L 2
50/60Hz REJECT
VIN3H, VIN3L 2
50/60Hz REJECT
VIN4H, VIN4L 2
PGIA
∑−∆
VIN5H, VIN5L 2
1
INTEGRATING
FILTER
50/60Hz REJECT
23
CALIBRATION
AND
CONTROL
24
16
Application Note 9518
4TH
ORDER
MODULATOR
50/60Hz REJECT
VIN6H, VIN6L 2
VIN7H, VIN7L 2
DATA
RAM
50/60Hz REJECT
DATA
RAM
VIN8H, VIN8L 2
50/60Hz REJECT
50/60Hz REJECT
16
CONVERSION CONTROL
CHANNEL
CONFIGURATION
REGISTERS
VCM
SERIAL
INTERFACE
CONTROL
REGISTER
MUXCTL
EOS
CA
CADDR <2:0>
RST MODE
CS
OSC1
CLOCK
GENERATOR
SCLK SDO SDIO RSTIO
OSC2
Application Note 9518
HI7188 Evaluation Board Simplified Block Diagram
J2
EXTERNAL DIFFERENTIAL
INPUT CONNECTOR
16 CHANNELS
CRYSTAL
OSCILLATOR
J6 - J13, J16 - J23
EXTERNAL
CLOCK
16 CHANNELS
JP4 - JP19
CALIBRATION
JUMPERS
VINH1
16 CHANNELS
CRYSTAL
OSC1
VINL1
OSC2
JP20 - JP35
FILTER JUMPERS
VINH8
16 CHANNELS
VINL8
DIGITAL
I/O
VRHI
J4, J5, J14, J15
ON-BOARD
REFERENCES
VRLO
LINE
DRIVERS
AND
RECEIVERS
TO
PC
VCM
SINGLE TO DIFFERENTIAL
CONVERTERS AND
TAP VOLTAGES
EXTERNAL
VREF
DGND
HI7188
The actual reference voltage is given by VREF = VRHI VRLO. The VRLO pin is hard wired to analog ground on the
evaluation board which means that VREF = VRHI. The nominal reference voltage for the HI7188 is 2.5V. Larger values of
VREF can be used without degradation in performance.
Smaller values of VREF can also be used, but performance
will be degraded since the system noise becomes larger relative to the LSB size.
The jumper JP1 controls whether the VRHI pin of the HI7188
is connected to an external reference, which connects to the
VREFH SMA pad, or to the on-board reference which is preset to 2.5V. If JP1 is in the far right position VRHI is connected to the on-board low noise reference and when JP2 is
in the far left position VRHI is connected to the external reference. If an external reference is used, it is recommended
that a twisted pair wire be used and soldered directly to the
SMA pad on the evaluation board. The potentiometer R1 can
be used to vary the on-board reference voltage. Please note
that the specifications for the HI7188 are tested with VREF
set to 2.5V. VRHI must always be greater than VRLO for
proper operation of the device.
Analog Inputs
The 8 analog inputs on the HI7188 are fully differential inputs
with programmable gain capabilities. The inputs accept both
unipolar and bipolar input signals and gains range from 1 to 8.
The user must pay careful attention to the input driver and/or
3
input filter circuitry as the input sampling rate (or modulator
clock rate) varies with the selected PGIA gain, and the input
impedance is dependent upon the modulator clock rate.
Please refer to the data sheet for more information.
External analog inputs come onto the board via the 34 pin
connector (J2) located at the upper left hand corner of the
board. Pin 1 is the bottom left pin on the connector.
The top row of jumpers (J6 - J13, J16 - J23) are used in conjunction with the single ended to differential converters. If an
external input on J2 is being used for a particular channel
then the top row jumpers for that channel must be removed
from the board. For example, if external inputs are used for
channels 1 and 5 and come into the board on J2, jumpers
J6, J10, J16, and J20 must be removed from the board.
The middle row of jumpers, JP4 - JP19 can be used to calibrate the HI7188 in the gain of 1 mode by using the on-board
reference voltage. For example, to perform a positive full
scale calibration on channel 3 jumper JP9 is in the upper
position (VREF) while JP8 is in the lower position (AGND).
For a negative full scale calibration on channel 3, jumper
JP9 is in the lower position (AGND) and jumper JP8 is in the
upper position (VREF). To offset calibrate channel 6 on the
HI7188 jumpers JP13 and JP14 are in the lower position
(AGND). If an external or on-board input is being used for a
particular channel then the middle row jumpers for that channel must be removed from the board. For example, if exter-
Application Note 9518
nal inputs are used for channels 1 and 5, jumpers JP4, JP7,
JP12, and JP15 must be removed from the board.
The bottom row of jumpers (JP20 to JP35) provide a simple
single pole RC Filter for each channel input. Putting the
jumper in the lower position means the input will be non-filtered while moving the jumper to the upper position will provide filtering.
Single Ended to Differential Converters
The board also includes 2 single ended to differential converters for use with external or on-board analog input voltages. The external inputs to the converters are the VINX and
VINY sockets on the boards. It is recommended that twisted
pair wire be used to connect to external analog inputs to
VINX and VINY on the evaluation board. Jumpers J4, J5,
J14, and J15 used in conjunction with jumpers J6 - J13 and
J16 - J23 connect the outputs of the single ended to differential converters to the inputs of the HI7188. The board is set
up such that an inherent gain of 2 exists in these converters.
So if VINX = 1V, the output of the single ended to differential
converter will be ±1V. Note that use of these single ended to
differential converters may limit the performance of the
HI7188.
The evaluation board also contains on-board resistor strings
used to generate inputs to the single ended to differential
converters. These on-board voltages provide the user with a
quick method of checking operation of the setup as well as
the various gains of the HI7188. With the on-board voltages
VREFH and VMINUS set to +2.5V and -2.5V respectively, the
following nominal “tap” voltages result:
TAP1 = 1.4996V
TAP2 = 1.0004V
TAP3 = 0.12478V
TAP4 = -0.12478V
VREFH and VMINUS are adjustable via R1 and R37 respectively.
Common Mode Input
The jumper JP2 is provided to allow the VCM Pin to be tied
to either analog ground (lower position), or VRHI (upper position). The input voltage for VCM should always be set at the
midpoint between AVDD and AVSS. So if AVDD = +5V and
AVSS = -5V, VCM should be at analog ground. Please note
the HI7188 is specified for AVDD = +5V and AVSS = -5V
operation only.
Clock Input
The master clock into the HI7188 can be supplied by either a
crystal connected between the OSC1 and OSC2 pins or a
CMOS compatible clock signal connected to the OSC1 pin.
The input sampling frequency, modulator clock frequency,
line noise rejection frequencies, output update rate, and calibration times are all directly related to the master clock frequency, fOSC. For the recommended 3.6864MHz clock the
available line noise rejection frequencies are 50Hz and
60Hz. If line noise rejection of 60Hz is chosen the output
update rate is 16.67ms. Please note that the HI7188 Specifications are written for a 3.6864MHz clock only.
4
The HI7188 Evaluation Board allows for the HI7188 Master
Clock to be supplied externally, generated by the on-board
crystal oscillator, or generated by an on-board crystal used
in conjunction with the on-chip oscillator circuitry. The jumper
JP3 must be removed from the board when using an external clocking source and the external clocking source must be
disconnected from the board when using either of the onboard clocking methods. When JP3 is in the left most position the 3.6864MHz crystal oscillator is selected and when
JP3 is in the right most position the combination 3.6864MHz
crystal and on-chip oscillator clocking method is selected.
For the best noise performance the crystal should be
removed from the board when using the crystal oscillator
and vice versa. Both the crystal and crystal oscillator should
be removed when using an external clock.
Digital Inputs/Outputs
The digital input and output pins of the HI7188 are interfaced
through line drivers and receivers to the 25 pin D connector
at the right edge of the board. These pins are activated and
deactivated by the evaluation software which controls the
functionality of the HI7188. Please refer to the HI7188 Data
Sheet for a detailed description of the functionality of these
pins.
U4 on the Evaluation Board is an “open socket” which is
used in conjunction with the test modes of the HI7188 for
Intersil internal testing and evaluation.
Software Description
The HI7188 Evaluation Software is designed to work with
the HI7188 Evaluation Hardware when connected to a
printer port on a standard PC. Both the executable file and
the source code are provided. The source code was compiled with Borland’s Turbo C++, Version 3.
The HI7188 Evaluation Software allows the user to operate
the device in most of the various configurations the part supports. The software is menu driven for ease of use. The simplified flow diagram shown in Figure 1 gives a good feel for
the structure of the software.
The HI7188 Evaluation Software includes capability that
allows the user to quickly perform the following functions:
1. Program the HI7188 without detailed knowledge of the
Serial Interface.
2. Determine and/or save the current HI7188 configuration.
3. Read/Write all registers without detailed knowledge of the
Serial Interface.
4. Continuously read the Data RAM and display statistics
based on the conversion results.
5. Move to any menu from any menu in a single keystroke.
6. Initialize the HI7188 in a single keystroke.
Application Note 9518
Configuration Menu:
MAIN MENU
READ
MENU
CONFIGURATION
MENU
IO RESET
RESET
WRITE
MENU
EXIT
PROGRAM
FIGURE 1. SIMPLIFIED SOFTWARE FLOW CHART
The Main Menu appears after invoking the HI7188 Evaluation Software. This menu is the gateway to other menus that
allow the user to communicate with and evaluate the
HI7188.
Main Menu:
c
Configuration Menu
r
Read Menu
Configuration Menu:
1
Set Chip Configuration
2
Set Channel Configuration
3
Set Full Configuration
4
Interpret Configuration File
5
Display/Save Current Configuration
6
Restore Full Configuration
Menu Select:
m Main Menu
w Write Menu
x
The Configuration Menu allows the user to quickly program
the HI7188 or to verify the current configuration. Capability
includes: 1) Chip level and channel level programming via
prompts to the user, 2) Configure the HI7188 from a file and
save the current configuration to a file, 3) Interpret a configuration file and 4) Move from the Configuration Menu to any
other menu.
r
EXIT PROGRAM
Read Menu
w Write Menu
Reset Select:
i
I/O Reset
Reset Select:
s
System Reset
i
I/O Reset
Enter Selection:
s
System Reset
c
Enter Selection:
r
Configuration Menu: Entering c from the Main Menu
causes the HI7188 Configuration Menu to be displayed
on the screen. The HI7188 Configuration Menu allows
the user to easily program the HI7188 configuration, load
preexisting configurations or quickly determine the current configuration. See the Configuration Menu description for details.
1
Set Chip Configuration: Entering 1 from the Configuration Menu allows the user to perform chip level configuration of the HI7188. The user is asked a series of
questions relating to the HI7188 Control Register bits.
After completing these questions, the user is given the
option of saving the information to a configuration file and
actually executing the configuration. If the user requests
writing a configuration file they are prompted to enter a
filename. If the users confirms execution of the configuration, the software compiles the proper data and writes
the Control Register, programming the HI7188 as
desired. Executing this command, regardless of options
chosen, returns the user to the Configuration menu. In
addition, entering c at any of the prompts immediately
returns the user to the Configuration menu.
2
Set Channel Configuration: Entering 2 from the Configuration Menu allows the user to program the channel(s)
specific configuration of the HI7188. The user is asked a
series of questions for each channel being converted. In
the logical conversion order the user is prompted for 1)
physical channel 2) unipolar/bipolar mode 3) operating/calibration mode and 4) gain. After completing these
questions, the user is given the option of saving the information to a configuration file and actually executing the
configuration. If the user requests writing a configuration
file they are prompted to enter a filename. If the users
confirms execution of the configuration, the software
compiles the proper data and writes the Channel Config-
Read Menu: Entering r from the Main Menu causes the
Read Menu to be displayed on the screen. The Read
Menu allows read access to all registers without having
knowledge of the specific instruction byte details. See
the Read Menu description for details.
w Write Menu: Entering 3 from the Main Menu causes the
Write Menu to be displayed on the screen. The Write
Menu allows write access to all registers without having
knowledge of the specific instruction byte details. See
the Write Menu description for details.
i
I/O Reset: Entering i from the Main Menu sends an
active low signal to the HI7188 RSTI/O pin, clearing the
Serial Interface Controller effectively aborting an ongoing
communication cycle. The Main Menu remains displayed
on the screen.
s
System Reset: Entering s from the Main Menu sends an
active low signal to the HI7188 RST pin, which initializes
the HI7188. The Main Menu remains displayed on the
screen.
x
Exit Program: Entering x from the Main Menu causes the
software to exit.
5
Application Note 9518
uration Register(s), programming the HI7188 as desired.
Executing this command returns the user to the Configuration menu. In addition, entering c at any of the prompts
immediately returns the user to the Configuration menu
3
4
5
6
Set Full Configuration: Entering 3 from the Configuration
Menu allows the user to fully program the configuration
of the HI7188 from a single menu pick. Choosing Set Full
Configuration is functionally equivalent to choosing Set
Chip Configuration followed by Set Channel Configuration. Executing this command returns the user to the
Configuration Menu.
Interpret File: Entering 4 from the Configuration Menu
allows the user to interpret a preset configuration file.
The user is prompted for a file name from which the software determines what configuration would occur if this
file were used to configure the HI7188. This information
is displayed on the screen. The first screen output displays the chip level configuration. Hit any key to continue
with the channel configuration information followed by
the calibration coefficients. The number of keystrokes
required to display all data in a configuration file is a
function of the configuration file contents. Executing this
command returns the user to the Configuration Menu.
Display/Save Current Configuration: Entering 5 from the
Configuration Menu allows the user to quickly determine
the present configuration of the HI7188. The software
completes a read of the Control Register, Channel Configuration Registers and all Calibration RAMs, then displays the information on the screen. The user is then is
given the option to save this configuration to a file. If saving to a file is selected, the user is prompted for a file
name and a header comment. Please see the Helpful
Hints Section of this document for a further explanation
on using the Display/Save command. Executing this
command returns the user to the Configuration Menu.
Restore Configuration: Entering 6 from the Configuration
Menu allows the user to configure the HI7188 from a file.
The user is prompted for a file name, from which the software executes the required communication cycles
required to configure the HI7188 as described. Executing
this command returns the user to the Configuration Menu.
Towards the bottom of the Configuration Menu are picks
that allow the user to quickly access the Main Menu,
Read Menu, and Write Menu.
m Main Menu: Entering m from the Configuration Menu
returns software execution to the Main Menu.
r
Read Menu: Entering r from the Configuration Menu
returns software execution to the Read Menu.
w Write Menu: Entering w from the Configuration Menu
returns software execution to the Write Menu.
i
I/O Reset: Entering i from the Configuration Menu sends
an active low signal to the HI7188 RSTI/O pin, clearing
the Serial Interface Controller effectively aborting an
ongoing communication cycle. The Configuration Menu
remains displayed on the screen.
s
Reset: Entering s from the Configuration Menu sends an
active low signal to the HI7188 RST pin, which initializes
6
the HI7188. The Configuration Menu remains displayed
on the screen.
Configuration Files
Configuration files are ASCII files that can be used to program the HI7188 using a single command. An example configuration file is shown below:
Comment lines can go anywhere
CNTL 0140
CCR2 17371737
CCR1 1737
ORAM 00000A 00000B 00000A 00000B 00000A 00000B
PRAM 00000C 00000D 00000C 00000D 00000C 00000D
NRAM 00000E 00000F 00000E 00000F 00000E 00000F
If the user invokes the restore configuration pick (6) of the
Configuration Menu and uses the file displayed above, the
following sequence occurs:
1. CNTL 0140: 0140 (hex) will be written to the Control Register. This will configure the part to convert on 6 channels
with line noise rejection disabled and the two’s complement data coding bit active.
2. CCR2 17371737: 17371737 (hex) will be written to the
CCR #2 Register. This will configure the HI7188 such that
the first and third logical channels converted in the 6 channel conversion scan will use physical channel 1, bipolar
mode, offset calibration mode and a gain select of 8. Also,
the second and fourth logical channels converted in the 6
channel conversion scan will use physical channel 2, bipolar mode, offset calibration mode and a gain select of 8.
3. CCR1 1737: 1737 (hex) will be written to the CCR#1 Register. This will configure the HI7188 such that the fifth logical channel converted in the 6 channel conversion scan
will use physical channel 1, bipolar mode, offset calibration
mode and a gain select of 8. Also, the sixth logical channel
converted in the 6 channel conversion scan will use physical channel 2, bipolar mode, offset calibration mode and a
gain select of 8.
4. ORAM 00000A 00000B 00000A 00000B 00000A 00000B:
00000A (hex) will be written to the first, third, and fifth logical offset RAM location. These offset coefficients would be
used for offset calibration of logical channels 1, 3, and 5
which are physically described by the CCR register contents. 00000B (hex) will be written to the second, fourth,
and sixth logical offset RAM location. These offset coefficients would be used for offset calibration of logical channels 2, 4, and 6 which are physically described by the CCR
register contents.
5. PRAM 00000C 00000D 00000C 00000D 00000C 00000D:
00000C (hex) will be written to the first, third, and fifth logical positive gain calibration RAM location. These coefficients would be used for gain calibration of positive input
voltages for logical channels 1, 3, and 5 which are physically described by the CCR register contents. 00000D
(hex) will be written to the second, fourth, and sixth logical
positive gain calibration RAM location. These coefficients
would be used for gain calibration of positive input voltages
for logical channels 2, 4, and 6 which are physically described by the CCR register contents.
Application Note 9518
6. NRAM 00000E 00000F 00000E 00000F 00000EC
00000F: 00000E (hex) will be written to the first, third, and
fifth logical negative gain calibration RAM location. These
coefficients would be used for gain calibration of negative
input voltages for logical channels 1, 3, and 5 which are
physically described by the CCR register contents. 00000F
(hex) will be written to the second, fourth, and sixth logical
negative gain calibration RAM location. These coefficients
would be used for gain calibration of negative input voltages for logical channels 2, 4, and 6, which are physically described by the CCR register contents.
1
Data RAM (quick read): Entering 1 from the Read Menu
invokes a read communication cycle with the Data RAM.
The data is displayed in binary (MSB to LSB format),
hex, and volts for each active channel being converted.
Touch any key to return execution to the Read Menu.
2
Data RAM: Entering 2 from the Read menu invokes a
read communication cycle with the Data RAM. The user
will be asked if a continuous read is required. If continuous read is not requested, a single Data RAM read will
occur and the software enters a “single step” read mode.
In this mode, entering [return] will execute another data
RAM read. This action continues until any key other than
[return] is entered at the prompt. Discontinuation of the
single step read mode returns the user to the Read
Menu. If a continuous read is requested, the software
inquires about saving the data to disc. If continuous read
without saving to disc is requested, the user is asked if
they would like data to be averaged and if so, how many
conversion results to average before displaying data (a
running average is maintained). See the Display of Data
RAM in Continuous Mode paragraph in the Software
Clarifications section of this document for details on what
is displayed whether averaging is requested or not. If the
user requests continuous reads and saving the data to
disc, details regarding file name, number of conversion
scans to store and data format are asked for. The reads
are completed and execution returns to the Read Menu.
See the Saving Conversion Results to a File paragraph
in the Software Clarifications section of this document for
details on the order of the prompts and other capabilities
3
Control Register: Entering 3 from the Read Menu invokes
a read communication cycle with the Control Register. The
data is displayed in hex, MSB to LSB format. Touch any
key to return execution to the Read Menu.
4
Channel Configuration Register #2: Entering 4 from the
Read Menu invokes a read communication cycle with the
Channel Configuration Register #2. The data is displayed in hex, MSB to LSB format. Touch any key to
return execution to the Read Menu.
5
Channel Configuration Register #1: Entering 5 from the
Read Menu invokes a read communication cycle with the
Channel Configuration Register #1. The data is displayed in hex, MSB to LSB format. Touch any key to
return execution to the Read Menu.
6
Offset Calibration RAM: Entering 6 from the Read Menu
invokes a read communication cycle with the Offset Calibration RAM. The data is displayed in hex, MSB to LSB
format, for each active channel being converted. Touch
any key to return execution to the Read Menu.
7
Positive Gain Calibration RAM: Entering 7 from the Read
Menu invokes a read communication cycle with the Positive
Gain Calibration RAM. The data is displayed in hex, MSB to
LSB format, for each active channel being converted. Touch
any key to return execution to the Read Menu.
8
Negative Gain Calibration RAM: Entering 8 from the Read
Menu invokes a read communication cycle with the Negative Gain Calibration RAM. The data is displayed in hex,
If the above configuration file were used to restore the HI7188
the part would convert physical channels 1 and 2 in alternating
sequence after a system offset calibration were performed. It is
up to the user to ensure that the offset calibration voltage is
applied to the HI7188 inputs before restoring this file.
Configuration files are ASCII files that may be generated with a
text editor of your choice or through the Configuration Menu. A
valid configuration file does not require all memory elements be
specified. That is, any number of the lines in the above example
could have been omitted. The software inspects the first field of
each line for a known key word. The key words are CNTL,
CCR2, CCR1, ORAM, PRAM, and NRAM. These key words
must be upper case. Any line that does not have one of these
key words in the first field is considered a comment line. It is
important that the CNTL line occur before the calibration
RAM lines as the software must know the active channel
count before accessing RAMs.
Please note that the calibration coefficients chosen for this
example are not realistic values and are used only for clarification in describing the contents of a configuration file.
Read Menu:
The Read Menu allows the user to quickly read the contents
of all accessible registers of the HI7188, without knowledge
of the instruction byte required.
Read Menu:
1 Data RAM (quick read)
2 Data RAM
3 Control Register
4 CCR #2
5 CCR #1
6 Offset RAM
7 Positive Gain RAM
8 Negative Gain RAM
9 Hex Input
Menu Select:
m Main Menu
c Configuration Menu
w Write Menu
Reset Select:
i I/O Reset
s System Reset
Enter Selection:
7
Application Note 9518
MSB to LSB format, for each active channel being converted. Touch any key to return execution to the Read Menu.
9
Hex Input: Entering 9 from the Read Menu invokes a
series of prompts allowing read access to any HI7188
Register. The user must know the instruction byte information for this command to be useful. The user will first
be asked to enter, in hex, the IR byte of the communication cycle. The IR byte entered will be analyzed. If a write
has been requested (from the Read Menu), an error
message is displayed and execution returns to the Read
Menu. If the IR byte entered is a valid read operation, the
data is displayed on the screen, in hex. Touch any key to
return execution to the Read Menu.
Enter Selection:
1. No Data RAM Write Possible: Entering 1 or 2 from the Write
Menu is a no operation. The Data RAM is not writable.
3
Control Register: Entering 3 from the Write Menu invokes
a write communication cycle with the Control Register.
The user is prompted for the number of bytes to write and
the starting byte before being prompted for the data. The
software requires the data be entered in hex, most significant to least significant format, first byte to last byte order.
Recall that if the most significant byte is not chosen as the
starting byte, the data written will not be in MSB to LSB
format as input at the keyboard. Please see the Software
Clarifications Section for further details. If the user does
not fully understand the HI7188 Serial Interface functionality, it is advisable to use the Configuration Menu to write
the Control Register. When the I/O cycle has been completed, execution returns to the Write Menu.
4
Channel Configuration Register #2: Entering 4 from the
Write Menu invokes a write communication cycle with the
Channel Configuration Register #2. The user is
prompted for the number of bytes to write and the starting byte before being prompted for the data. The software requires the data be entered in hex, most
significant to least significant format, first byte to last byte
order. Recall that if the most significant byte is not chosen as the starting byte, the data written will not be in
MSB to LSB format as input at the keyboard. Please see
the Software Clarifications Section for further details. If
the user does not fully understand the HI7188 Serial
Interface functionality, it is advisable to use the Chip Configuration Menu to write the Channel Configuration Register #2. When the I/O cycle has been completed,
execution returns to the Write Menu.
5
Channel Configuration Register #1: Entering 5 from the
Write Menu invokes a write communication cycle with the
Channel Configuration Register #1. The user is
prompted for the number of bytes to write and the starting byte before being prompted for the data. The software requires the data be entered in hex, most
significant to least significant format, first byte to last byte
order. Recall that if the most significant byte is not chosen as the starting byte, the data written will not be in
MSB to LSB format as input at the keyboard. Please see
the Software Clarifications Section for further details. If
the user does not fully understand the HI7188 Serial
Interface functionality, it is advisable to use the Chip Configuration Menu to write the Channel Configuration Register #1. When the I/O cycle has been completed,
execution returns to the Write Menu.
6
Offset Calibration RAM: Entering 6 from the Write Menu
invokes a write communication cycle with the Offset Calibration RAM. The user will be prompted, per channel, to
enter the data to write. The number of channels prompted
for is determined by the CR<7:5> bits. The software
requires the data be entered in hex, most significant to
least significant format. An Offset Calibration RAM word is
3 bytes, all bytes must be entered at the prompt.
Towards the bottom of the Read Menu are picks that allow
the user to quickly access the Main Menu, Configuration
Menu, and Write Menu.
m Main Menu: Entering m from the Read Menu returns
software execution to the Main Menu.
c
Configuration Menu: Entering c from the Read Menu
returns software execution to the Configuration Menu.
w Write Menu: Entering w from the Read Menu returns
software execution to the Write Menu.
i
I/O Reset: Entering i from the Read Menu sends an
active low signal to the HI7188 RSTI/O pin, clearing the
Serial Interface Controller effectively aborting an ongoing
communication cycle. The Read Menu remains displayed on the screen.
s
Reset: Entering s from the Read Menu sends an active
low signal to the HI7188 RST pin, which initializes the
HI7188. The Read Menu remains displayed on the
screen.
Write Menu:
The Write Menu allows the user to quickly write data into all
accessible memory elements of the HI7188, without knowledge of the instruction byte required.
Write Menu:
1 Data RAM (No OP)
2 Data RAM (No OP)
3 Control Register
4 CCR #2
5 CCR #1
6 Offset RAM
7 Positive Gain RAM
8 Negative Gain RAM
9 Hex Input
Menu Select:
m Main Menu
c Configuration Menu
r Read Menu
Reset Select:
i
s
I/O Reset
System Reset
8
Application Note 9518
7
8
9
Positive Gain Calibration RAM: Entering 7 from the Write
Menu invokes a write communication cycle with the Positive Gain Calibration RAM. The user will be prompted,
per channel, to enter the data to write. The number of
channels prompted for is determined by the CR<7:5>
bits. The software requires the data be entered in hex,
most significant to least significant format. A Positive
Gain Calibration RAM word is 3 bytes, all bytes must be
entered at the prompt.
Negative Gain Calibration RAM: Entering 8 from the
Write Menu invokes a write communication cycle with the
Negative Gain Calibration RAM. The user will be
prompted, per channel, to enter the data to write. The
number of channels prompted for is determined by the
CR<7:5> bits. The software requires the data be entered
in hex, most significant to least significant format. A Negative Gain Calibration RAM word is 3 bytes, all bytes
must be entered at the prompt.
Hex Input: Entering 9 from the Write Menu invokes a
series of prompts allowing write access to any HI7188
Register. The user must know the instruction byte information for this command to be useful. The user will first
be asked to enter, in hex, the IR byte of the communication cycle. The IR byte entered will be analyzed. If a read
has been requested (from the Write Menu), an error
message is displayed and execution returns to the Write
Menu. If the IR byte entered is a write operation, the IR is
analyzed for register destination and the user is
prompted to input the data, in hex. The number of hex
digits required at the input prompt is a function of the
destination register and the instruction byte entered.
When the I/O cycle has been completed, execution
returns to the Write Menu.
Towards the bottom of the Write Menu are picks that allow
the user to quickly access the Main Menu, Configuration
Menu, and Read Menu.
Software Execution
The PORTADR.DAT file contains the port identification for
the parallel printer port interfacing the HI7188 Evaluation
Board to the PC. Check the printer port address you are
using and if required, update the PORTADR.DAT file. The
DOS MSD command can be used to find the printer port
address. Communication between the Evaluation Board
and the PC is not possible without the proper printer
port address in the PORTADR.DAT file.
Also on the diskette is the directory SRCCODE, which contains the evaluation software source code. The source code
was compiled with Borland’s Turbo C++, Version 3. The
project file used for compilation is 88EVAL.PRJ. If disc space
is limited, do not load this directory onto the PC disc.
Loading Software - Copy the four files (88EVAL.EXE,
TESTALL5.CFG, TESTALLA.CFG and PORTADR.DAT) from
the diskette onto your PC hard drive into the directory of your
choice. The file 88EVAL.EXE is the executable program. The
TEST*.CFG files are configuration files used during the
boot-up test. They must remain at the same hierarchial level
as the 88EVAL.EXE file.
Executing the Program - Change directory (cd) into the
directory containing the 88EVAL.EXE file. At the DOS
prompt type 88EVAL [return]. The software reminds the user
to apply power to the board before continuing with a
automatic test that checks the communication capability
between the PC and evaluation board. After completing this
test, the Main Menu is displayed and evaluation of the
HI7188 may continue.
If errors occur during the boot-up test routine, the on chip
memory element that cannot be read will be displayed on the
screen and the user must hit the return key for each failure to
complete the test. If errors occur, an incorrect printer port
identification is usually the problem.
m Main Menu: Entering m from the Write Menu returns
software execution to the Main Menu.
Software Clarifications
c
When programming the HI7188 configuration via the Configuration Menu entering c at any of the prompts will return the
user to the Configuration Menu. This feature is useful if an
undesired input is made allowing the user to quickly restart
configuring the product without having to answer any further
questions.
Configuration Menu: Entering c from the Write Menu
returns software execution to the Configuration Menu.
w Read Menu: Entering w from the Write Menu returns
software execution to the Read Menu.
i
s
I/O Reset: Entering i from the Write Menu sends an
active low signal to the HI7188 RSTI/O pin, clearing the
Serial Interface Controller effectively aborting an ongoing
communication cycle. The Write Menu remains displayed
on the screen.
Reset: Entering s from the Write Menu sends an active
low signal to the HI7188 RST pin, which initializes the
HI7188. The Write Menu remains displayed on the
screen.
9
Interrupting Configuration Menu Prompts
Active Channels Display
The upper right corner of the screen displays the current
number of active channels programmed into the DUT,
regardless of the current menu. This is helpful as a quick
check on the current configuration of the HI7188.
Application Note 9518
Writing the Control Register
Caution should be taken when writing the Control Register via
the Write Menu or Configuration Menu. The least significant
byte contains information regarding the serial interface configuration that must be maintained when running the software
provided. To ensure proper functionality of the evaluation software, the serial interface must be configured in MSB first
mode, descending byte order and bidirectional I/O pin operation. This configuration is maintained by writing logic zeros
into the 3 least significant bits of the Control Register.
Invalid Inputs
Entering invalid inputs at some menu prompts will lock up
the software. Generally a CTL-C will return the user to the
DOS prompt.
Software Defaults
Every effort has been made to ease data input when writing
the HI7188 memory elements. Default inputs have been
chosen and the latest input is recorded in memory and used
as the default the next time that prompt is issued. Its important to note that the defaults do not necessarily indicate the
current state of the HI7188 or the state of the HI7188 after a
power up reset. If the user is unsure of the current configuration of the HI7188, use the display/save current configuration
menu pick.
Bypassing Calibration
The HI7188 calibration algorithm can be effectively
bypassed by writing all zeros into the Offset Calibration RAM
and 800000 (hex) into the Positive and Negative Full Scale
Calibration RAMs. This causes zero offset and forces a gain
slope factor of 1.0. Please Note: If the calibration algorithm is
bypassed in this manner, the data displayed when reading
the Data RAM will convert the binary output to volts incorrectly. Without proper calibration, the HI7188 Evaluation
Software cannot be used to determine accurate voltage as
well as dynamic range and ENOB.
Write Menu Data Entry
When entering data from prompts of the Write Menu the
data must be entered in hex, MSB to LSB format with no
spaces. Error detection is provided for invalid hex digits. A
space or missing hex digit is flagged as an error and the user
is re-prompted for the data.
Reading the Configuration Registers
Recall that the Configuration Register bits associated with
the calibration mode automatically return to normal mode
after calibration is completed. If the user programs a calibration mode, then completes a read of the Configuration Menu
(or invokes a display/save current configuration), the operating mode bits usually will be in the normal mode due to the
fact that calibration is complete.
Saving Conversion Results to a File
Entering 2 from the Read Menu allows the user to save conversion results to a file. If the user requests continuous reads
and answers yes to the save to a file prompt, the following
sequence occurs: The user is prompted for the number of
10
conversion readings to save followed by the data format. The
user is then prompted as to whether a header should be
included in the file and is then prompted for the file name in
which the data is saved. If a header is requested, the user is
prompted for a one line comment. The complete header will
include a date stamp line, the current state of the Control Register, Configuration Registers and all calibration RAMs as well
as the one line comment. If no header is selected, only the
conversion result data is included in the file.
Choosing the Binary format writes the conversion results, in
binary, for each channel being converted. The first field of
each line is the logical channel number of that conversion
scan, while the second field is the data. The number of data
lines in the file is equal to the number of conversions the
user has requested to save times the number of logical
channels being converted.
Choosing the Hex format writes the conversion results, in
hex, for each channel being converted. The first field of each
line is the logical channel number of that conversion scan,
while the second field is the data. The number of data lines
in the file is equal to the number of conversions the user has
requested to save times the number of logical channels
being converted.
Choosing the Volts format writes the conversion results, in
volts, for each channel being converted. The first field of
each line is the logical channel number of that conversion
scan, while the second field is the data. The number of data
lines in the file is equal to the number of conversions the
user has requested to save times the number of logical
channels being converted. Please note, the conversion to
volts will not be accurate unless accurate calibration coefficients are used by the HI7188.
Choosing the Binary, Hex, Volts format writes the conversion results, in all three formats, for each channel being converted. The first field of each line is the logical channel
number of that conversion scan. The second, third and
fourth fields are the data in binary, hex and volts; respectively. The number of data lines in the file is equal to the
number of conversions the user has requested to save times
the number of logical channels being converted. Please
note, the conversion to volts will not be accurate unless
accurate calibration coefficients are used by the HI7188.
Display of Data RAM in Continuous Mode
Entering 2 from the Read Menu allows the user to request
continuous read of the Data RAM. If continuous read mode is
chosen, the user is asked if averaging is required and if so,
how many points to use while maintaining a running average.
If averaging is requested, the following information is displayed, per active channel: 1) The binary output stream read
from the HI7188, 2) The binary output stream converted to
hex, 3) The binary output stream converted to volts, 4) The
mean voltage of the last 10 conversion results, 5) The maximum voltage result, 6) the minimum voltage result, 7) The difference between the maximum voltage and minimum voltage,
and 8) standard deviation, dynamic range and ENOB, which
is updated in groups of 10 conversions. If averaging is not
requested, only the binary output, binary conversion to hex
and volts is displayed, per active channel:
Application Note 9518
NOTE: The CTRL input on the keyboard is used to “normalize” the
statistical output. For example, the maximum voltage is set to 5.5V
and the minimum is set to -5.5V. The maximum/minimum results displayed from then on will include only those conversions read since
“normalization”.
The Dynamic Range and ENOB Equations are as follows:
2
( 2.5 ) /2
Dynamic Range =10log 10 --------------------2
V RMS
Dynamic Range -1.76
ENOB = ----------------------------------------------------------6.02
V MAX – V MIN
V RMS = -----------------------------------6.6
Helpful Hints
Start with the Configuration Menu
Novice users should consider reviewing and exercising the
Configuration Menu picks first. The Configuration Menu
offers a wide range of functions that allow the user to quickly
program and report on the HI7188 configuration.
When programming the initial configuration, use pick 3. This
will prompt for both chip level and channel configuration
information. After the initial configuration is complete it is
generally useful to use picks 1 or 2 when making configuration revisions. Use of picks 1 or 2 allow chip level or channel
specific programming, respectively.
Make use of Configuration Files
Resetting the DUT
Entering s from the Main Menu resets the HI7188 to its initial
state. The initial state of the HI7188 is as follows: Convert 1 logical channel (physical channel 1, bipolar inputs, gain of 1, conversion mode), bypass line noise rejection filters. The serial
interface configuration is MSB first bit positioning, descending
byte order, bidirectional I/O Pin. This reset function is also
accessible from the sub-menus as previously described in the
Software Description Section of this document.
Resetting the I/O of DUT
Entering i from the Main Menu resets the HI7188 serial interface controller. This has no affect on the HI7188 configuration, only the synchronization of the serial interface is
affected. As this hardware and software has been tested and
I/O synchronization is automatically maintained, this menu
pick will seldom be used. This serial interface reset function
is also accessible from the sub-menus as previously
described in the Software Description Section of this document.
Understand and make use of the configuration file restore
capability. This capability allows the user to “fully” configure
the HI7188 with a single command.
Configuration files may be hand crafted with a text editor of
your choice or they may be generated via the Configuration
Menu. Recall that when the HI7188 is configured for a calibration mode that the CCR bits will return to normal mode automatically. Therefore, it is recommended that when using the
Configuration Menu to generate a configuration file, the user
save the configuration file before executing the command.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
11
C7
0.01µF
SMA1
U2
CLOCK
+5VD
L1
FOSC
SMA1
14
+5VD
V
DGND CC
C26
XTAL OSC
CAP
H1
L2
12
H2
TP1
L3
1 2 3
JP3
JMP3
1
H3
CON1
L4
H4
SDIO
SDO
L5
L6
MODE
H8
40
1
CS
MODE
39
2
SCLK RSTIO
38
3
EOS
SDO
37
4
A
SDIO
2
36
5
A1
OSC
1
35
6
A0
OSC2
34
7
MXC
DVDD
8
CA 33
DGND
RST 32
DGND 31
AVSS
VINL1
VINH1
VINL2
VINH2
VINL3
VINH3
VINL4
AVSS 30
AVDD 29
VRHI 28
VRLO 27
VCM 26
VINH8 25
VINL8 24
VINH7 23
VINL7 22
VINH6 21
L8
VINH4
H7
VINL5
L7
VINH5
VINL6
H6
Application Note 9518
SCLK
9
10
11
12
13
14
15
16
17
18
19
20
FIGURE 2. SCHEDULE 1 SCHEMATIC
H5
U3
HI7188IP
CS
RSTIO
+5V
C4
4.7µF AT 10V JP2
1
2
C2
3
JMP3
U1 2
0.01µF
R3
+V
6
C8
VOUT
50
5 R1
0.1µF
10K
TRIM
-V
REF
4
3 2 1
EOS
A2
A1
A0
C1
0.01µF
MXC
CA
RST
RS
+5VD
10
JP1
JP3
SMA 2
PC4
PINCON
-5V
VREFH
-5V
PC3
PINCON
C5
4.7µF AT 10V
+5V
SMA
VREFH
PC1
PC2
PINCON PINCON
PC5
PINCON
R2
R4
10
10
+5VD
C6
4.7µF AT 10V
Application Note 9518
VINL1
VINH1
VINL2
VINH2
VINL3
VINH3
VINL4
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
VINH4
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
J2
CON34A
VINL5
VINH5
VINL6
VINH6
VINL7
VINH7
VINL8
VINH8
J1
+5V
-5V
+5VD
1A
2A
3A
4A
5A
6A
7A
8A
9A
10A
11A
12A
13A
14A
15A
16A
17A
18A
19A
20A
21A
22A
D2
AB
2B
3B
4B
5B
6B
7B
8B
9B
10B
11B
12B
13B
14B
15B
16B
17B
18B
19B
20B
21B
22B
+5V
IN4000
D3
-5V
+5VD
IN4000
D1
IN4000
CONNECTOR
EDGE 44AB
FIGURE 2. SCHEDULE 1 SCHEMATIC (Continued)
13
J24
JMP2
R24
1
2K
2
-5V
TAP1
R23
TAP3
2K
1
2
14
J25
JMP2
VINX
P2
PIN
2
3
4 8
+
U12
6
OP27
VINL1
7 1
3
2
2
+5V
+5V
-5V
1
P4
PIN
VREFH
U11
6
7 1
+
-
1
J15
JMP2
2
VINH1
R25
2K
2
J22
JMP2
1
J20
JMP2
VINL2
2
OP27
4 8
1
2
1
2
1
J14
JMP2
J28
JMP2
J21
JMP2
2
1
1
J19
JMP2
2
R28
1
2K
2
2
1
R27
TAP4
2K
1
2
J27
JMP2
P3
PIN
P5
PIN
2
J29
JMP2
4 8
-
+
7 1
+
-
4 8
2
1
J4
JMP2
2
VINH5
2
OP27
1
R34
23.7K
6
-5V
J15
JMP2
1
C32
0.01µ
R37
10K
C9
0.01µF
2
1
J5
JMP2
1
1
1
J10
JMP2
1
J12
JMP2
VINL7
2
J9
JMP2
VINL8
2
VINH7
2
J8
JMP2
J7
JMP2
VINH6
2
1
J11
JMP2
VINH8
2
1
J13
JMP2
FIGURE 3. SCHEDULE 2 SCHEMATIC
C33
0.01µ
C34
0.01µ
C35
0.01µ
BYPASS CAPS FOR OP AMPS
J6
JMP2
VINL6
2
R33
10K
4
VINL5
U14
6
R29
2K
TAP4
+5V
7 1
3
2
TAP2
VOUT 5
TRIM
-4
U10
REF
J17
JMP2
U13
6
OP27
+5V
+5V
-5V
1
2
3
R35
2.49K
+V
J16
JMP2
-5V
TAP2
VINY
1
R32
4.99K
J18
JMP2
VINH4
J26
JMP2
TAP3
VMINUS
VINL4
VINH3
2
TAP1
-5V
C36
0.01µ
C37
0.01µ
C38
0.01µ
C39
0.01µ
Application Note 9518
1
R36
23.7K
VINL3
VINH2
2
R31
10K
VREFH
VREFH
JP34
JMP3
R43
VREFH
VINH1
1 2 3
JP21
JMP3
R51
H1
C11
0.1µF
50
3 2 1
VREFH
JP18
JMP3
H5
C19
0.1µF
50
3 2 1
VINH5
1 2 3
JP15
JMP3
15
JP35
JMP3
R44
3 2 1
JP19
JMP3
1 2 3
JP32
JMP3
R45
3 2 1
JP12
JMP3
H2
VINH6
1 2 3
H6
C21
0.1µF
50
Application Note 9518
J16
JMP3
L5
JP23
JMP3
R53
3 2 1
VINL5
1 2 3
C20
0.1µF
50
VINH2
1 2 3
C13
0.1µF
50
JP20
JMP3
R52
L1
C12
0.1µF
50
3 2 1
VINL1
JP14
JMP3
JP33
JMP3
R46
3 2 1
J17
JMP3
R48
J15
JMP3
50
1 2 3
VINL3
JP17
JMP3
R42
JP16
JMP3
50
JP27
R56 JMP3
H4
C17
0.1µF
50
3 2 1
J12
JMP3
H7
JP24
JMP3
L3
3 2 1
1 2 3
1 2 3
3 2 1
J13
JMP3
50
JP29
JMP3
1 2 3
C18
0.1µF
VINL4
VINH8
H8
C24
0.1µF
3 2 1
FIGURE 4. SCHEDULE 3 SCHEMATIC
JP19
JMP3
JP26
JMP3
1 2 3
VINL8
L8
R57
L4
VINL7
L7
C10
0.1µF
JP18
JMP3
R50
VINH7
1 2 3
C23
0.1µF
50
VINH4
1 2 3
L6
JP25
JMP3
R55
3 2 1
VINL6
1 2 3
C22
0.1µF
50
H3
C16
0.1µF
50
JP28
R49 JMP3
3 2 1
JP31
JMP3
JP13
JMP3
VINH3
1 2 3
C15
0.1µF
50
J14
JMP3
3 2 1
3 2 1
JP30
JMP3
R47
JP22
JMP3
R54
L2
C14
0.1µF
50
3 2 1
VINL2
1 2 3
50
C25
0.1µF
U8B
74HC125
BYPASS CAPS FOR DIGITAL DEVICES
+5VD
5
C28
C27
C29
C30
C31
0.01µ
0.01µ
0.01µ
0.01µ
0.01µ
TP3
6
1
R18
10K
4
R17
10K
R16
10K
R15
10K
R14
10K
R13
10K
CA
MXC
EOS
16
EOS
SCLK
CS
U6C
74HC04
RSTIO
MODE
A1
A0
12
13 U6F
74HC04
A1
2Y4 2A4
2Y3 2A3
2Y2 2A2
2Y1 2A1
1Y4 1A4
1Y2 1A3
1Y3 1A2
1Y1 1A1
74HC244
1
2
3
4
5
6
7
8
U6D
74HC04
U6E
74HC04
EOS
P1
TP6
1 CON1
TP5
1
U5
TP4
SDO
2
2G
1G
1
U7A
74HC125
3
5
7
9
12
14
16
18
CON1
3
SDO
U6A
74HC04
R7
10K
2
1
1
2Y4
2Y3
2Y2
2Y1
1Y4
1Y3
1Y2
1Y1
2A4
2A3
2A2
2A1
1A4
1A3
1A2
1A1
19
1
17
15 A1
13
11 A2
8
6
4
2
74HC244
+5VD
6
CONNECTOR DB25
U8D
74HC125
U7B
74HC125
R9
10K
11
R22
10K
12
5
SDIO
+5VD
R20
10K
13
25
12
24
11
23
10
22
9
21
8
20
7
19
6
18
5
17
4
16
3
15
2
14
1
A0
CON1
16
15
14
13
12
11
10
9
SDO
11
10
U4
SOCKET_16
TP7
1 CON1
TP2
1 CON1
9
8
A2
3
5
7
9
12
14
16
18
19
1
17
15
13
11
8
6
4 A0
2
Application Note 9518
A2
2G
1G
5
6
RST
U9
+5VD
CON1
13
2 1
J3
JMP2
9
U8C
74HC125
8
10
+5VD
4
U7C
74HC125
9
8
10
R10
10K
R12
10K
13
12
U6B
4
3
11
U7D
74HC125
R11
10K
R8
10K
R6
10K
+5VD
R19
10K
R21
10K
2
1
3
U8A
74HC125
74HC04
FIGURE 5. SCHEDULE 4 SCHEMATIC
Application Note 9518
TABLE 1. PARTS LIST
ITEM
QUANTITY
REFERENCE
PART
1
19
C1, C2, C3, C7, C9, C26, C27, C28, C29, C30, C31, C32,
C33, C34, C35, C36, C37, C38, C39
0.01µF
2
3
C4, C5, C6
10µF at 10V
3
18
C8, C10, C11, C12, C13, C14, C15, C16, C17, C18, C19,
C20, C21, C22, C23, C24, C25, C26
0.1µF
4
3
D1, D2, D3
1N4001
5
62
JP1, JP2, JP3, JP4, JP5, JP6, JP7, JP8, JP9, JP10, JP11,
JP12, JP13, JP14, JP15, JP16, JP17, JP18, JP19, JP20,
JP21, JP22, JP23, JP24, JP25, JP26, JP27, JP28, JP29,
JP30, JP31, JP32, JP33, JP34, JP35, J3, J4, J5, J6, J7, J8,
J9, J10, J11, J12, J13, J14, J15, J16, J17, J18, J19, J20,
J21, J22, J23, J24, J25, J26, J27, J28, J29
JMP2, JMP3
6
1
J1
CONNECTOR EDGE44AB
7
1
J2
CON34A
8
1
P1
CONNECTOR DB25
9
2
R1, R37
10K
10
17
R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17,
R18, R19, R20, R21, R22
10K
11
17
R3, R42, R43, R44, R45, R46, R47, R48, R49, R50, R51,
R52, R53, R54, R55, R56, R57
49.9
12
3
R2, R4, R5
10
13
4
R23, R24, R25, R27, R28, R29
2.0K
14
2
R26, R30
2.0K
15
2
R31, R33
10K
16
1
R32
4.99K
17
2
R34, R36
23.7K
18
1
R35
2.49K
19
2
SMA1, SMA2
SMA
20
2
U1, U10
LT1019CN8-2.5
21
1
U2
XTAL OSCILLATOR
22
1
U3
HI7188IP
23
2
U5, U9
74HC244
24
1
U6
74HC04
25
2
U7, U8
74HC125
26
4
U11, U12, U13, U14
HA5170
27
1
Y1
CRYSTAL
28
42
Shunts
29
6
Bumpers
30
1
Cable
31
136
32
3
Pin Sockets
14 Pin IC sockets
17
18
Application Note 9518
FIGURE 6. COMPONENTS LAYOUT
FIGURE 7. COMPONENT SIDE
Application Note 9518
19
FIGURE 8. GROUND PLANES
Application Note 9518
20
FIGURE 9. POWER PLANES
Application Note 9518
21
FIGURE 10. SOLDER SIDE
Application Note 9518
22
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