DATASHEET

12-Bit Differential Input 200kSPS SAR ADC
ISL267817
Features
The ISL267817 is a 12-bit, 200kSPS sampling SAR-type ADC
which features excellent linearity over supply and temperature
variations, and provides a drop-in compatible alternative to all
ADS7817 performance grades. The robust, fully-differential
input offers high impedance to minimize errors due to leakage
currents, and the specified measurement accuracy is
maintained with input signals up to the supply rails.
• Drop-In Compatible with ADS7817 (All Performance Grades)
The reference accepts inputs between 0.1V to 2.5V, providing
design flexibility in a wide variety of applications. The
ISL267817 also features up to 8kV Human Body Model ESD
survivability.
The serial digital interface is SPI compatible and is easily
interfaced to popular FPGAs and microcontrollers. Operating
from a 5V supply, power dissipation is 2.15mW at a sampling
rate of 200kSPS, and just 25µW between conversions utilizing
the Auto Power-Down mode, making the ISL267817 an
excellent solution for remote industrial sensors and
battery-powered instruments. It is available in the compact,
industry-standard 8 Lead SOIC and MSOP packages and is
specified for operation over the industrial temperature range
(-40°C to +85°C).
• Differential Input
• Simple SPI-compatible Serial Digital Interface
• Guaranteed No Missing Codes
• 200kHz Sampling Rate
• +4.75V to +5.25V Supply
• Low 2.15mW Operating Power (200kSPS)
• Power-down Current between Conversions: 3µA
• Excellent Differential Non-Linearity (1.0LSB max)
• Low THD: -85dB (typ)
• Pb-Free (RoHS Compliant)
• Available in SOIC and MSOP Packages
Applications
• Remote Data Acquisition
• Battery Operated Systems
• Industrial Process Control
• Energy Measurement
• Data Acquisition Systems
• Pressure Sensors
• Flow Controllers
1.00
+VCC
0.75
DAC
VREF
0.50
0.25
+IN
SAR
LOGIC
–IN
SERIAL
INTERFACE
DCLOCK
0.00
DOUT
CS/SHDN
-0.25
VREF
DAC
-0.50
-0.75
GND
FIGURE 1. BLOCK DIAGRAM
April 19, 2012
FN7877.2
1
-1.00
0
512
1024 1536 2048 2560 3072 3584 4096
FIGURE 2. DIFFERENTIAL LINEARITY ERROR vs CODE
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2011, 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL267817
Typical Connection Diagram
VREF
+5V SUPPLY
+
VREF
REFP-P
+IN
REFP-P
–IN
GND
0.1µF +
10µF
+VCC
DCLOCK
µP/µC
DOUT
CS/SHDN
SERIAL
INTERFACE
Pin Configuration
ISL267817
(8 LD SOIC, MSOP)
TOP VIEW
VREF 1
Pin Descriptions
8 +VCC
+IN 2
7 DCLOCK
–IN 3
6 DOUT
GND 4
5 CS/SHDN
PIN NAME
PIN NUMBER
DESCRIPTION
VREF
1
Reference Input
+IN
2
Non Inverting Input
–IN
3
Inverting Input
GND
4
Ground
CS/SHDN
5
Low = Chip Select, High = Shutdown
DOUT
6
Serial Output Data
DCLOCK
7
Data Clock
+VCC
8
Power Supply
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
+VCC RANGE
(V)
TEMP RANGE
(°C)
PACKAGE
PKG.
DWG. #
ISL267817IBZ
267817 IBZ
4.75 to 5.25
-40°C to +85°C
8 Ld SOIC
M8.15
ISL267817IUZ
67817
4.75 to 5.25
-40°C to +85°C
8 Ld MSOP
M8.118
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for the ISL267817. For more information on MSL please see tech brief
TB363.
2
FN7877.2
April 19, 2012
ISL267817
Table of Contents
Typical Connection Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
ADC Transfer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Reference Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Down/Standby Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dynamic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Static Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Short Cycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power vs Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
11
12
13
13
13
13
13
13
Serial Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Application Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Grounding and Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Package Outline Drawing (M8.15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Package Outline Drawing (M8.118). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3
FN7877.2
April 19, 2012
ISL267817
Absolute Maximum Ratings
Thermal Information
Any Pin to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.0V
Analog Input to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +VCC+0.3V
Digital I/O to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +VCC+0.3V
Digital Input Voltage to GND . . . . . . . . . . . . . . . . . . . . . .-0.3V to +VCC+0.3V
Maximum Current In to Any Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
ESD Rating
Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . . . 8kV
Machine Model (Tested per JESD22-A115B) . . . . . . . . . . . . . . . . . 400V
Charged Device Model (Tested per JESD22-C101E). . . . . . . . . . . . 1.5kV
Latch Up (Tested per JESD78C; Class 2, Level A) . . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
8 Ld SOIC Package (Notes 4, 5). . . . . . . . . .
120
64
8 Ld MSOP Package (Notes 4, 5). . . . . . . . .
165
64
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
5. For θJC, the “case temp” location is taken at the package top center.
Electrical Specifications
+VCC = +5V, fDCLOCK = 3.2MHz, fS = 200kSPS, VREF = 2.5V; VCM = VREF, Typical values are at TA = +25°C.
Boldface limits apply over the operating temperature range, -40°C to +85°C.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 6)
MAX
(Note 6)
UNITS
-VREF
+VREF
V
TYP
ANALOG INPUT (Note 7)
|AIN|
Full-Scale Input Span
+IN – (–IN)
Absolute Input Voltage
+IN
-0.3
+VCC +0.3
V
–IN
-0.3
+VCC +0.3
V
CVIN
Input Capacitance
ILEAK
Input DC Leakage Current
Sample/Hold Mode
13/6
-1
0.01
pF
1
µA
SYSTEM PERFORMANCE
N
Resolution
12
Bits
No Missing Codes
12
Bits
INL
Integral Nonlinearity
-1
DNL
Differential Nonlinearity
-1
±0.4
1
LSB
Zero-Code Error
-6
±0.25
6
LSB
GAIN
Gain Error
-4
±0.12
4
LSB
CMRR
Common-Mode Rejection
80
dB
PSRR
Power Supply Rejection
82
dB
OFFSET
±0.5
1
LSB
SAMPLING DYNAMICS
tCONV
Conversion Time
tACQ
Acquisition Time
fmax
Throughput Rate
fDCLOCK = 3.2MHz
12
1.5
Clk Cycles
Clk Cycles
200
kSPS
DYNAMIC CHARACTERISTICS
THD
Total Harmonic Distortion
VIN = 5.0VP-P at fIN = 1kHz
-85
dB
VIN = 5.0VP-P at fIN = 5kHz
-84
dB
SINAD
Signal-to (Noise + Distortion) Ratio
VIN = 5.0VP-P at fIN = 1kHz
71
dB
SFDR
Spurious Free Dynamic Range
VIN = 5.0VP-P at fIN = 1kHz
85
dB
Full Power Bandwidth
At –3dB
15
MHz
BW
4
FN7877.2
April 19, 2012
ISL267817
Electrical Specifications
+VCC = +5V, fDCLOCK = 3.2MHz, fS = 200kSPS, VREF = 2.5V; VCM = VREF, Typical values are at TA = +25°C.
Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
2.5
V
REFERENCE INPUT
VREF
VREFLEAK
VREF Input Range
0.1
Current Drain
-100
4
100
µA
-20
0.23
20
µA
-3
0.01
3
µA
fSAMPLE = 12.5kHz
CS/SHDN = +VCC
DIGITAL INPUT/OUTPUT
Logic Family
CMOS
VIH
Input High Voltage
3
+VCC + 0.3
V
VIL
Input Low Voltage
-0.3
0.8
V
VOH
Output High Voltage
IOH = –250µA
VOL
Output Low Voltage
IOL = 250µA
3.5
V
0.4
Output Coding
ILEAK
Two’s Complement
Input Leakage Current
CIN
Input Capacitance
IOZ
Floating-State Output Current
COUT
V
-1
1
µA
10
pF
-1
1
Floating-State Output Capacitance
µA
5
pF
POWER REQUIREMENTS
VCC
Supply Voltage Range
ICC
Supply Current
4.75
430
Power Down Current
5.25
V
800
µA
fSAMPLE = 12.5kHz (Notes 8, 9)
38
µA
fSAMPLE = 12.5kHz (Note 9)
223
µA
CS/SHDN = +VCC, fSAMPLE = 0Hz
0.5
3
µA
+85
°C
TEMPERATURE RANGE
Specified Performance
-40
NOTES:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
7. The absolute voltage applied to each analog input must be between GND and +VCC to guarantee datasheet performance.
8. fDCLOCK = 3.2MHz, CS/SHDN = +VCC for 241 clock cycles out of every 256.
9. See “Power vs Throughput Rate” on page 13 for more information regarding lower sample rates.
Timing Specifications
Limits established by characterization and are not production tested. +VCC = 5V, fDCLOCK = 3.2MHz, fS = 200kSPS,
VREF = 2.5V; VCM = VREF. Boldface limits apply over the operating temperature range, -40°C to +85°C.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 6)
TYP
1.5
MAX
(Note 6)
UNITS
2.0
Clk Cycles
tSMPL
Analog Input Sample Time
tCONV
Conversion Time
fCYC
Throughput Rate
tCSD
CS/SHDN Falling Edge to DCLOCK Low
tSUCS
CS/SHDN Falling Edge to DCLOCK Rising Edge
30
ns
thDO
DCLOCK Falling Edge to Current DOUT Not Valid
15
ns
12
5
Clk Cycles
200
kHz
0
ns
FN7877.2
April 19, 2012
ISL267817
Timing Specifications
Limits established by characterization and are not production tested. +VCC = 5V, fDCLOCK = 3.2MHz, fS = 200kSPS,
VREF = 2.5V; VCM = VREF. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
SYMBOL
PARAMETER
MIN
(Note 6)
TEST CONDITIONS
tdDO
DCLOCK Falling Edge to Next DOUT Valid
tDIS
CS/SHDN Rising Edge to DOUT Disable Time
tEN
TYP
MAX
(Note 6)
UNITS
35
150
ns
40
50
ns
DCLOCK Falling Edge to DOUT Enabled
22
100
ns
tf
DCLOCK Fall Time
1
100
ns
tr
DCLOCK Rise Time
1
100
ns
See Note 10
NOTE:
10. During characterization, tDIS is measured from the release point with a 10pF load (see Figure 4) and the equivalent timing using the ADS7817 loading
(3kΩ, 100pF) is calculated.
tCYC
CS/SHDN
POWER
DOWN
tSUCS
DCLOCK
tCSD
Hi-Z
DOUT
tSMPL
NULL
B11 B10
BIT
(MSB)
NULL
BIT
Hi-Z
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
B11
B10
B9
B8
Note 11
tCONV
tDATA
tCYC
CS/SHDN
POWER
DOWN
tSUCS
DCLOCK
tCSD
Hi-Z
DOUT
tSMPL
NULL
B11 B10
BIT
(MSB)
Hi-Z
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10 B11
Note 12
tCONV
tDATA
NOTES:
11. After completing the data transfer, additional clocks applied while CS/SHDN is low will result in the previous data being retransmitted LSB-first,
followed by indefinite transmission of zeros.
12. After completing the data transfer, additional clocks applied while CS/SHDN is low will result in indefinite transmission of zeros.
FIGURE 3. SERIAL INTERFACE TIMING DIAGRAM
+VCC
RL
2.85kΩ
OUTPUT
PIN
CL
10pF
FIGURE 4. EQUIVALENT LOAD CIRCUIT
6
FN7877.2
April 19, 2012
ISL267817
VIL = 0.8V
50%
DCLOCK
DCLOCK
tEN
DOUT
50%
CS/SHDN
tSUCS
thDO
DOUT
DCLOCK
50%
VOH = VDD - 0.2V
VOL = 0.4V
VIL = 0.8V
VIH = 2.4V
DCLOCK
50%
CS/SHDN
CS/SHDN
tDIS
tCSD
thDO
DOUT
DCLOCK
DOUT
10%
VOL = 0.4V
50%
FIGURE 5. TIMING PARAMETER DEFINITIONS
7
FN7877.2
April 19, 2012
ISL267817
Typical Performance Characteristics
fCLK = 16 * fSAMPLE, unless otherwise specified.
TA = +25°C, VCC = 5V, VREF = 2.5V, fSAMPLE = 200kHz,
1.2
2.5
OFFSET ERROR CHANGE
FROM 20°C (LSB)
OFFSET ERROR (LSB)
2.0
1.5
1.0
0.5
0.0
-0.5
-1.0
-1.5
-2.0
-2.5
1.00
1.20
1.40
1.60
1.80
2.00
2.20
0.8
0.4
0.0
-0.4
-0.8
-1.2
-50
2.40
-30
REFERENCE VOLTAGE (V)
0.15
GAIN ERROR CHANGE
FROM 20°C (LSB)
GAIN ERROR (LSB)
0.20
1.5
1.0
0.5
0.0
-0.5
-1.0
-1.5
1.40
1.60
1.80
2.00
2.20
0.00
-0.05
-0.10
-0.15
-30
-10
10
30
50
70
90
FIGURE 9. CHANGE IN GAIN vs TEMPERATURE
POWER SUPPLY REJECTION (dB)
11.5
ENOB (BITS)
90
TEMPERATURE (°C)
12.0
11.0
10.5
10.0
9.5
10.0
REFERENCE VOLTAGE (V)
FIGURE 10. EFFECTIVE NUMBER OF BITS vs REFERENCE VOLTAGE
8
70
0.05
-0.20
-50
2.40
FIGURE 8. CHANGE IN GAIN vs REFERENCE VOLTAGE
1.0
50
0.10
REFERENCE VOLTAGE (V)
9.0
0.1
30
FIGURE 7. CHANGE IN OFFSET vs TEMPERATURE
2.0
1.20
10
TEMPERATURE (°C)
FIGURE 6. CHANGE IN OFFSET vs REFERENCE VOLTAGE
-2.0
1.00
-10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
1
10
100
1k
RIPPLE FREQUENCY (Hz)
FIGURE 11. POWER SUPPLY REJECTION vs RIPPLE FREQUENCY
FN7877.2
April 19, 2012
ISL267817
Typical Performance Characteristics
fCLK = 16 * fSAMPLE, unless otherwise specified. (Continued)
TA = +25°C, VCC = 5V, VREF = 2.5V, fSAMPLE = 200kHz,
0
73
-20
72
SNR & SINAD (dB)
AMPLITUDE (dBFS)
SNR
-40
-60
-80
71
70
SINAD
69
-100
-120
0
68
25
50
75
67
1
100
10
FREQUENCY (kHz)
FIGURE 12. FREQUENCY SPECTRUM (8192 POINT FFT;
fIN = 9.9kHz, –0.5dB
FIGURE 13. SIGNAL-TO-NOISE RATIO AND SIGNAL-TO(NOISE+DISTORTION) vs INPUT FREQUENCY
95
-95
80
90
-90
70
85
-85
80
-80
THD
75
-75
70
-70
SINAD (dB)
60
THD (dB)
SFDR (dB)
SFDR
50
40
30
20
65
1
-65
100
10
10
0
-60
-50
-40
-30
-20
-10
0
INPUT LEVEL (dB)
INPUT FREQUENCY (kHz)
FIGURE 14. SPURIOUS FREE DYNAMIC RANGE AND TOTAL
HARMONIC DISTORTION vs INPUT FREQUENCY
DELTA FROM fSAMPLE = 200kHz (LSB)
100
INPUT FREQUENCY (kHz)
1.5
FIGURE 15. SIGNAL-TO-(NOISE+DISTORTION) vs INPUT LEVEL
1.00
0.75
1.0
0.5
0.50
CHANGE IN INTEGRAL
LINEARITY (LSB)
0.25
0.00
CHANGE IN DIFFERENTIAL
LINEARITY (LSB)
-0.25
0.0
-0.50
-0.75
-0.5
0
80
160
240
320
400
-1.00
0
512
1024 1536 2048 2560 3072 3584 4096
SAMPLE RATE (kHz)
FIGURE 16. CHANGE IN INTEGRAL LINEARITY and DIFFERENTIAL
LINEARITY vs SAMPLE RATE
9
FIGURE 17. INTEGRAL LINEARITY ERROR vs CODE
FN7877.2
April 19, 2012
ISL267817
1.00
0.75
0.50
0.25
0.00
-0.25
-0.50
-0.75
-1.00
0
512
1024 1536 2048 2560 3072 3584 4096
TA = +25°C, VCC = 5V, VREF = 2.5V, fSAMPLE = 200kHz,
DELTA FROM 2.5V REFERENCE (LSB)
Typical Performance Characteristics
fCLK = 16 * fSAMPLE, unless otherwise specified. (Continued)
0.20
CHANGE IN INTEGRAL
LINEARITY (LSB)
0.15
0.10
0.05
0.00
CHANGE IN DIFFERENTIAL
LINEARITY (LSB)
-0.05
-0.10
-0.15
-0.20
1.00
1.25
1.50
1.75
2.00
2.25
2.50
REFERENCE VOLTAGE (V)
FIGURE 18. DIFFERENTIAL LINEARITY ERROR vs CODE
FIGURE 19. CHANGE IN INTEGRAL LINEARITY AND DIFFERENTIAL
LINEARITY vs REFERENCE VOLTAGE
600
SUPPLY CURRENT (µA)
LEAKAGE CURRENT (nA)
10
1
0.1
0.01
-50
-25
0
25
50
75
550
500
450
400
350
300
-50
100
TEMPERATURE (°C)
25
50
75
100
FIGURE 21. SUPPLY CURRENT vs TEMPERATURE
3.0
20
REFERENCE CURRENT (µA)
SUPPLY CURRENT (µA)
0
TEMPERATURE (°C)
FIGURE 20. INPUT LEAKAGE CURRENT vs TEMPERATURE
2.5
2.0
1.5
1.0
0.5
0.0
-50
-25
-25
0
25
50
75
100
TEMPERATURE (°C)
FIGURE 22. POWER DOWN SUPPLY CURRENT vs TEMPERATURE
10
15
10
5
0
0
80
160
SAMPLE RATE (kHz)
FIGURE 23. REFERENCE CURRENT vs SAMPLE RATE
(CODE = FF8h)
FN7877.2
April 19, 2012
ISL267817
Typical Performance Characteristics
fCLK = 16 * fSAMPLE, unless otherwise specified. (Continued)
TA = +25°C, VCC = 5V, VREF = 2.5V, fSAMPLE = 200kHz,
REFERENCE CURRENT (µA)
30
25
20
15
10
5
0
-50
-25
0
25
50
75
100
TEMPERATURE (°C)
FIGURE 24. REFERENCE CURRENT vs TEMPERATURE (CODE = FF8h)
The ISL267817 is based on a successive approximation register
(SAR) architecture utilizing capacitive charge redistribution
digital to analog converters (DACs). Figure 25 shows a simplified
representation of the converter. During the acquisition phase
(ACQ), the differential input is stored on the sampling capacitors
(CS). The comparator is in a balanced state since the switch
across its inputs is closed. The signal is fully acquired after tACQ
has elapsed, and the switches then transition to the conversion
phase (CONV) so the stored voltage may be converted to digital
format. The comparator will become unbalanced when the
differential switch opens and the input switches transition
(assuming that the stored voltage is not exactly at mid-scale).
The comparator output reflects whether the stored voltage is
above or below mid-scale, which sets the value of the MSB. The
SAR logic then forces the capacitive DACs to adjust up or down by
one quarter of full-scale by switching in binarily weighted
capacitors. Again, the comparator output reflects whether the
stored voltage is above or below the new value, setting the value
of the next lowest bit. This process repeats until all 12 bits have
been resolved.
A stable, low-noise reference voltage must be applied to the VREF
pin to set the full-scale input range and common-mode voltage. See
“Voltage Reference Input” on page 12 for more details.
ADC Transfer Function
The output coding for the ISL267817 is twos complement. The
first code transition occurs at successive LSB values (i.e., 1 LSB,
2 LSB, and so on). The LSB size is 2*VREF/4096. The ideal
transfer characteristic of the ISL267817 is shown in Figure 26.
011...111
1LSB = 2•VREF/4096
011...110
ADC CODE
Functional Description
000...001
000...000
111...111
100...010
100...001
100...000
DAC
–VREF
+ ½LSB
–IN
ACQ
ACQ
+VREF +VREF
– 1½LSB – 1LSB
ANALOG INPUT
+IN – (–IN)
FIGURE 26. IDEAL TRANSFER CHARACTERISTICS
CONV
+IN
0V
ACQ
CONV
SAR
LOGIC
CONV
DAC
VREF
Analog Input
The ISL267817 features a fully differential input with a nominal
full-scale range equal to twice the applied VREF voltage. Each
input swings VREF VP-P, 180° out-of-phase from one another for
a total differential input of 2*VREF (refer to Figure 27).
FIGURE 25. SAR ADC ARCHITECTURAL BLOCK DIAGRAM
An external clock must be applied to the DCLOCK pin to generate
a conversion result. The allowable frequency range for DCLOCK is
10kHz to 3.2MHz (625SPS to 200kSPS). Serial output data is
transmitted on the falling edge of DCLOCK. The receiving device
(FPGA, DSP or Microcontroller) may latch the data on the rising
edge of DCLOCK to maximize set-up and hold times.
11
VREF PP
+IN
ISL267817
VCM
VREF PP
–IN
FIGURE 27. DIFFERENTIAL INPUT SIGNALING
FN7877.2
April 19, 2012
ISL267817
Differential signaling offers several benefits over a single-ended
input, such as:
• Doubling of the full-scale input range (and therefore the
dynamic range)
• Improved even order harmonic distortion
VCM
5.0
4.0
4.0
3.0
2.8
• Better noise immunity due to common mode rejection
2.2
2.0
Figure 28 shows the relationship between the reference voltage
and the full-scale input range for two different values of VREF.
Note that there is a trade-off between VREF and the allowable
common mode input voltage (VCM). The full-scale input range is
proportional to VREF; therefore the VCM range must be limited
for larger values of VREF in order to keep the absolute maximum
and minimum voltages on the +IN and –IN pins within
specification. Figures 29 and 30 illustrate this relationship for
single-ended and differential inputs, respectively.
SIN G LE-EN D ED
1.0
0.0
-0.3
-1.0
0.5
1.0
1.5
2.0
2.5
FIGURE 29. RELATIONSHIP BETWEEN VREF AND VCM FOR
SINGLE-ENDED INPUTS (+VCC = 5V)
VCM
V
5.0
5.0
4.0
–IN
4.0
3.0
+IN
2.0Vpp
3.0
VCM
2.0
2.0
D IFFE R E N TIA L
1.0
0.95
0.0
1.0
t
VREF = 2V
-0.3
-1.0
0.5
1.0
1.5
2.0
2.5
FIGURE 30. RELATIONSHIP BETWEEN VREF AND VCM FOR
DIFFERENTIAL INPUTS (+VCC = 5V)
V
5.0
4.0
2.75
–IN
Voltage Reference Input
VCM
An external low-noise reference voltage must be applied to the VREF
pin to set the full-scale input range of the converter. The reference
input accepts voltages ranging from 0.1V to 2.5V; however the
device is specified with a reference voltage of 2.5V.
+IN
2.5Vpp
3.0
2.0
1.0
t
VREF = 2.5V
FIGURE 28. RELATIONSHIP BETWEEN VREF AND FULL-SCALE RANGE
12
Figures 31 and 32 illustrate possible voltage reference options
for the ISL267817. Figure 31 uses the precision ISL21090
voltage reference which exhibits exceptionally low drift and low
noise. The VREF input pin of the ISL267817 devices uses very low
current, so the decoupling capacitor can be small (0.1µF).
Figure 32 illustrates the ISL21010 voltage reference being used
with these ADCs. The ISL21010 series voltage references have
higher noise and drift than the ISL26090 devices, but they
consume very low operating current and are excellent for
battery-powered applications.
FN7877.2
April 19, 2012
ISL267817
+5V
+
BULK
0.1µF
0.1µF
1 DNC
DNC
8
2 VIN
DNC
7
3 COMP VOUT
6
4 GND
5
+VCC
ISL267817
VREF
2.5V
0.1µF
TRIM
ISL21090
FIGURE 31. PRECISION VOLTAGE REFERENCE
+5V
+
BULK
VIN
VOUT
1
0.1µF
GND
3
0.1µF
+VCC
ISL267817
VREF
2
1.25, 2.048 OR 2.5V
ISL21010
0.1µF
FIGURE 32. LOWER COST VOLTAGE REFERENCE
POWER-DOWN/STANDBY MODES
STATIC MODE
The mode of operation of the ISL267817 is selected by
controlling the logic state of the CS/SHDN signal during a
conversion. There are two possible modes of operation: dynamic
mode or static mode. When CS/SHDN is high (deasserted), the
ADC will be in static mode. Conversely, when CS/SHDN is low
(asserted), the device will be in dynamic mode. There are no
minimum or maximum number of DCLOCK cycles required to
enter static mode, which simplifies power management and
allows the user to easily optimize power dissipation versus
throughput for different application requirements.
The ISL267817 enters the power-saving static mode
automatically any time CS/SHDN is deasserted. It is not required
that the user force a device into this mode following a conversion
in order to optimize power consumption.
DYNAMIC MODE
This mode is entered when a conversion result is desired by
asserting CS/SHDN. Figure 33 shows the general diagram of
operation in this mode. The conversion is initiated on the falling
edge of CS/SHDN, as described in the “Serial Digital Interface”
section on page 14. As soon as CS/SHDN is brought high, the
conversion will be terminated and DOUT will go back into
three-state. Sixteen serial clock cycles are required to complete
the conversion and access the complete conversion result.
CS/SHDN may idle high until the next conversion or idle low until
sometime prior to the next conversion. Once a data transfer is
complete, i.e., when DOUT has returned to three-state, another
conversion can be initiated by again bringing CS/SHDN low.
CS/SHDN
DCLOCK
DOUT
10
1
NULL BIT AND CONVERSION RESULT
FIGURE 33. NORMAL MODE OPERATION
13
16
SHORT CYCLING
In cases where a lower resolution conversion is acceptable,
CS/SHDN can be pulled high before 12 DCLOCK falling edges
have elapsed. This is referred to as short cycling, and it can be
used to further optimize power dissipation. In this mode, a lower
resolution result will be acquired, but the ADC will enter static
mode sooner and exhibit a lower average power dissipation than
if the complete conversion cycle were carried out. The acquisition
time (tACQ) requirement must be met for the next conversion to
be valid.
POWER-ON RESET
The ISL267817 performs a power-on reset when the supplies are
first activated, which requires approximately 2.5ms to execute.
After this is complete, a single dummy cycle must be executed in
order to initialize the switched capacitor track and hold. A
dummy cycle will take 5μs with an 3.2MHz DCLOCK. Once the
dummy cycle is complete, the ADC mode will be determined by
the state of CS/SHDN. At this point, switching between dynamic
and static modes is controlled by CS/SHDN with no delay
required between states.
POWER vs THROUGHPUT RATE
The ISL267817 provides reduced power consumption at lower
conversion rates by automatically switching into a low-power
mode after completing a conversion. Maximum power savings
are achieved by running SCLK at the maximum rate, as shown in
Figure 34. If SCLK is operated at a fixed 16x multiple of the
FN7877.2
April 19, 2012
ISL267817
sample rate then the average power consumption of the ADC is
roughly constant, decreasing somewhat at lower throughput
rates (Figure 35).
The shutdown current is impacted by the state of the CS/SHDN
pin, as shown in Figure 36.
SUPPLY CURRENT (µA)
1000
TA= +25°C
VCC = 5V
VREF = 2.5V
fCLK = 3.2MHz
100
10
1
1
10
100
1k
SAMPLE RATE (kHz)
FIGURE 34. POWER CONSUMPTION vs SAMPLE RATE, fCLK = 3.2MHz
Serial Digital Interface
Conversion data is accessed with an SPI-compatible serial
interface. The interface consists of the data clock (DCLOCK),
serial data output (DOUT), and chip select/shutdown (CS/SHDN).
A falling edge on the CS/SHDN signal initiates a conversion by
placing the part into the acquisition (ACQ) phase. After tACQ has
elapsed, the part enters the conversion (CONV) phase and begins
outputting the conversion result starting with a null bit followed
by the most significant bit (MSB) and ending with the least
significant bit (LSB). The CS/SHDN pin can be pulled high at this
point to put the device into Standby mode and reduce the power
consumption. If CS/SHDN is held low after the LSB bit has been
output, the conversion result will be repeated in reverse order
until the MSB is transmitted, after which the serial output enters
a high impedance state. The ISL267817 will remain in this state,
dissipating typical dynamic power levels, until CS/SHDN
transitions high then low to initiate the next conversion.
Data Format
Output data is encoded in two’s complement format, as shown in
Table 1. The voltage levels in the table are idealized and don’t
account for any gain/offset errors or noise.
TABLE 1. TWO’S COMPLEMENT DATA FORMATTING
SUPPLY CURRENT (µA)
1000
100
10
TA= +25°C
VCC = 5V
VREF = 2.5V
fCLK= 16 • fSAMPLE
1
1
10
100
1k
60
50
SUPPLY CURRENT (µA)
DIGITAL OUTPUT
–Full Scale
–VREF
1000 0000 0000
–Full Scale + 1LSB
–VREF+ ½ LSB
1000 0000 0001
Midscale
0
0000 0000 0000
+Full Scale – 1LSB
+VREF– 1½ LSB
0111 1111 1110
+Full Scale
+VREF – ½ LSB
0111 1111 1111
40
30
Signal-to-(Noise + Distortion) Ratio (SINAD)
This is the measured ratio of signal-to-(noise + distortion) at the
output of the ADC. The signal is the RMS amplitude of the
fundamental. Noise is the sum of all non-fundamental signals up
to half the sampling frequency (fs/2), excluding DC. The ratio
is dependent on the number of quantization levels in the
digitization process; the more levels, the smaller the quantization
noise. The theoretical signal-to-(noise + distortion) ratio for an
ideal N-bit converter with a sine wave input is given by
Equation 1:
FIGURE 35. SHUTDOWN CURRENT vs SAMPLE RATE,
fCLK = 16 • fSAMPLE
CSB = HIGH
(VCC)
Signal-to-(Noise + Distortion) = ( 6.02 N + 1.76 )dB
(EQ. 1)
Thus, for a 12-bit converter this is 74dB, and for a 10-bit this is
62dB.
CSB = LOW
(GND)
10
0
1
VOLTAGE
TERMINOLOGY
SAMPLE RATE (kHz)
20
INPUT
Total Harmonic Distortion
10
100
SAMPLE RATE (kHz)
FIGURE 36. SHUTDOWN CURRENT vs SAMPLE RATE
1k
Total harmonic distortion (THD) is the ratio of the RMS sum of
harmonics to the fundamental. For the ISL267817, it is defined
as Equation 2:
V 22 + V 32 + V 42 + V 52 + V 62
THD ( dB ) = 20 log ----------------------------------------------------------------------V 12
14
(EQ. 2)
FN7877.2
April 19, 2012
ISL267817
where V1 is the RMS amplitude of the fundamental and V2, V3,
V4, V5, and V6 are the RMS amplitudes of the second to the sixth
harmonics.
Peak Harmonic or Spurious Noise (SFDR)
Peak harmonic or spurious noise is defined as the ratio of the
RMS value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding DC) to the RMS value of
the fundamental. Also referred to as Spurious Free Dynamic
Range (SFDR). Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, it will be
a noise peak.
Full Power Bandwidth
The full power bandwidth of an ADC is that input frequency at
which the amplitude of the reconstructed fundamental is
reduced by 3dB for a full-scale input.
Common-Mode Rejection Ratio (CMRR)
The common-mode rejection ratio is defined as the ratio of the
power in the ADC output at full-scale frequency, f, to the power of
a 250mVP-P sine wave applied to the common-mode voltage of
+IN and –IN of frequency fs:
CMRR ( dB ) = 10 log ( Pfl ⁄ Pfs )
(EQ. 3)
Pf is the power at the frequency f in the ADC output; Pfs is the
power at frequency fs in the ADC output.
Integral Nonlinearity (INL)
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function.
Differential Nonlinearity (DNL)
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Zero-Code Error
This is the deviation of the midscale code transition (111...111 to
000...000) from the ideal +IN – (–IN) (i.e., 0 LSB).
Gain Error
This is the deviation of the first code transition (100...000 to
100...001) from the ideal +IN – (–IN) (i.e., – VREF + ½ LSB) or the
last code transition (011...110 to 011...111) from the ideal +IN –
(–IN) (i.e., +VREF – 1½ LSB), after the zero code error has been
adjusted out.
Power Supply Rejection Ratio (PSRR)
The power supply rejection ratio is defined as the ratio of the
power in the ADC output at full-scale frequency, f, to ADC +VCC
supply of frequency fS. The frequency of this input varies from
1kHz to 1MHz.
PSRR ( dB ) = 10 log ( Pf ⁄ Pfs )
(EQ. 4)
Pf is the power at frequency f in the ADC output; Pfs is the power
at frequency fs in the ADC output.
Application Hints
Grounding and Layout
The printed circuit board that houses the ISL267817 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. This facilitates the
use of ground planes that can be easily separated. A minimum
etch technique is generally best for ground planes since it gives
the best shielding. Digital and analog ground planes should be
joined in only one place, and the connection should be a star
ground point established as close to the GND pin on the
ISL267817 as possible. Avoid running digital lines under the
device, as this will couple noise onto the die. The analog ground
plane should be allowed to run under the ISL267817 to avoid
noise coupling.
The power supply lines to the device should use as large a trace
as possible to provide low impedance paths and reduce the
effects of glitches on the power supply line.
Fast switching signals, such as clocks, should be shielded with
digital ground to avoid radiating noise to other sections of the
board, and clock signals should never run near the analog inputs.
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
reduces the effects of feedthrough through the board. A
microstrip technique is by far the best but is not always possible
with a double-sided board.
In this technique, the component side of the board is dedicated
to ground planes, while signals are placed on the solder side.
Good decoupling is also important. All analog supplies should be
decoupled with 10μF tantalum capacitors in parallel with 0.1μF
capacitors to GND. To achieve the best from these decoupling
components, they must be placed as close as possible to the
device.
Track and Hold Acquisition Time
The track and hold acquisition time is the minimum time
required for the track and hold amplifier to remain in track mode
for its output to reach and settle to within 0.5 LSB of the applied
input signal.
15
FN7877.2
April 19, 2012
ISL267817
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
CHANGE
March 19, 2012
FN7877.2
Renamed in Figure 1 pin names to match package pinout names
Electrical Spec Table Reference Input on page 5 changed “REF” to “VREF”
Modified text in Figures 31 and 32 by renaming Figure titles from “Precision Voltage Reference for +5V Supply”
to “Precision Voltage Reference” and “Voltage Reference for +2.7V to +3.6V or for +5V” to “Lower Cost Voltage
Reference”, Changed pin names VDD to +VCC, Removed +2.7V to +3.5V and leaving +5V in Figure 32
Removed “+” from VREF capacitor in “Typical Connection Diagram” on page 2.
Replaced last sentence of 1st paragraph, 2nd paragraph and graphic in “Voltage Reference Input” on page 12.
Removed “Applications Information” section
M8.15 - Updated to latest revision - Changed Note 1 "1982" to "1994"
December 14, 2011
FN7877.1
Pg 1, Added mention of MSOP package to last paragraph of description and last Features bullet.
Pg 2, Removed "Coming Soon" for ISL267817IUZ package in Ordering Information table.
Changed "(8 LD SOIC)" to "(8 LD SOIC, MSOP)" in the Pin Configuration
Pg 18, Inserted latest M8.118 POD at the end of the document
October 28, 2011
FN7877.0
Initial Release
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16
FN7877.2
April 19, 2012
ISL267817
Package Outline Drawing
M8.15
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 1/12
DETAIL "A"
1.27 (0.050)
0.40 (0.016)
INDEX
6.20 (0.244)
5.80 (0.228)
AREA
0.50 (0.20)
x 45°
0.25 (0.01)
4.00 (0.157)
3.80 (0.150)
1
2
8°
0°
3
0.25 (0.010)
0.19 (0.008)
SIDE VIEW “B”
TOP VIEW
2.20 (0.087)
SEATING PLANE
5.00 (0.197)
4.80 (0.189)
1.75 (0.069)
1.35 (0.053)
1
8
2
7
0.60 (0.023)
1.27 (0.050)
3
6
4
5
-C-
1.27 (0.050)
0.51(0.020)
0.33(0.013)
SIDE VIEW “A
0.25(0.010)
0.10(0.004)
5.20(0.205)
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensioning and tolerancing per ANSI Y14.5M-1994.
2. Package length does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
3. Package width does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
4. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
5. Terminal numbers are shown for reference only.
6. The lead width as measured 0.36mm (0.014 inch) or greater above the
seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch).
7. Controlling dimension: MILLIMETER. Converted inch dimensions are not
necessarily exact.
8. This outline conforms to JEDEC publication MS-012-AA ISSUE C.
17
FN7877.2
April 19, 2012
ISL267817
Package Outline Drawing
M8.118
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 7/11
5
3.0±0.05
A
DETAIL "X"
D
8
1.10 MAX
SIDE VIEW 2
0.09 - 0.20
4.9±0.15
3.0±0.05
5
0.95 REF
PIN# 1 ID
1
2
B
0.65 BSC
GAUGE
PLANE
TOP VIEW
0.55 ± 0.15
0.25
3°±3°
0.85±010
H
DETAIL "X"
C
SEATING PLANE
0.25 - 0.36
0.08 M C A-B D
0.10 ± 0.05
0.10 C
SIDE VIEW 1
(5.80)
NOTES:
(4.40)
(3.00)
1. Dimensions are in millimeters.
(0.65)
(0.40)
(1.40)
TYPICAL RECOMMENDED LAND PATTERN
18
2. Dimensioning and tolerancing conform to JEDEC MO-187-AA
and AMSEY14.5m-1994.
3. Plastic or metal protrusions of 0.15mm max per side are not
included.
4. Plastic interlead protrusions of 0.15mm max per side are not
included.
5. Dimensions are measured at Datum Plane "H".
6. Dimensions in ( ) are for reference only.
FN7877.2
April 19, 2012
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