DATASHEET

12-Bit, 20kSPS SAR ADC
ISL2671286
Features
The ISL2671286 is a sampling SAR-type ADC which features
excellent linearity over supply and temperature variations, and
provides a drop-in compatible alternative to all ADS1286
performance grades. The robust high impedance input
minimizes errors due to leakage currents, and specified
measurement accuracy is maintained with input signals up to
the supply rails.
• Drop-In Compatible with ADS1286 (All Performance Grades)
The reference accepts inputs between 1.25V to 5.0V, providing
design flexibility in a wide variety of applications. The
ISL2671286 also features up to 8kV Human Body Model ESD
survivability.
• Simple SPI-compatible Serial Digital Interface
• Guaranteed No Missing Codes
• 20kHz Sampling Rate
• +4.50V to +5.25V Supply
• Low 280µA Operating Current (20kSPS)
• Power-down Current between Conversions: 3µA
• Excellent Differential Non-Linearity (0.75LSB Max)
• Low THD: -83dB (Typ)
The serial digital interface is SPI compatible and is easily
interfaced to all popular FPGAs and microcontrollers.
Operating from a 5V supply, power dissipation is 1.4mW at a
sampling rate of 20kSPS and just 15µW between conversions
utilizing the Auto Power-Down mode. These features make the
ISL2671286 an excellent solution for remote industrial
sensors and battery-powered instruments.
• Pb-Free (RoHS Compliant)
The ISL2671286 is available in an 8 Ld SOIC package and is
specified for operation over the industrial temperature range
of –40°C to +85°C.
• Industrial Process Control
• Available in SOIC Package
Applications
• Remote Data Acquisition
• Battery Operated Systems
• Energy Measurement
• Data Acquisition Systems
• Pressure Sensors
• Flow Controllers
+VCC
DAC
VREF
+IN
SAR
LOGIC
VREF
DAC
–IN
SERIAL
INTERFACE
DCLOCK
DOUT
CS/SHDN
DIFFERENTIAL NONLINEARITY (LSB)
3
2
1
0
-1
-2
-3
GND
FIGURE 1. BLOCK DIAGRAM
November 1, 2011
FN7863.0
1
0
512
1024
1536
2048
CODE
2560
3072
3584
4096
FIGURE 2. DIFFERENTIAL LINEARITY ERROR vs CODE
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL2671286
Typical Connection Diagram
+5V SUPPLY
+
VREF
+
VREF
+IN
REFP-P
–IN
GND
0.1 F
+
10 F
+VCC
DCLOCK
P/ C
DOUT
CS/SHDN
SERIAL
INTERFACE
Pin Configuration
Pin Descriptions
ISL2671286
(8 LD SOIC)
TOP VIEW
VREF 1
8
+IN 2
7
+VCC
PIN NAME
PIN
NUMBER
VREF
1
Reference input
+IN
2
Non-inverting input
–IN
3
Inverting input. Connect to ground or remote
sense point.
GND
4
Ground
CS/SHDN
5
Chip select when low; shut-down mode when
high.
DOUT
6
Serial output data word comprises 12 bits of
data. In operation, data is valid on falling
edge of DCLOCK. Second clock pulse after
falling edge of CS/SHDN enables serial
output. After one null bit, data is valid for
next 12 edges.
DCLOCK
7
Data clock synchronizes serial data transfer.
+VCC
8
Power supply
DCLOCK
–IN 3
6
DOUT
GND 4
5
CS/SHDN
DESCRIPTION
Ordering Information
PART NUMBER
(Notes 1, 2)
PART MARKING
+VCC RANGE
(V)
TEMP RANGE
(°C)
ISL2671286IBZ (Note 3)
2671286 IBZ
4.50 to 5.25
-40°C to +85°C
8 Ld SOIC
M8.15
Coming Soon
ISL2671286IPZ
2671286 IPZ
4.50 to 5.25
-40°C to +85°C
8 Ld PDIP
E8.3
PACKAGE
PKG.
DWG. #
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL2671286. For more information on MSL please see Tech Brief TB363.
2
FN7863.0
November 1, 2011
ISL2671286
Absolute Maximum Ratings
Thermal Information
Any Pin to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.0V
Analog Input to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +VCC+0.3V
Digital I/O to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +VCC+0.3V
External Reference Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6V
Maximum Current In to Any Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
ESD Rating
Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . . . 8kV
Machine Model (Tested per JESD22-A115B) . . . . . . . . . . . . . . . . . 400V
Charged Device Model (Tested per JESD22-C101E). . . . . . . . . . . . .1.5kV
Latch Up (Tested per JESD78C; Class 2, Level A) . . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
8 Ld SOIC Package (Notes 4, 5). . . . . . . . . .
120
64
8 Ld PDIP Package (Notes 5, 6, 7) . . . . . . .
120
66
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+100°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
5. For θJC, the “case temp” location is taken at the package top center.
6. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
7. Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
Electrical Specifications +VCC = +5V, VREF = +5V, fSAMPLE = 12.5kHz, fCLK = 16 • fSAMPLE , unless otherwise noted. Typical
values are at TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 8)
MAX
(Note 8)
UNITS
0
VREF
V
TYP
ANALOG INPUT (Note 9)
|AIN|
CIN
ILEAK
Full-Scale Input Range
+IN – (–IN)
Absolute Input Voltage
+IN
-0.2
+VCC +0.2
V
–IN
-0.2
+0.2
V
Input Capacitance
Track/Hold mode
Input DC Leakage Current (Note 10)
19/1.8
-1
0.01
pF
1
µA
SYSTEM PERFORMANCE
N
Resolution
12
No Missing Codes
INL
Integral Linearity
DNL
Differential Linearity
Guaranteed no missed codes
Bits
12
Bits
-1
±0.5
1
LSB
-0.75
±0.4
0.75
LSB
Zero-Code Error
-3
±0.1
3
LSB
GAIN
Gain Error
-8
±0.2
8
LSB
PSRR
Power Supply Rejection
OFFSET
82
dB
SAMPLING DYNAMICS
tCONV
Conversion Time
tACQ
Acquisition Time
SSBW
12
1.5
Small Signal Bandwidth
Clk Cycles
Clk Cycles
320
kHz
AIN = 5.0VPP at fIN = 1kHz
-82
dB
AIN = 5.0VPP at fIN = 5kHz
-83
dB
DYNAMIC CHARACTERISTICS
THD
Total Harmonic Distortion
SINAD
Signal-to (Noise + Distortion) Ratio
AIN = 5.0VP-P at fIN = 1kHz
72
dB
SFDR
Spurious Free Dynamic Range
AIN = 5.0VP-P at fIN = 1kHz
83
dB
3
FN7863.0
November 1, 2011
ISL2671286
Electrical Specifications +VCC = +5V, VREF = +5V, fSAMPLE = 12.5kHz, fCLK = 16 • fSAMPLE , unless otherwise noted. Typical
values are at TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
SYMBOL
MIN
(Note 8)
TYP
MAX
(Note 8)
UNITS
1.25
2.5
VCC + 0.05
V
-2.5
0.01
2.5
µA
tCYC ≥ 640µs, fCLK ≤ 25kHz
0.06
20
µA
tCYC = 80µs, fCLK= 200kHz
0.5
20
µA
PARAMETER
TEST CONDITIONS
REFERENCE INPUT
REF
REFLEAK
REF Input Range
Current Drain
CS/SHDN = VCC
DIGITAL INPUT/OUTPUT
Logic Family
CMOS
VIH
Input High Voltage
3
+VCC
V
VIL
Input Low Voltage
0.0
0.8
V
VOH
Output High Voltage
IOH = 250µA
3
+VCC
V
VOL
Output Low Voltage
IOL = 250µA
0.0
0.4
V
1
µA
Data Format
ILEAK
Straight Binary
Input DC Leakage Current
CIN
Input Capacitance
IOZ
Floating-State Output Leakage
Current
COUT
-1
0.01
9
-1
pF
0.01
Floating-State Output Capacitance
1
µA
6
pF
POWER SUPPLY REQUIREMENTS
+VCC
Power Supply Voltage
VANA
Quiescent Current
4.50
Power Down
5
5.25
V
tCYC ≥ 640µs, fCLK ≤ 25kHz
280
500
µA
tCYC = 90µs, fCLK= 200kHz
360
600
µA
CS/SHDN = VCC
0.5
3
µA
+85
°C
TEMPERATURE RANGE
Specified Performance
-40
NOTES:
8. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
9. The absolute voltage applied to each analog input must be between GND and +VCC to guarantee datasheet performance.
10. Applies only to +IN.
Timing Specifications At fCLK = 200kHz , unless otherwise noted. Typical values are at TA = +25°C. Boldface limits apply over the
operating temperature range, -40°C to +85°C.
SYMBOL
tSMPL
tSMPL (MAX)
PARAMETER
Analog Input Sample Time
TEST CONDITIONS
See operating sequence; Figure 3
MIN
(Note 8)
TYP
1.5
Maximum Sampling Frequency
tCONV
Conversion Time
See operating sequence; Figure 3
12
tdDO
Delay Time, DCLOCK↓ to DOUT Data Valid
See test circuits; Figure 4
36
tDIS
Delay Time, CS/SHDN↑ to DOUT Hi-Z
See test circuits; Figure 4 (Note 11)
tEN
Delay Time, DCLOCK↓ to DOUT Enable
See test circuits; Figure 4
4
21
MAX
(Note 8)
UNITS
2.0
CLK
Cycles
20
kHz
CLK
Cycles
150
ns
50
ns
100
ns
FN7863.0
November 1, 2011
ISL2671286
Timing Specifications At fCLK = 200kHz , unless otherwise noted. Typical values are at TA = +25°C. Boldface limits apply over the
operating temperature range, -40°C to +85°C. (Continued)
SYMBOL
thDO
PARAMETER
TEST CONDITIONS
MIN
(Note 8)
TYP
15
30
MAX
(Note 8)
UNITS
Output Data Remains Valid After DCLOCK↓
CLOAD = 100pF
tf
DOUT Fall Time
See test circuits; Figure 4
1
100
ns
ns
tR
DOUT Rise Time
See test circuits; Figure 4
1
100
ns
tCSD
Delay Time, CS/SHDN↓ to DCLOCK↓
See operating sequence; Figure 3
0
ns
tSUCS
Delay Time, CS/SHDN↓ to DCLOCK↑
See operating sequence; Figure 3
30
ns
NOTE:
11. During characterization, tDIS is measured from the release point with a 10pF load (see Figure 4) and the equivalent timing using the ADS1286
loading (3kΩ, 100pF) is calculated.
tCYC
CS/SHDN
POWER
DOWN
tSUCS
DCLOCK
tCSD
DOUT
Hi-Z
Null
Bit
tSMPL
B11
B10
B9
B8
(MSB)
B7
B6
B5
B4
B3
B2
B1
Null
Bit
Hi-Z
(1)
B0
tCONV
B11
B10
B9
B8
tDATA
Note: (1) After completing the data transfer, additional clocks applied while CS/SHDN is low
will result in the previous data being retransmitted LSB-first, followed by indefinite
transmission of zeros
tCYC
CS/SHDN
POWER
DOWN
tSUCS
DCLOCK
tCSD
DOUT
Hi-Z
tSMPL
Null
Bit
Hi-Z
B11
(MSB)
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
B1
B2
B3
tCONV
B4
B5
B6
B7
B8
B9
B10
B11
(2)
tDATA
Note: (2) After completing the data transfer, additional clocks applied while CS/SHDN is low
will result in indefinite transmission of zeros
FIGURE 3. SERIAL INTERFACE TIMING DIAGRAM
+VCC
RL
2.85k
OUTPUT PIN
CL
10pF
FIGURE 4. EQUIVALENT LOAD CIRCUIT
5
FN7863.0
November 1, 2011
ISL2671286
VIL = 0.8V
50%
DCLOCK
DCLOCK
tEN
DOUT
50%
CS/SHDN
tSUCS
thDO
DOUT
DCLOCK
50%
VOH = VDD - 0.2V
VOL = 0.4V
VIL = 0.8V
VIH = 2.4V
DCLOCK
50%
CS/SHDN
CS/SHDN
tDIS
tCSD
thDO
DOUT
DCLOCK
DOUT
10%
VOL = 0.4V
50%
FIGURE 5. TIMING PARAMETER DEFINITIONS
6
FN7863.0
November 1, 2011
ISL2671286
Typical Performance Characteristics
otherwise specified.
At TA = +25°C, +VCC = VREF = 5V, fSAMPLE = 12.5kHz, fCLK = 16 * fSAMPLE, unless
2.5
4.0
REFERENCE CURRENT (µA)
REFERENCE CURRENT (µA)
3.5
2.0
1.5
1.0
0.5
0.0
0
2
4
6
8
SAMPLE RATE (kHz)
10
2.5
2.0
1.5
1.0
0.5
0.0
-55
12
FIGURE 6. REFERENCE CURRENT vs SAMPLE RATE
5.0
1.0
4.5
0.8
4.0
0.6
3.5
3.0
2.5
2.0
1.5
1.0
0.5
-15
5
25
45
TEMPERATURE (°C)
65
85
105
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
0.0
1
2
3
4
REFERENCE VOLTAGE (V)
-1.0
-55
5
FIGURE 8. CHANGE IN OFFSET vs REFERENCE VOLTAGE
0.5
0.0
0.4
-0.5
0.3
0.2
CHANGE IN DNL (LSB)
0.1
0.0
-0.1
-0.2
1
-35
-15
5
25
45
TEMPERATURE (°C)
65
85
105
FIGURE 9. CHANGE IN OFFSET vs TEMPERATURE
CHANGE IN GAIN (LSB)
DELTA FROM +5V REFERENCE (LSB)
-35
FIGURE 7. REFERENCE CURRENT vs TEMPERATURE
DELTA FROM 25°C (LSB)
CHANGE IN OFFSET (LSB)
3.0
-1.0
-1.5
-2.0
-2.5
-3.0
-3.5
CHANGE IN INL (LSB)
-4.0
2
3
4
REFERENCE VOLTAGE (V)
5
FIGURE 10. CHANGE IN INTEGRAL LINEARITY AND DIFFERENTIAL
LINEARITY vs REFERENCE VOLTAGE
7
1
2
3
4
REFERENCE VOLTAGE (V)
5
FIGURE 11. CHANGE IN GAIN vs REFERENCE VOLTAGE
FN7863.0
November 1, 2011
ISL2671286
Typical Performance Characteristics
At TA = +25°C, +VCC = VREF = 5V, fSAMPLE = 12.5kHz, fCLK = 16 * fSAMPLE, unless
otherwise specified. (Continued)
3
DIFFERENTIAL NONLINEARITY (LSB)
EFFECTIVE NUMBER OF BITS (BITS)
12.0
11.5
11.0
10.5
10.0
9.5
9.0
8.5
8.0
7.5
0.1
0
-1
-2
10.0
0
100
100
90
90
80
80
70
70
60
50
40
30
60
10
0
0.1
10.0
2560
3072
3584
4096
SPURIOUS FREE DYNAMIC RANGE
SIGNAL-TO-NOISE RATIO
1.0
FREQUENCY (kHz)
10.0
FIGURE 15. SPURIOUS FREE DYNAMIC RANGE AND
SIGNAL-TO-NOISE RATIO vs FREQUENCY
0
TOTAL HARMONIC DISTORTION (dB)
80
70
60
50
40
30
20
10
0
-40
2048
CODE
30
10
FIGURE 14. SIGNAL-TO-(NOISE + DISTORTION) vs FREQUENCY
1536
40
20
1.0
FREQUENCY (kHz)
1024
50
20
0
0.1
512
FIGURE 13. DIFFERENTIAL LINEARITY ERROR vs CODE
SFDR AND SNR (dB)
SIGNAL-TO-(NOISE + DISTORTION) (dB)
1
-3
1.0
REFERENCE VOLTAGE (V)
FIGURE 12. EFFECTIVE NUMBER OF BITS vs REFERENCE VOLTAGE
SIGNAL-TO-(NOISE + DISTORTION) (dB)
2
-35
-30
-25
-20
-15
INPUT LEVEL (dB)
-10
-5
0
FIGURE 16. SIGNAL-TO-(NOISE + DISTORTION) vs INPUT LEVEL
8
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0.1
1.0
FREQUENCY (kHz)
10.0
FIGURE 17. TOTAL HARMONIC DISTORTION vs FREQUENCY
FN7863.0
November 1, 2011
ISL2671286
Typical Performance Characteristics
At TA = +25°C, +VCC = VREF = 5V, fSAMPLE = 12.5kHz, fCLK = 16 * fSAMPLE, unless
otherwise specified. (Continued)
0
POWER SUPPLY REJECTION (dB)
0
MAGNITUDE (dB)
-25
-50
-75
-100
-125
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
2
4
1
6
10
FREQUENCY (kHz)
FIGURE 18. 4096 POINT FFT
100
1k
RIPPLE FREQUENCY (kHz)
10k
FIGURE 19. POWER SUPPLY REJECTION vs RIPPLE FREQUENCY
3.0
0.50
SUPPLY CURRENT (µA)
DELTA FROM 25°C (LSB)
2.5
0.25
0.00
-0.25
2.0
1.5
1.0
0.5
-0.50
-55
-35
-15
5
25
45
TEMPERATURE (°C)
65
85
0.0
-55
105
FIGURE 20. CHANGE IN GAIN vs TEMPERATURE
-15
5
25
45
TEMPERATURE (°C)
65
85
105
FIGURE 21. POWER-DOWN SUPPLY CURRENT vs TEMPERATURE
3
400
INTEGRAL NONLINEARITY (LSB)
450
SUPPLY CURRENT (µA)
-35
fSAMPLE = 12.5kHz
350
300
250
fSAMPLE = 1.6kHz
200
150
100
-55
2
1
0
-1
-2
-3
-35
-15
5
25
45
TEMPERATURE (°C)
65
85
FIGURE 22. SUPPLY CURRENT vs TEMPERATURE
9
105
0
512
1024
1536
2048
CODE
2560
3072
3584
4096
FIGURE 23. INTEGRAL LINEARITY ERROR vs CODE
FN7863.0
November 1, 2011
ISL2671286
Typical Performance Characteristics
At TA = +25°C, +VCC = VREF = 5V, fSAMPLE = 12.5kHz, fCLK = 16 * fSAMPLE, unless
3.0
10.0
2.5
LEAKAGE CURRENT (nA)
DIGITAL INPUT THRESHOLD VOLTAGE (V)
otherwise specified. (Continued)
2.0
1.5
1.0
0.5
0.0
3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25 5.50
SUPPLY VOLTAGE (V)
FIGURE 24. DIGITAL INPUT LINE THRESHOLD vs SUPPLY VOLTAGE
10
1.0
0.1
0.01
-55
-35
-15
5
25
45
TEMPERATURE (°C)
65
85
105
FIGURE 25. INPUT LEAKAGE CURRENT vs TEMPERATURE
FN7863.0
November 1, 2011
ISL2671286
Analog Input
The ISL2671286 is based on a successive approximation register
(SAR) architecture utilizing capacitive charge redistribution
digital-to-analog converters (DACs). Figure 26 shows a simplified
representation of the converter. During the acquisition phase
(ACQ), the differential input is stored on the sampling capacitors
(CS). The comparator is in a balanced state since the switch
across its inputs is closed. The signal is fully acquired after tACQ
has elapsed, and the switches then transition to the conversion
phase (CONV) so the stored voltage can be converted to digital
format. The comparator becomes unbalanced when the
differential switch opens and the input switches transition
(assuming that the stored voltage is not exactly at mid-scale).
The comparator output reflects whether the stored voltage is
above or below mid-scale, which sets the value of the MSB. The
SAR logic then forces the capacitive DACs to adjust up or down by
one-quarter of full-scale by switching in binarily weighted
capacitors. Again, the comparator output reflects whether the
stored voltage is above or below the new value and sets the value
of the next lowest bit. This process repeats until all 12 bits have
been resolved.
The ISL2671286 features a pseudo-differential input with a
nominal full-scale range equal to the applied VREF voltage. The
negative input (VIN–) must be biased within 200mV of ground.
DAC
Functional Description
CONV
VIN+
VIN–
ACQ
ACQ
ACQ
SAR
LOGIC
CONV
CONV
Modes of Operation
There are two possible modes of operation, which are controlled
by the CS/SHDN signal. When CS/SHDN is high (deasserted), the
ADC is in static mode. Conversely, when CS/SHDN is low
(asserted), the device is in dynamic mode. There is no minimum
or maximum number of SCLK cycles required to enter static
mode. This simplifies power management and allows the user to
easily optimize power dissipation versus throughput for various
application requirements.
DYNAMIC MODE
This mode is entered when a conversion result is desired by
asserting CS/SHDN. Figure 28 shows the general operation in
this mode. The conversion is initiated on the falling edge of
CS/SHDN (refer to “Serial Digital Interface” section). When
CS/SHDN is deasserted, the conversion is terminated, and DOUT
returns to a high-impedance state. Sixteen serial clock cycles are
required to complete the conversion and access the complete
conversion result. CS/SHDN may idle high until the next
conversion or idle low until sometime prior to the next
conversion. Once a data transfer is complete (DOUT has returned
to a high-impedance state), another conversion can be initiated
by again asserting CS/SHDN.
CSB
DAC
VREF
SCLK
1
10
16
FIGURE 26. SAR ADC ARCHITECTURAL BLOCK DIAGRAM
ADC Transfer Function
DOUT
The output coding for the ISL2671286 is straight binary. The first
code transition occurs at successive LSB values (i.e., 1 LSB, 2
LSB, and so on). The LSB size is VREF/4096. The ideal transfer
characteristic of the ISL2671286 is shown in Figure 27.
1LSB = VREF/4096
111...111
ADC CODE
111...110
4 LEADING ZEROS AND CONVERSION RESULT
FIGURE 28. NORMAL MODE OPERATION
STANDBY MODE
The ISL2671286 enters the power-saving static mode
automatically any time CS/SHDN is deasserted. The user is not
required to force a device into this mode following a conversion
in order to optimize power consumption.
SHORT CYCLING
100...001
100...000
011...111
000...010
000...001
000...000
0V
+VREF +VREF
– 1½LSB – 1LSB
+½LSB
ANALOG INPUT
+IN – (–IN)
FIGURE 27. IDEAL TRANSFER CHARACTERISTICS
11
In cases where a lower resolution conversion is acceptable,
CS/SHDN can be pulled high before 12 SCLK falling edges have
elapsed. This is referred to as short cycling, and it can be used to
further optimize power dissipation. In this mode, a lower
resolution result is acquired, but the ADC enters static mode
sooner and exhibits a lower average power dissipation than if the
complete conversion cycle is carried out. The acquisition time
(tACQ) requirement must be met for the next conversion to be
valid.
POWER-ON RESET
The ISL2671286 performs a power-on reset that requires
approximately 2.5ms to execute when the supplies are first
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ISL2671286
activated. After reset is complete, a single dummy cycle lasting
one conversion must be executed to initialize the switched
capacitor track and hold. Once the dummy cycle is complete, the
ADC mode is determined by the state of CS/SHDN. At this point,
switching between dynamic and static modes is controlled by
CS/SHDN, with no delay required between states.
POWER vs THROUGHPUT RATE
The ISL2671286 power consumption is reduced slightly at lower
conversion rates. Figure 29 shows the typical power consumption
over a wide range of throughput rates.
SUPPLY CURRENT (µA)
1000
conversion process and frames the data transfer. The falling
edge of CS/SHDN puts the track-and-hold into hold mode and
takes the bus out of three-state. The analog input is sampled and
the conversion initiated at this point.
The conversion result from the ISL2671286 is provided on DOUT
output as a serial data stream. The bits are clocked out on the
falling of the SCLK input. The output coding is two’s complement.
Applications Information
Analog Input Filtering
A low-pass, anti-alias filter is recommended to optimize
performance, as shown in Figure 31. The capacitive input
switching currents are averaged into a net DC current by CFILT. It
is recommended that a high-quality capacitor with low voltage
and temperature coefficients, such as C0G/NP0, be used. A
small series resistance value minimizes voltage drops across the
resistor.
100
10
RFILT
TA = 25°C
VCC = +5V
VREF = +5V
fCLK = 16 x fSAMPLE
1
0.1
IDC
VIN
+IN
CFILT
1.0
10
SAMPLE RATE (kHz)
ISL2671286
100
–IN
FIGURE 29. SUPPLY CURRENT vs SAMPLE RATE
6
SUPPLY CURRENT (µA)
5
TA = 25°C
VCC = +5V
VREF = +5V
fCLK = 16 x fSAMPLE
FIGURE 31. INPUT FILTERING
Reduced Reference Operation
4
3
The ISL2671286 exhibits good linearity and gain over a wide
range of reference voltages (see Figures 10 and 11). When
operating at low values of VREF, offset errors and noise must be
considered because of the reduced LSB size.
CSB = LOW
(GND)
2
1
CSB = HIGH
(VCC)
0
0.1
1.0
10
SAMPLE RATE (kHz)
100
FIGURE 30. SHUTDOWN CURRENT vs SAMPLE RATE
Serial Digital Interface
The ISL2671286 communicates using a 3-wire serial interface.
DCLOCK synchronizes the data transfer, with each bit
transmitted on the falling DCLOCK edge and captured on the
rising DCLOCK edge in the receiving system. A falling CS/SHDN
initiates data transfer, as shown in Figure 3. After CS/SHDN falls,
the second DCLOCK pulse enables DOUT. After one null bit, the
A/D conversion result is output on the DOUT line. Bringing
CS/SHDN high resets the ISL2671286 for the next data
exchange.
Figure 3 shows a detailed timing diagram for the serial interface.
The serial clock provides the conversion clock and controls the
transfer of data during conversion. CS/SHDN initiates the
12
Input errors can have a larger impact on performance when
operating the ADC with a reduced reference voltage, since LSB
size is proportional to VREF. Figure 8 shows how the offset in
LSBs is related to reference voltage for a typical value of VOS. For
example, a VOS of 100µV is 0.082 LSB with a 5V reference. If
VREF is reduced to 1V, the same 100µV offset is 0.41 LSB, and it
increases to 2.05 LSB with a 0.2V reference. The offset can be
corrected digitally after conversion, or an opposing bias can be
applied to the –IN pin (within the allowable range according to
the “Electrical Specifications”).
Similarly, total input referred noise appears as a larger fraction of
an LSB when operating at reduced VREF values. Attention should
be paid to the output noise of the driving amplifier, and proper
filtering should be applied to limit the noise that aliases in the
Nyquist zone. Averaging multiple readings can improve
performance if the application conditions allow.
Grounding and Layout
The printed circuit board that houses the ISL2671286 should be
designed so that the analog and digital sections are separated
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ISL2671286
and confined to certain areas of the board. This facilitates the
use of ground planes that can be separated easily. A minimum
etch technique is generally best for ground planes because it
gives the best shielding. Digital and analog ground planes should
be joined in only one place, and the connection should be a star
ground point established as close to the GND pin on the
ISL2671286 as possible. Avoid running digital lines under the
device, as this couples noise onto the die. The analog ground
plane should be allowed to run under the ISL2671286 to avoid
noise coupling.
Power supply lines to the device should use as large a trace as
possible, to provide low impedance paths and to reduce the
effects of glitches on the power supply line.
Fast switching signals, such as clocks, should be shielded with
digital ground to avoid radiating noise to other sections of the
board. Clock signals should never run near analog inputs. Avoid
crossover of digital and analog signals. Traces on opposite sides
of the board should run at right angles to each other. This
reduces the effects of feedthrough through the board.
A microstrip technique is by far the best but is not always
possible with a double-sided board. In this technique, the
component side of the board is dedicated to ground planes, while
signals are placed on the solder side.
Good decoupling is also important. All analog supplies should be
decoupled with 10μF tantalum capacitors in parallel with 0.1μF
capacitors to GND. To achieve the best performance from these
decoupling components, they must be placed as close as
possible to the device.
Terminology
Signal-to-(Noise + Distortion) Ratio (SINAD)
SINAD is the measured ratio of signal-to-(noise + distortion) at
the output of the ADC. The signal is the RMS amplitude of the
fundamental. Noise is the sum of all nonfundamental signals up
to half the sampling frequency (fs/2), excluding DC. The ratio is
dependent on the number of quantization levels in the
digitization process: the more levels, the smaller the quantization
noise. The theoretical signal-to-(noise + distortion) ratio for an
ideal N-bit converter with a sine wave input is given in Equation 1:
Signal-to-(Noise + Distortion) = ( 6.02 N + 1.76 )dB
(EQ. 1)
Peak Harmonic or Spurious Noise (SFDR)
Peak harmonic or spurious noise is defined as the ratio of the
RMS value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding DC) to the RMS value of the
fundamental. Also referred to as Spurious Free Dynamic Range
(SFDR), the value of this specification normally is determined by
the largest harmonic in the spectrum. For ADCs in which the
harmonics are buried in the noise floor, however, SFDR is a noise
peak.
Small-Signal Bandwidth
Small-signal bandwidth is the input frequency at which the
amplitude of the reconstructed fundamental is reduced by 3dB
for a signal whose peak-to-peak amplitude spans no more than
10% of the full-scale input range.
Integral Nonlinearity (INL)
Integral nonlinearity is the maximum deviation from a straight
line passing through the endpoints of the ADC transfer function.
Differential Nonlinearity (DNL)
Differential nonlinearity (DNL) is the difference between the
measured and the ideal 1 LSB change between any two adjacent
codes in the ADC.
Zero-Code Error
Zero-code error is the deviation of the first code transition
(000...000 to 000...001) from an ideal ½ LSB step.
Gain Error
Gain error is the deviation of the full-scale input (111...111) from
the ideal span (i.e., +VREF – 1LSB) after the zero code error has
been adjusted out.
Track-and-Hold Acquisition Time
Track-and-hold acquisition time is the minimum time required for
the track-and-hold amplifier to remain in track mode for its
output to reach and settle to within 0.5 LSB of the applied input
signal.
Power Supply Rejection Ratio (PSRR)
Power supply rejection ratio is the ratio of the power in the ADC
output at full-scale frequency, f, to ADC +VCC supply of frequency
fS (Equation 3). The frequency of this input varies from 1kHz to
1MHz.
Thus, for a 12-bit converter, the ratio is 74dB and for a 10-bit
converter is 62dB.
PSRR ( dB ) = 10 log ( Pf ⁄ Pfs )
Total Harmonic Distortion
Pf is the power at frequency f in the ADC output; Pfs is the power
at frequency fs in the ADC output.
Total harmonic distortion (THD) is the ratio of the RMS sum of
harmonics to the fundamental. For the ISL2671286, it is defined
as shown in Equation 2:
V 22 + V 32 + V 42 + V 52 + V 62
THD ( dB ) = 20 log ------------------------------------------------------------------V 12
(EQ. 3)
(EQ. 2)
where V1 is the RMS amplitude of the fundamental, and V2, V3,
V4, V5, and V6 are the RMS amplitudes of the second through the
sixth harmonic.
13
FN7863.0
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ISL2671286
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest revision.
DATE
REVISION
11/1/2011
FN7863.0
CHANGE
Initial Release
Products
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14
FN7863.0
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ISL2671286
Package Outline Drawing
M8.15
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 3, 3/11
DETAIL "A"
1.27 (0.050)
0.40 (0.016)
INDEX
6.20 (0.244)
5.80 (0.228)
AREA
0.50 (0.20)
x 45°
0.25 (0.01)
4.00 (0.157)
3.80 (0.150)
1
2
8°
0°
3
0.25 (0.010)
0.19 (0.008)
SIDE VIEW “B”
TOP VIEW
2.20 (0.087)
SEATING PLANE
5.00 (0.197)
4.80 (0.189)
1.75 (0.069)
1.35 (0.053)
1
8
2
7
0.60 (0.023)
1.27 (0.050)
3
6
4
5
-C-
1.27 (0.050)
0.51(0.020)
0.33(0.013)
SIDE VIEW “A
0.25(0.010)
0.10(0.004)
5.20(0.205)
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensioning and tolerancing per ANSI Y14.5M-1982.
2. Package length does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
3. Package width does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
4. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
5. Terminal numbers are shown for reference only.
6. The lead width as measured 0.36mm (0.014 inch) or greater above the
seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch).
7. Controlling dimension: MILLIMETER. Converted inch dimensions are not
necessarily exact.
8. This outline conforms to JEDEC publication MS-012-AA ISSUE C.
15
FN7863.0
November 1, 2011
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