DATASHEET

10-Bit and 12-Bit, 1MSPS SAR ADCs
ISL267440, ISL267450A
Features
The ISL267440 and ISL267450A are 10-bit and 12-bit, 1MSPS
sampling SAR-type ADCs featuring excellent linearity over supply
and temperature variations. These devices are drop-in
compatible with the AD7440 and AD7450A. The robust,
fully-differential input offers high impedance to minimize errors
due to leakage currents, and the specified measurement
accuracy is maintained with input signals up to the supply rails.
• Drop-in Compatible with AD7440, AD7450A
The reference accepts inputs from 0.1V to 2.2V for 3V operation
and 0.1V to 3.5V for 5V operation. This provides design flexibility
in a wide variety of applications. The ISL267440, ISL267450A
also feature up to 8kV Human Body Model ESD survivability.
• Differential Input
• Simple SPI-compatible Serial Digital Interface
• Guaranteed No Missing Codes
• 1MHz Sampling Rate
• 3V or 5V Operation
• Low Operating Current
- 1.25mA at 1MSPS with 3V Supplies
- 1.70mA at 1MSPS with 5V Supplies
The serial digital interface is SPI compatible and is easily
interfaced to popular FPGAs and microcontrollers. Power
dissipation is 8.5mW at a sampling rate of 1MSPS, and just 5µW
between conversions utilizing Auto Power-Down mode (with a 5V
supply). The ISL267440, ISL267450A are excellent solutions for
remote industrial sensors and battery-powered instruments.
• Power-down Current between Conversions: 1µA
The ISL267440, ISL267450A are available in an 8 lead MSOP
package, and are specified for operation over the Industrial
temperature range (–40°C to +85°C).
Applications
• Excellent Differential Non-Linearity
• Low THD: -83dB (typ)
• Pb-Free (RoHS Compliant)
• Available in MSOP Package
• Remote Data Acquisition
• Battery Operated Systems
• Industrial Process Control
• Energy Measurement
• Data Acquisition Systems
• Pressure Sensors
• Flow Controllers
1.0
0.8
0.6
0.4
VIN+
SAR
LOGIC
VIN–
SERIAL
INTERFACE
SCLK
SDATA
DNL (LSB)
VDD
DAC
VREF
0.2
0.0
-0.2
-0.4
CS
VREF
DAC
-0.6
-0.8
-1.0
GND
0
1024
2048
3072
4096
CODE
FIGURE 1. BLOCK DIAGRAM
June 28, 2012
FN7708.2
1
FIGURE 2. DIFFERENTIAL LINEARITY ERROR vs CODE
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2011, 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL267440, ISL267450A
Typical Connection Diagram
VREF
0.1µF
VREF
REFP-P
VIN+
REFP-P
VIN–
GND
+3V/5V
0.1µF + 10µF SUPPLY
VDD
SCLK
SDATA
µP/µC
CS
SERIAL
INTERFACE
Pin Configuration
ISL267440, ISL267450A
(8 LD MSOP)
TOP VIEW
VREF 1
8 VDD
VIN+ 2
7 SCLK
VIN– 3
6 SDATA
GND 4
5 CS
Pin Descriptions
ISL267440, ISL267450A
PIN NAME
PIN NUMBER
DESCRIPTION
VDD
8
Supply voltage, +2.7V to 5.25V.
SCLK
7
Serial clock input. Controls digital I/O timing and clocks the conversion.
SDATA
6
Digital conversion output.
CS
5
Chip select input. Generally controls the start of a conversion though not always the sampling signal.
GND
4
Ground
VIN–
3
Negative analog input.
VIN+
2
Positive analog input.
VREF
1
Reference voltage.
2
FN7708.2
June 28, 2012
ISL267440, ISL267450A
Ordering Information
PART NUMBER
(Note 4)
PART
MARKING
VDD RANGE
(V)
TEMP RANGE
(°C)
PACKAGE
PKG.
DWG. #
ISL267440IUZ (Note 3)
67440
2.7 to 5.25
-40 to +85
8 Ld MSOP
M8.118
ISL267440IUZ-T (Notes 1, 3)
67440
2.7 to 5.25
-40 to +85
8 Ld MSOP
M8.118
ISL267440IUZ-T7A (Notes 1, 3)
67440
2.7 to 5.25
-40 to +85
8 Ld MSOP
M8.118
ISL267450AIUZ (Note 3)
7450A
2.7 to 5.25
-40 to +85
8 Ld MSOP
M8.118
ISL267450AIUZ -T (Notes 1, 3)
7450A
2.7 to 5.25
-40 to +85
8 Ld MSOP
M8.118
ISL267450AIUZ -T7A (Notes 1, 3)
7450A
2.7 to 5.25
-40 to +85
8 Ld MSOP
M8.118
ISL267440IHZ-T (Notes 1, 2)
7440 (Note 5)
2.7 to 5.25
-40 to +85
8 Ld SOT-23
P8.064
ISL267440IHZ-T7A (Notes 1, 2)
7440 (Note 5)
2.7 to 5.25
-40 to +85
8 Ld SOT-23
P8.064
ISL267450AIHZ-T (Notes 1, 2)
450A (Note 5)
2.7 to 5.25
-40 to +85
8 Ld SOT-23
P8.064
ISL267450AIHZ-T7A (Notes 1, 2)
450A (Note 5)
2.7 to 5.25
-40 to +85
8 Ld SOT-23
P8.064
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate
-e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4. For Moisture Sensitivity Level (MSL), please see device information page for ISL267440 or ISL267450A. For more information on MSL please see
techbrief TB363.
5. The part marking is located on the bottom of the part.
3
FN7708.2
June 28, 2012
ISL267440, ISL267450A
Table of Contents
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
ADC Transfer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Reference Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Converter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Acquisition Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Short Cycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power vs Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
11
12
13
13
13
13
14
Serial Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Signal-to-(Noise + Distortion) Ratio (SINAD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Total Harmonic Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peak Harmonic or Spurious Noise (SFDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Intermodulation Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Aperture Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Aperture Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Full Power Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Common-Mode Rejection Ratio (CMRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Integral Nonlinearity (INL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential Nonlinearity (DNL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Zero-Code Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Positive Gain Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Negative Gain Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Track and Hold Acquisition Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply Rejection Ratio (PSRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
15
15
15
15
15
15
15
15
15
15
15
15
16
16
Application Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Grounding and Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
M8.118 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
P8.064 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4
FN7708.2
June 28, 2012
ISL267440, ISL267450A
Absolute Maximum Ratings
Thermal Information
Any Pin to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.0V
Analog Input to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD+0.3V
Digital I/O to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD+0.3V
Digital Input Voltage to GND . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD+0.3V
Maximum Current In to Any Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
ESD Rating
Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . . . 8kV
Machine Model (Tested per JESD22-A115B) . . . . . . . . . . . . . . . . . 400V
Charged Device Model (Tested per JESD22-C101E). . . . . . . . . . . . 1.5kV
Latch Up (Tested per JESD78C; Class 2, Level A) . . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
8 Ld MSOP Package (Notes 6, 7). . . . . . . . .
165
64
8 Ld SOT-23 Package (Notes 6, 7). . . . . . . .
135
99
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
6. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
7. For θJC, the “case temp” location is taken at the package top center.
Electrical Specifications
VDD = +3.0V to +3.6V, fSCLK = 18MHz, fS = 1MSPS, VREF = 2.0V; VDD = +4.75V to +5.25V, fSCLK = 18MHz,
fS = 1MSPS, VREF = 2.5V; VCM = VREF, unless otherwise noted. Typical values are at TA = +25°C. Boldface limits apply over the operating temperature
range, -40°C to +85°C.
ISL267440
SYMBOL
PARAMETER
TEST CONDITIONS
ISL267450A
MIN
(Note 8)
MAX
MIN
(Note 8) (Note 8)
TYP
61.0
61.6
70.0
71.4
dB
60.7
61.5
68.5
70.5
dB
TYP
MAX
(Note 8) UNITS
DYNAMIC PERFORMANCE
SINAD
Signal-to (Noise + Distortion) Ratio fIN = 100kHz
VDD = +4.75V to +5.25V
fIN = 100kHz
VDD = +3.0V to +3.6V
THD
SFDR
Total Harmonic
Distortion
Spurious Free Dynamic Range
IMD
Intermodulation Distortion
tpd
Aperture Delay
Δtpd
Aperture Jitter
β3dB
Full Power Bandwidth
fIN = 100kHz
VDD = +4.75V to +5.25V
-82
-74
-84
-76
dB
fIN = 100kHz
VDD = +3.0V to +3.6V
-80
-72
-84
-74
dB
fIN = 100kHz
VDD = +4.75V to +5.25V
-82
-76
-87
-76
dB
fIN = 100kHz
VDD = +3.0V to +3.6V
-82
-74
-85
-74
dB
2nd and 3rd order, fIN = 90kHz,
110kHz
-92
-95
dB
1
1
ns
@ –3dB
15
15
ps
15
15
MHz
DC ACCURACY
N
Resolution
10
12
Bits
INL
Integral Nonlinearity
-0.5
±0.1
0.5
-1
±0.4
1
LSB
DNL
Differential Nonlinearity
Guaranteed no missed codes to 12bits (ISL267450A) or 10 bits
(ISL267440)
-0.5
±0.1
0.5
-0.95
±0.3
0.95
LSB
Zero-Code Error
Zero Volt Differential Input
-2.5
±0.2
2.5
-6
±0.2
6
LSB
-1
±0.1
1
-2
±0.1
2
LSB
-1
±0.1
1
-2
±0.1
2
LSB
OFFSET
GAIN
Positive Gain Error
± REF input range
Negative Gain Error
ANALOG INPUT (Note 9)
|AIN|
Full-Scale Input Span
2 x VREF
5
VIN+ - VIN–
VIN+ - VIN–
V
FN7708.2
June 28, 2012
ISL267440, ISL267450A
Electrical Specifications
VDD = +3.0V to +3.6V, fSCLK = 18MHz, fS = 1MSPS, VREF = 2.0V; VDD = +4.75V to +5.25V, fSCLK = 18MHz,
fS = 1MSPS, VREF = 2.5V; VCM = VREF, unless otherwise noted. Typical values are at TA = +25°C. Boldface limits apply over the operating temperature
range, -40°C to +85°C. (Continued)
ISL267440
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 8)
TYP
ISL267450A
MAX
MIN
(Note 8) (Note 8)
TYP
MAX
(Note 8) UNITS
Absolute Input Voltage Range
VIN+, VIN– VIN+
VCM = VREF
VCM ±VREF/2
VCM ±VREF/2
VCM ±VREF/2
VIN–
ILEAK
Input DC Leakage Current
CVIN
Input Capacitance
-1
Track/Hold mode
V
VCM±VREF/2
1
-1
V
1
µA
13/5
13/5
pF
VDD = 3V (1% tolerance for specified
performance)
2.0
2.0
V
VDD = 5V (1% tolerance for specified
performance)
2.5
2.5
V
REFERENCE INPUT
VREF
VREF Input Voltage Range
ILEAK
DC Leakage Current
CREF
REF Input Capacitance
-1
Track/Hold mode
1
-1
21/18.5
1
21/18.5
µA
pF
LOGIC INPUTS
VIH
Input High Voltage
VIL
Input Low Voltage
ILEAK
CIN
2.4
2.4
V
0.8
Input Leakage Current
-1
Input Capacitance
1
-1
10
0.8
V
1
µA
10
pF
LOGIC OUTPUTS
VOH
Output High Voltage
ISOURCE = 200µA
VOL
Output Low Voltage
ISINK = 200µA
IOZ
Floating-State Output Current
COUT
VDD - 0.3
VDD - 0.3
V
0.4
-1
Floating-State Output Capacitance
1
-1
10
Output Coding
0.4
V
1
µA
10
pF
Two’s Complement
CONVERSION RATE
tCONV
Conversion Time
888
888
ns
tACQ
Acquisition Time
fSCLK = 18MHz
200
200
ns
fmax
Throughput Rate
1000
1000
kSPS
POWER REQUIREMENTS
VDD
IDD
Positive Supply Voltage Range
2.7
3.6
2.7
3.6
V
4.75
5.25
4.75
5.25
V
1
1
µA
3V
1250
1250
µA
5V
1700
1700
µA
3
3
µW
Positive Supply Input Current
Static
Dynamic
Power Dissipation
VDD = 3V
Static Mode
VDD = 5V
Dynamic
5
5
µW
VDD = 3V, fsmpl = 1MSPS
3.75
3.75
mW
VDD = 5V, fsmpl = 1MSPS
8.50
8.50
mW
NOTES:
8. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
9. The absolute voltage applied to each analog input must be between GND and VDD to guarantee datasheet performance.
6
FN7708.2
June 28, 2012
ISL267440, ISL267450A
Timing Specifications
Limits established by characterization and are not production tested. VDD = 3.0V to 3.6V, fSCLK = 18MHz,
fS = 1MSPS, VREF = 2.0V; VDD = 4.75V to 5.25V, fSCLK = 18MHz, fS = 1MSPS, VREF = 2.5V; VCM = VREF unless otherwise noted. Boldface limits apply over
the operating temperature range, -40°C to +85°C.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 8)
TYP
MAX
(Note 8)
UNITS
18
MHz
fSCLK
Clock Frequency
tSCLK
Clock Period
tACQ
Acquisition Time (Note 10)
tCONV
Conversion Time
tCSW
CS Pulse Width
10
ns
tCSS
CS Falling Edge to SCLK Falling Edge Setup Time
10
ns
tCDV
CS Falling Edge to SDATA Valid
0.01
55
SCLK Falling Edge to SDATA Valid
tSDH
SCLK Falling Edge to SDATA Hold
tSW
SCLK Pulse Width
tQUIET
ns
888
tCLKDV
tDISABLE
ns
ns
20
ns
40
ns
10
SCLK Falling Edge to SDATA Disable Time
(Note 11)
Extrapolated back to true bus relinquish
Quiet Time Before Sample
ns
0.4 x tSCLK
0.6 x tSCLK
ns
10
35
ns
60
ns
NOTE:
10. Read the “Acquisition Time” section on page 13 for a discussion of this parameter.
11. During characterization, tDISABLE is measured from the release point with a 10pF load (see Figure 4) and the equivalent timing using the
AD7440/450A loading (25pF) is calculated.
FIGURE 3. SERIAL INTERFACE TIMING DIAGRAM
VDD
RL
2.85kΩ
OUTPUT
PIN
CL
10pF
FIGURE 4. EQUIVALENT LOAD CIRCUIT
7
FN7708.2
June 28, 2012
ISL267440, ISL267450A
Typical Performance Characteristics
75
0
8192-POINT FFT
fSAMPLE = 1MSPS
fIN = 95.2kHz
SINAD = 72.0dB
THD = -91dB
SFDR = 93dB
5.25V
-20
4.75V
3.6V
2.7V
AMPLITUDE (dBFS)
SINAD (dBc)
70
65
60
-40
-60
-80
-100
-120
55
10
100
INPUT FREQUENCY (kHz)
0
1.0
0.8
-20
0.6
-30
0.4
-40
0.2
DNL (LSB)
0
-50
-60
300
400
500
0.0
-0.2
-70
-0.4
-80
-0.6
-90
-0.8
-1.0
100k
1k
10k
0
1024
2048
3072
4096
CODE
FREQUENCY (Hz)
FIGURE 7. CMRR vs FREQUENCY FOR VDD = 5V
FIGURE 8. TYPICAL DNL FOR THE ISL267450A FOR VDD = 5V
0
1.0
250mVP-P SINE WAVE ON VDD
NO DECOUPLING ON VDD
0.8
-20
0.6
0.4
INL (LSB)
-40
PSRR (dB)
200
FIGURE 6. ISL267450A DYNAMIC PERFORMANCE WITH VDD = 5V
-10
-100
10k
100
FREQUENCY (kHz)
FIGURE 5. ISL267450A SINAD vs ANALOG INPUT FREQUENCY FOR
VARIOUS SUPPLY VOLTAGES
CMRR (dB)
-140
1k
-60
-80
0.2
0.0
-0.2
-0.4
-0.6
-100
-0.8
-120
0
100
200
300
400
500
600
700
800
900
1000
FREQUENCY (kHz)
FIGURE 9. PSRR vs SUPPLY RIPPLE FREQUENCY WITHOUT SUPPLY
DECOUPLING
8
-1.0
0
1024
2048
3072
4096
CODE
FIGURE 10. TYPICAL INL FOR THE ISL267450A FOR VDD = 5V
FN7708.2
June 28, 2012
ISL267440, ISL267450A
Typical Performance Characteristics
(Continued)
3.0
2.5
2.5
2.0
1.5
Pos INL
1.0
1.5
INL (LSB)
DNL (LSB)
2.0
1.0
Pos DNL
0.5
0.5
Neg INL
0.0
-0.5
Neg DNL
0.0
-1.0
-0.5
-1.5
-1.0
-2.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
3.5
0.5
1.0
2.0
5
ZERO CODE ERROR (LSB)
6
DNL (LSB)
1.5
Pos DNL
0.5
Neg DNL
-0.5
4
3
2
3V VDD
1
0
5V VDD
-1
-2
-1.0
0.0
0.5
1.0
1.5
2.0
0.0
2.5
0.5
1.0
1.5
VREF (V)
2.0
2.5
3.0
3.5
VREF (V)
FIGURE 13. CHANGE IN DNL vs VREF FOR THE ISL267450A FOR
VDD = 3V
FIGURE 14. CHANGE IN OFFSET ERROR vs REFERENCE VOLTAGE
FOR VDD = 5V AND 3V FOR THE ISL267450A
5
12.0
4
11.5
3
11.0
2
10.5
Pos INL
ENOB (BITS)
INL (LSB)
2.5
FIGURE 12. CHANGE IN INL vs VREF FOR THE ISL267450A FOR
VDD = 3V
2.5
0.0
2.0
VREF (V)
VREF (V)
FIGURE 11. CHANGE IN DNL vs VREF FOR THE ISL267450A FOR
VDD = 5V
1.0
1.5
1
0
-1
Neg INL
5V VDD
3V VDD
10.0
9.5
9.0
-2
8.5
-3
8.0
-4
7.5
7.0
-5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VREF (V)
FIGURE 15. CHANGE IN INL vs VREF FOR THE ISL267450A FOR
VDD = 5V
9
3.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VREF (V)
FIGURE 16. CHANGE IN ENOB vs REFERENCE VOLTAGE FOR
VDD = 5V AND 3V FOR THE ISL267450A
FN7708.2
June 28, 2012
ISL267440, ISL267450A
Typical Performance Characteristics
(Continued)
70k
0.5
0.4
60k
65,516
CODES
0.3
0.2
DNL (LSB)
HITS
50k
40k
30k
0.1
0
-0.1
-0.2
20k
-0.3
10k
10
CODES
0
2044
2045
2046
-0.4
10
CODES
2047
2048
-0.5
2049
0
2050
256
FIGURE 17. HISTOGRAM OF 10,000 CONVERSIONS OF A DC INPUT
FOR THE ISL267450A WITH VDD = 5V
768
1024
FIGURE 18. TYPICAL DNL FOR THE ISL267440 FOR VDD = 5V
0.5
0
8192-POINT FFT
fSAMPLE = 1MSPS
fIN = 95.2kHz
SINAD = 61.6dB
THD = -75dB
SFDR = 81dB
-20
-40
0.4
0.3
0.2
INL (LSB)
AMPLITUDE (dBFS)
512
CODE
CODE
-60
-80
0.1
0
-0.1
-0.2
-100
-0.3
-120
-0.4
-140
-0.5
0
100
200
300
400
500
FREQUENCY (kHz)
FIGURE 19. ISL267440 DYNAMIC PERFORMANCE WITH VDD = 5V
10
0
256
512
768
1024
CODE
FIGURE 20. TYPICAL INL FOR THE ISL267440 FOR VDD = 5V
FN7708.2
June 28, 2012
ISL267440, ISL267450A
Functional Description
DAC
CONV
VIN+
VIN–
ACQ
CS
ACQ
ACQ
CONV
CONV
SAR
LOGIC
CS
011...111
1LSB = 2•VREF/4096
011...110
ADC CODE
The ISL267440, ISL267450A are based on a successive
approximation register (SAR) architecture utilizing capacitive
charge redistribution digital to analog converters (DACs).
Figure 21 shows a simplified representation of the converter.
During the acquisition phase (ACQ) the differential input is stored
on the sampling capacitors (CS). The comparator is in a balanced
state since the switch across its inputs is closed. The signal is
fully acquired after tACQ has elapsed, and the switches then
transition to the conversion phase (CONV) so the stored voltage
may be converted to digital format. The comparator will become
unbalanced when the differential switch opens and the input
switches transition (assuming that the stored voltage is not
exactly at mid-scale). The comparator output reflects whether the
stored voltage is above or below mid-scale, which sets the value
of the MSB. The SAR logic then forces the capacitive DACs to
adjust up or down by one quarter of full-scale by switching in
binarily weighted capacitors. Again, the comparator output
reflects whether the stored voltage is above or below the new
value, setting the value of the next lowest bit. This process
repeats until all 12 bits have been resolved.
000...001
000...000
111...111
100...010
100...001
100...000
–VREF
+ ½LSB
0V
+VREF +VREF
– 1½LSB – 1LSB
ANALOG INPUT
VIN+ – (VIN–)
FIGURE 22. IDEAL TRANSFER CHARACTERISTICS
Analog Input
The ISL267440, ISL267450A feature a fully differential input
with a nominal full-scale range equal to twice the applied VREF
voltage. Each input swings VREF VP-P, 180° out of phase from
one another for a total differential input of 2*VREF (refer to
Figure 23). Differential signaling offers several benefits over a
single-ended input, such as:
• Doubling of the full-scale input range (and therefore the
dynamic range)
• Improved even order harmonic distortion
• Better noise immunity due to common mode rejection
DAC
VREF
FIGURE 21. SAR ADC ARCHITECTURAL BLOCK DIAGRAM
An external clock must be applied to the SCLOCK pin to generate
a conversion result. The allowable frequency range for SCLOCK is
10kHz to 18MHz (556SPS to 1MSPS). Serial output data is
transmitted on the falling edge of SCLOCK. The receiving device
(FPGA, DSP or Microcontroller) may latch the data on the rising
edge of SCLOCK to maximize set-up and hold times.
A stable, low-noise reference voltage must be applied to the
VREF pin to set the full-scale input range and common-mode
voltage. See “Voltage Reference Input” on page 12 for more
details.
VREF P-P
VIN+
ISL267440,
ISL267450A
VCM
VREF P-P
VIN–
FIGURE 23. DIFFERENTIAL INPUT SIGNALING
Figure 24 shows the relationship between the reference voltage
and the full-scale input range for two different values of VREF.
ADC Transfer Function
The output coding for the ISL267440, ISL267450A is twos
complement. The first code transition occurs at successive LSB
values (i.e., 1 LSB, 2 LSB, and so on). The LSB size of the
ISL267450A is 2*VREF/4096, while the LSB size of the
ISL267440 is 2*VREF/1024. The ideal transfer characteristic of
the ISL267440, ISL267450A is shown in Figure 22.
11
FN7708.2
June 28, 2012
ISL267440, ISL267450A
VCM
V
2.5
5.0
4.0
2.5
VIN–
VIN+
2.0VP-P
3.0
2.0V
2.0
VCM
1.5
2.0
1.0V
1.0
1.0
t
0.5
VREF = 2V
VREF
V
0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
FIGURE 26. RELATIONSHIP BETWEEN VREF AND VCM FOR VDD = 3V
5.0
VIN–
4.0
Voltage Reference Input
VIN+
2.5VP-P
An external low-noise reference voltage must be applied to the
VREF pin to set the full-scale input range of the converter. The
reference input accepts voltages ranging from 0.1V to 2.2V for 3V
operation and 0.1V to 3.5V for 5V operation. The device is
specified with a reference voltage of 2.5V for 5V operation and
2.0V for 3V operation.
VCM
3.0
2.0
1.0
t
VREF = 2.5V
FIGURE 24. RELATIONSHIP BETWEEN VREF AND FULL-SCALE RANGE
Note that there is a trade-off between VREF and the allowable
common mode input voltage (VCM). The full-scale input range is
proportional to VREF; therefore the VCM range must be limited
for larger values of VREF in order to keep the absolute maximum
and minimum voltages on the VIN+ and VIN– pins within
specification. Figures 25 and 26 illustrate this relationship for 5V
and 3V operation, respectively. The dashed lines show the
theoretical VCM range based solely on keeping the VIN+ and VIN–
pins within the supply rails. Additional restrictions are imposed
due to the required headroom of the input circuitry, resulting in
practical limits shown by the shaded area.
Figures 27 and 28 illustrate possible voltage reference options
for the ISL267440/ISL26750A. Figure 27 uses the precision
ISL21090 voltage reference which exhibits exceptionally low drift
and low noise. The ISL21090 must use a power supply greater
than 4.7V. The VREF input pin of the ISL267XX devices uses very
low current, so the decoupling capacitor can be small (0.1µF).
Figure 28 illustrates the ISL21010 voltage reference being used
with these ADCs. The ISL21010 series voltage references have
higher noise and drift than the ISL26090 devices, but they
consume very low operating current and are excellent for
battery-powered applications.
VCM
5.0
4.0
4.25V
3.25V
3.0
2.0
1.75V
1.0
VREF
0.5
1.0
1.5
2.0
2.5
3.0
3.5
FIGURE 25. RELATIONSHIP BETWEEN VREF AND VCM FOR VDD = 5V
12
FN7708.2
June 28, 2012
ISL267440, ISL267450A
5V
+
BULK
0.1µF
0.1µF
1 DNC
DNC
8
2 VIN
DNC
7
3 COMP
VOUT
6
4 GND
TRIM
5
ISL267440 VDD
ISL267450A
VREF
2.5V
0.1µF
ISL21090
FIGURE 27. PRECISION VOLTAGE REFERENCE FOR +5V SUPPLY
+2.7V TO +3.6V
OR +5V
+
BULK
VIN
1
VOUT
2
GND
3
0.1µF
0.1µF
ISL267440 VDD
ISL267450A
VREF
1.25, 2.048 OR 2.5V
0.1µF
ISL21010
FIGURE 28. VOLTAGE REFERENCE FOR +2.7V TO +3.6V, OR FOR +5V SUPPLY
Converter Operation
Power-On Reset
The ISL267440 and ISL267450A are designed to minimize
power consumption by only powering up the SAR comparator
during conversion time. When the converter is in track mode (its
sample capacitors are tracking the input signal) the SAR
comparator is powered down. The state of the converter is
dictated by the logic state of CS. When CS is high, the SAR
comparator is powered down while the sampling capacitor array
is tracking the input. When CS transitions low, the capacitor array
immediately captures the analog signal that is being tracked.
After CS is taken low, the SCLK pin is toggled 16 times. For the
first 3 clocks, the comparator is powered up and auto-zeroed,
then the SAR decision process is begun. This process uses 12
SCLK cycles for the 12-bit ISL267450A. Each SAR decision is
presented to the SDATA output on the next clock cycle after the
SAR decision is performed. The SAR process (12 bits) is
completed on SCLK cycle 15. At this point in time, the SAR
comparator is powered down and the capacitor array is placed
back into Track mode. The last SAR comparator decision is
output from SDATA on the 16th SCLK cycle. When the last data
bit is output from SDATA, the output switches to a logic 0 until CS
is taken high, at which time, the SDATA output enters a High-Z
state.
When power is first applied, the ISL267440/ISL267450A
performs a power-on reset that requires approximately 2.5ms to
execute. After this is complete, a single dummy conversion must
be executed (by taking CS low) in order to initialize the switched
capacitor track and hold. The dummy conversion cycle will take
1µs with an 18MHz SCLK. Once the dummy cycle is complete,
the ADC mode will be determined by the state of CS. Regular
conversions can be started immediately after this dummy cycle
is completed and time has been allowed for proper acquisition.
Figures 29 and 30 on page 14 illustrate the system timing for the
12, and 10-bit converters respectively.
13
Acquisition Time
To achieve the maximum sample rate (1MSps) in the
ISL267450A device, the maximum acquisition time is 200ns. For
slower conversion rates, or for conversions performed using a
slower SCLK value than 18MHz, the minimum acquisition time is
200ns. This same minimum applies to the ISL267440. This
minimum acquisition time also applies to all the devices if short
cycling is utilized.
Short Cycling
In cases where a lower resolution conversion is acceptable, CS
can be pulled high before all SCLK falling edges have elapsed.
This is referred to as short cycling, and it can be used to further
optimize power dissipation. In this mode, a lower resolution
result will be output, but the ADC will enter static mode sooner
and exhibit a lower average power consumption than if the
complete conversion cycle were carried out. The minimum
acquisition time (tACQ) requirement of 200ns must be met for
the next conversion to be valid.
FN7708.2
June 28, 2012
ISL267440, ISL267450A
FIGURE 29. ISL267450A SYSTEM TIMING
FIGURE 30. ISL267440 SYSTEM TIMING
Power vs Throughput Rate
Serial Digital Interface
The ISL267440 and ISL267450A provide reduced power
consumption at lower conversion rates by automatically
switching into a low-power mode after completing a conversion.
The average power consumption of the ADC decreases at lower
throughput rates. Figure 31 shows the typical power
consumption over a wide range of throughput rates.
Conversion data is accessed with an SPI-compatible serial
interface. The interface consists of the serial clock (SCLK), serial
data output (SDATA), and chip select (CS).
100
POWER (mW)
10
VDD = 5V
The serial interface is designed around using 16 SCLK cycles to
perform an autozero on the SAR comparator and additional SCLK
cycles for SAR comparator decisions (12 SLCKs in the 12-bit
device, 10 SCLKs in the 10-bit device, and 8 SCLKs in the 8-bit
device). If short cycling is not used, all converter throughput
cycles take 16 SCLKs. The SDATA output goes low after the last
conversion decision has been presented to the SDATA output, as
shown in Figures 29 and 30.
1
VDD = 3V
0.1
0.01
0
50
100
150
200
250
300
350
THROUGHPUT (Ksps)
FIGURE 31. POWER CONSUMPTION vs THROUGHPUT RATE
14
FN7708.2
June 28, 2012
ISL267440, ISL267450A
Data Format
Output data is encoded in two’s complement format as shown in
Table 1. The voltage levels in the table are idealized and don’t
account for any gain/offset errors or noise.
TABLE 1. TWO’S COMPLEMENT DATA FORMATTING
INPUT
VOLTAGE
DIGITAL OUTPUT
–Full Scale
–VREF
1000 0000 0000
–Full Scale + 1LSB
–VREF+ 1LSB
1000 0000 0001
Midscale
0
0000 0000 0000
+Full Scale – 1LSB
+VREF– 1LSB
0111 1111 1110
+Full Scale
+VREF
0111 1111 1111
second order terms include (fa + fb) and (fa – fb), while the third
order terms include (2fa + fb), (2fa – fb), (fa + 2fb), and (fa –2fb).
The ISL267440, ISL267450A is tested using the CCIF standard,
where two input frequencies near the top end of the input
bandwidth are used. In this case, the second order terms are
usually distanced in frequency from the original sine waves,
while the third order terms are usually at a frequency close to the
input frequencies. As a result, the second and third order terms
are specified separately. The calculation of the intermodulation
distortion is as per the THD specification, where it is the ratio of
the rms sum of the individual distortion products to the rms
amplitude of the sum of the fundamentals expressed in dBs.
Aperture Delay
This is the amount of time from the leading edge of the sampling
clock until the ADC actually takes the sample.
Terminology
Signal-to-(Noise + Distortion) Ratio (SINAD)
This is the measured ratio of signal-to-(noise + distortion) at the
output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals up
to half the sampling frequency (fs/2), excluding DC. The ratio
is dependent on the number of quantization levels in the
digitization process; the more levels, the smaller the quantization
noise. The theoretical signal-to-(noise + distortion) ratio for an
ideal N-bit converter with a sine wave input is given by:
Signal-to-(Noise + Distortion) = ( 6.02 N + 1.76 )dB
(EQ. 1)
Thus, for a 12-bit converter this is 74dB, and for a 10-bit this is 62dB.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the ISL267440, ISL267450A,
it is defined as:
V 22 + V 32 + V 42 + V 52 + V 62
THD ( dB ) = 20 log ----------------------------------------------------------------------V 12
(EQ. 2)
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5, and V6 are the rms amplitudes of the second to the
sixth harmonics.
Peak Harmonic or Spurious Noise (SFDR)
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding DC) to the rms value of
the fundamental (also referred to as Spurious Free Dynamic
Range (SFDR)). Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, it will be
a noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m and n = 0, 1, 2 or 3. Intermodulation distortion terms are those
for which neither m nor n are equal to zero. For example, the
15
Aperture Jitter
This is the sample-to-sample variation in the effective point in
time at which the actual sample is taken.
Full Power Bandwidth
The full power bandwidth of an ADC is that input frequency at
which the amplitude of the reconstructed fundamental is
reduced by 3dB for a full-scale input.
Common-Mode Rejection Ratio (CMRR)
The common-mode rejection ratio is defined as the ratio of the
power in the ADC output at full-scale frequency, f, to the power of
a 250mVP-P sine wave applied to the common-mode voltage of
VIN+ and VIN– of frequency fs:
CMRR ( dB ) = 10 log ( Pfl ⁄ Pfs )
(EQ. 3)
Pf is the power at the frequency f in the ADC output; Pfs is the
power at frequency fs in the ADC output.
Integral Nonlinearity (INL)
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function.
Differential Nonlinearity (DNL)
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Zero-Code Error
This is the deviation of the midscale code transition (111...111 to
000...000) from the ideal VIN+ – VIN– (i.e., 0 LSB).
Positive Gain Error
This is the deviation of the last code transition (011...110 to
011...111) from the ideal VIN+ – VIN– (i.e., +REF – 1 LSB), after
the zero code error has been adjusted out.
Negative Gain Error
This is the deviation of the first code transition (100...000 to
100...001) from the ideal VIN+ – VIN– (i.e., – REF + 1 LSB), after
the zero code error has been adjusted out.
FN7708.2
June 28, 2012
ISL267440, ISL267450A
Track and Hold Acquisition Time
The track and hold acquisition time is the minimum time
required for the track and hold amplifier to remain in track mode
for its output to reach and settle to within 0.5 LSB of the applied
input signal.
Power Supply Rejection Ratio (PSRR)
The power supply rejection ratio is defined as the ratio of the
power in the ADC output at full-scale frequency, f, to ADC VDD
supply of frequency fS. The frequency of this input varies from
1kHz to 1MHz.
PSRR ( dB ) = 10 log ( Pf ⁄ Pfs )
(EQ. 4)
Pf is the power at frequency f in the ADC output; Pfs is the power
at frequency fs in the ADC output.
Application Hints
Grounding and Layout
The printed circuit board that houses the ISL267440,
ISL267450A should be designed so that the analog and digital
sections are separated and confined to certain areas of the
board. This facilitates the use of ground planes that can be easily
separated. A minimum etch technique is generally best for
ground planes since it gives the best shielding. Digital and analog
ground planes should be joined in only one place, and the
connection should be a star ground point established as close to
the GND pin on the ISL267440, ISL267450A as possible. Avoid
running digital lines under the device, as this will couple noise
onto the die. The analog ground plane should be allowed to run
under the ISL267440, ISL267450A to avoid noise coupling.
The power supply lines to the device should use as large a trace
as possible to provide low impedance paths and reduce the
effects of glitches on the power supply line.
Fast switching signals, such as clocks, should be shielded with
digital ground to avoid radiating noise to other sections of the
board, and clock signals should never run near the analog inputs.
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
reduces the effects of feedthrough through the board. A
microstrip technique is by far the best but is not always possible
with a double-sided board.
In this technique, the component side of the board is dedicated
to ground planes, while signals are placed on the solder side.
Good decoupling is also important. All analog supplies should be
decoupled with μF tantalum capacitors in parallel with 0.1μF
capacitors to GND. To achieve the best from these decoupling
components, they must be placed as close as possible to the
device.
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
June 15, 2012
FN7708.2
Page 2- Typical Connection Diagram: Added value to cap 0.1µF and removed ‘+’ from the 0.1 capacitor.
Page 3, Ordering Information Table: “Removed coming soon on all the SOT23’s.”
Page11- Figure22, Ideal Transfer Characteristics: replaced the diagram for clarity.
CHANGE
March 22, 2012
FN7708.1
Page 12 - Updated Voltage Reference Input section
Page 13 - Removed Applications Information section
Pages 13, 14 - Replaced/updated the following sections: Power-Down/Standby Modes, Dynamic Mode, Static
Mode, Short Cycling, Power-on Reset, Power vs Throughput Rate, and Serial Digital Interface with:
Converter Operation, Power-On Reset, Acquisition Time, Short Cycling, Power vs Throughput Rate, and Serial
Digital Interface setions.
Page 18 - Added package outline drawing P8.064
December 5, 2011
FN7708.0
Initial release.
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on
intersil.com: ISL267440, ISL267450A
To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff
FITs are available from our website at: http://rel.intersil.com/reports/search.php
16
FN7708.2
June 28, 2012
ISL267440, ISL267450A
Package Outline Drawings
M8.118
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 7/11
5
3.0±0.05
A
DETAIL "X"
D
8
1.10 MAX
SIDE VIEW 2
0.09 - 0.20
4.9±0.15
3.0±0.05
5
0.95 REF
PIN# 1 ID
1
2
B
0.65 BSC
GAUGE
PLANE
TOP VIEW
0.55 ± 0.15
0.25
3°±3°
0.85±010
H
DETAIL "X"
C
SEATING PLANE
0.25 - 0.36
0.08 M C A-B D
0.10 ± 0.05
0.10 C
SIDE VIEW 1
(5.80)
NOTES:
(4.40)
(3.00)
1. Dimensions are in millimeters.
(0.65)
(0.40)
(1.40)
TYPICAL RECOMMENDED LAND PATTERN
17
2. Dimensioning and tolerancing conform to JEDEC MO-187-AA
and AMSEY14.5m-1994.
3. Plastic or metal protrusions of 0.15mm max per side are not
included.
4. Plastic interlead protrusions of 0.15mm max per side are not
included.
5. Dimensions are measured at Datum Plane "H".
6. Dimensions in ( ) are for reference only.
FN7708.2
June 28, 2012
ISL267440, ISL267450A
Small Outline Transistor Plastic Packages (SOT23-8)
0.20 (0.008)
CL
6
7
VIEW C
INCHES
5
CL
CL
E
1
2
8 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
e
b
8
P8.064
M C
3
E1
MIN
MAX
MIN
MAX
NOTES
A
0.036
0.057
0.90
1.45
-
A1
0.000
0.0059
0.00
0.15
-
A2
0.036
0.051
0.90
1.30
-
b
0.009
0.015
0.22
0.38
-
b1
0.009
0.013
0.22
0.33
c
0.003
0.009
0.08
0.22
6
4
e1
C
D
CL
A
MILLIMETERS
SYMBOL
A2
A1
SEATING
PLANE
-C-
0.10 (0.004)
c1
0.003
0.008
0.08
0.20
6
D
0.111
0.118
2.80
3.00
3
E
0.103
0.118
2.60
3.00
-
E1
0.060
0.067
1.50
1.70
3
e
0.0256 Ref
0.65 Ref
-
e1
0.0768 Ref
1.95 Ref
-
L
C
0.014
0.022
0.35
0.55
L1
0.024 Ref.
0.60 Ref.
L2
0.010 Ref.
0.25 Ref.
N
8
8
5
WITH
b
R
0.004
-
0.10
PLATING
b1
R1
0.004
0.010
0.10
0.25
α
0o
8o
0o
8o
c
c1
4
-
Rev. 2 9/03
NOTES:
BASE METAL
1. Dimensioning and tolerance per ASME Y14.5M-1994.
2. Package conforms to EIAJ SC-74 and JEDEC MO178BA.
4X θ1
3. Dimensions D and E1 are exclusive of mold flash, protrusions, or gate
burrs.
R1
4. Footlength L measured at reference to gauge plane.
5. “N” is the number of terminal positions.
R
GAUGE PLANE
SEATING
PLANE
L
C
L1
α
6. These Dimensions apply to the flat section of the lead between 0.08mm
and 0.15mm from the lead tip.
7. Controlling dimension: MILLIMETER. Converted inch dimensions
are for reference only
L2
4X θ1
VIEW C
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
18
FN7708.2
June 28, 2012
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