DATASHEET

12-Bit, 555kSPS SAR ADC
ISL267452
Features
The ISL267452 is a 12-bit, 555kSPS sampling SAR-type ADC
featuring excellent linearity over supply and temperature
variations, and is drop-in compatible with the AD7452. The
robust, fully-differential input offers high impedance to minimize
errors due to leakage currents, and the specified measurement
accuracy is maintained with input signals up to the supply rails.
• Drop-in Compatible with AD7452
The reference accepts inputs from 0.1V to 2.2V for 3V operation
and 0.1V to 3.5V for 5V operation, which provides design
flexibility in a wide variety of applications. The ISL267452 also
features up to 8kV Human Body Model ESD survivability.
• 3V or 5V Operation
The serial digital interface is SPI compatible and is easily
interfaced to all popular FPGAs and microcontrollers. Power
dissipation is 7mW at a sampling rate of 555kSPS, and just 5µW
between conversions utilizing Auto Power-Down mode (with a 5V
supply), making the ISL267452 an excellent solution for remote
industrial sensors and battery-powered instruments.
The ISL267452 is available in an 8 LD SOT-23 package, and is
specified for operation over the Industrial temperature range
(-40°C to +85°C).
• Differential Input (Span = 2VREF)
• Simple SPI-compatible Serial Digital Interface
• Guaranteed No Missing Codes
• 555kHz Sampling Rate
• Low Operating Current
- 1.25mA at 555kSPS with 3V Supplies
- 1.70mA at 555kSPS with 5V Supplies
• Power-down Current between Conversions: 1µA
• Excellent Differential Non-Linearity
• Low THD: -83dB (typ)
• Pb-Free (RoHS Compliant)
• Available in SOT-23 Package
Applications
• Remote Data Acquisition
• Battery Operated Systems
• Industrial Process Control
• Energy Measurement
• Data Acquisition Systems
• Pressure Sensors
• Flow Controllers
1.0
0.8
0.6
VDD
VIN+
SAR
LOGIC
VIN–
SERIAL
INTERFACE
SCLK
SDATA
CS
DNL (LSB)
0.4
DAC
VREF
0.2
0.0
-0.2
-0.4
VREF
DAC
-0.6
-0.8
GND
-1.0
0
1024
2048
3072
4096
CODE
FIGURE 1. BLOCK DIAGRAM
July 26, 2012
FN8255.0
1
FIGURE 2. DIFFERENTIAL LINEARITY ERROR vs CODE
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL267452
Typical Connection Diagram
VREF
0.1µF
+3V/5V
0.1µF + 10µF SUPPLY
VREF
VREFP-P
VIN+
VREFP-P
VIN–
VDD
SCLK
SDATA
GND
µP/µC
CS
SERIAL
INTERFACE
Pin Configuration
ISL267452
(8 LD SOT-23)
TOP VIEW
VREF 1
8 VDD
VIN+ 2
7 SCLK
VIN– 3
6 SDATA
GND 4
5 CS
Pin Descriptions
ISL267452
PIN NAME
PIN NUMBER
DESCRIPTION
VDD
8
Supply voltage, +2.7V to 5.25V.
SCLK
7
Serial clock input. Controls digital I/O timing and clocks the conversion.
SDATA
6
Digital conversion output.
CS
5
Chip select input. Controls the start of a conversion.
GND
4
Ground
VIN–
3
Negative analog input.
VIN+
2
Positive analog input.
VREF
1
Reference voltage.
2
FN8255.0
July 26, 2012
ISL267452
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PACKAGE
Tape & Reel
(Pb-free)
PKG.
DWG. #
PART
MARKING
VDD RANGE
(V)
TEMP RANGE
(°C)
ISL267452IHZ-T
7452 (Note 4)
2.7 to 5.25
-40 to +85
8 Ld SOT-23
P8.064
ISL267452IHZ-T7A
7452 (Note 4)
2.7 to 5.25
-40 to +85
8 Ld SOT-23
P8.064
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate
-e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL267452. For more information on MSL please see techbrief TB363.
4. The part marking is located on the bottom of the part.
3
FN8255.0
July 26, 2012
ISL267452
Table of Contents
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
ADC Transfer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Voltage Reference Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Converter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Acquisition Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Short Cycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Application Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Grounding and Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Signal-to-(Noise + Distortion) Ratio (SINAD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Total Harmonic Distortion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peak Harmonic or Spurious Noise (SFDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Intermodulation Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Aperture Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Aperture Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Full Power Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Common-Mode Rejection Ratio (CMRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Integral Nonlinearity (INL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential Nonlinearity (DNL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Zero-Code Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Positive Gain Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Negative Gain Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Track and Hold Acquisition Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply Rejection Ratio (PSRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
P8.064 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4
FN8255.0
July 26, 2012
ISL267452
Absolute Maximum Ratings
Thermal Information
Any Pin to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.0V
Analog Input to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to VDD+0.3V
Digital I/O to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to VDD+0.3V
Digital Input Voltage to GND . . . . . . . . . . . . . . . . . . . . . . .-0.3V to VDD+0.3V
Maximum Current In to Any Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
ESD Rating
Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . . . 8kV
Machine Model (Tested per JESD22-A115B) . . . . . . . . . . . . . . . . . 400V
Charged Device Model (Tested per JESD22-C101E). . . . . . . . . . . . 1.5kV
Latch Up (Tested per JESD78C; Class 2, Level A) . . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
8 Ld SOT-23 Package (Notes 5, 6). . . . . . . .
135
99
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
5. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
6. For θJC, the “case temp” location is taken at the package top center.
Electrical Specifications VDD = +3.0V to +3.6V, fSCLK = 10MHz, fS = 555kSPS, VREF = 2.0V; VDD = +4.75V to +5.25V, fSCLK = 10MHz,
fS = 555kSPS, VREF = 2.5V; VCM = VREF, unless otherwise noted. Typical values are at TA = +25°C. Boldface limits apply over the operating temperature
range, -40°C to +85°C.
ISL267452
SYMBOL
MIN
(Note 7)
TYP
fIN = 100kHz
VDD = +4.75V to +5.25V
70.0
71.4
dB
fIN = 100kHz
VDD = +3.0V to +3.6V
68.5
70.5
dB
PARAMETER
TEST CONDITIONS
MAX
(Note 7)
UNITS
DYNAMIC PERFORMANCE
SINAD
THD
SFDR
Signal-to (Noise + Distortion) Ratio
Total Harmonic
Distortion
Spurious Free Dynamic Range
IMD
Intermodulation Distortion
fIN = 100kHz
VDD = +4.75V to +5.25V
-84
-76
dB
fIN = 100kHz
VDD = +3.0V to +3.6V
-84
-74
dB
fIN = 100kHz
VDD = +4.75V to +5.25V
-87
-76
dB
fIN = 100kHz
VDD = +3.0V to +3.6V
-85
-74
dB
2nd and 3rd order, fIN = 90kHz, 110kHz
-95
dB
tpd
Aperture Delay
1
ns
Δtpd
Aperture Jitter
15
ps
β3dB
Full Power Bandwidth
15
MHz
@ –3dB
DC ACCURACY
Resolution
12
INL
N
Integral Nonlinearity
-1
±0.4
1
LSB
DNL
Differential Nonlinearity
Guaranteed no missed codes to 12 bits
-0.95
±0.3
0.95
LSB
Zero-Code Error
Zero Volt Differential Input
-6
±0.2
6
LSB
-2
±0.1
2
LSB
-2
±0.1
2
LSB
OFFSET
GAIN
Positive Gain Error
± VREF input range
Negative Gain Error
Bits
ANALOG INPUT (Note 8)
|AIN|
Full-Scale Input Span
2 x VREF
VIN+ - VIN–
V
VCM ±VREF/2
V
VCM±VREF/2
V
Absolute Input Voltage Range
VIN+, VIN–
VIN+
VCM = VREF
VIN–
5
FN8255.0
July 26, 2012
ISL267452
Electrical Specifications VDD = +3.0V to +3.6V, fSCLK = 10MHz, fS = 555kSPS, VREF = 2.0V; VDD = +4.75V to +5.25V, fSCLK = 10MHz,
fS = 555kSPS, VREF = 2.5V; VCM = VREF, unless otherwise noted. Typical values are at TA = +25°C. Boldface limits apply over the operating temperature
range, -40°C to +85°C. (Continued)
ISL267452
SYMBOL
PARAMETER
ILEAK
Input DC Leakage Current
CVIN
Input Capacitance
TEST CONDITIONS
MIN
(Note 7)
TYP
-1
Track/Hold mode
MAX
(Note 7)
UNITS
1
µA
13/5
pF
VDD = 3V (1% tolerance for specified
performance)
2.0
V
VDD = 5V (1% tolerance for specified
performance)
2.5
V
REFERENCE INPUT
VREF
VREF Input Voltage Range
ILEAK
DC Leakage Current
CVREF
VREF Input Capacitance
-1
Track/Hold mode
μA
1
21/18.5
pF
LOGIC INPUTS
VIH
Input High Voltage
VIL
Input Low Voltage
ILEAK
CIN
2.4
Input Leakage Current
V
-1
Input Capacitance
0.8
V
1
µA
10
pF
LOGIC OUTPUTS
VOH
Output High Voltage
ISOURCE = 200µA
VOL
Output Low Voltage
ISINK = 200µA
IOZ
Floating-State Output Current
COUT
VDD - 0.3
V
-1
Floating-State Output Capacitance
0.4
V
1
µA
10
Output Coding
pF
Two’s Complement
CONVERSION RATE
tCONV
Conversion Time
fSCLK = 10MHz
1.6
µs
tACQ
Acquisition Time
200
ns
fmax
Throughput Rate
555
kSPS
2.7
3.6
V
4.75
5.25
V
POWER REQUIREMENTS
VDD
Positive Supply Voltage Range
IDD
Positive Supply Input Current
Static
Dynamic
1
µA
3V
1250
µA
5V
1700
µA
VDD = 3V
3
µW
VDD = 5V
5
µW
VDD = 3V, fsmpl = 555kSPS
3.75
mW
VDD = 5V, fsmpl = 555kSPS
8.5
mW
Power Dissipation
Static Mode
Dynamic
NOTES:
7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
8. The absolute voltage applied to each analog input must be between GND and VDD to guarantee datasheet performance.
6
FN8255.0
July 26, 2012
ISL267452
Timing Specifications
Limits established by characterization and are not production tested. VDD = 3.0V to 3.6V, fSCLK = 10MHz,
fS = 555kSPS, VREF = 2.0V; VDD = 4.75V to 5.25V, fSCLK = 10MHz, fS = 555kSPS, VREF = 2.5V; VCM = VREF unless otherwise noted. Boldface limits apply
over the operating temperature range, -40°C to +85°C.
SYMBOL
PARAMETER
MIN
(Note 7)
TEST CONDITIONS
TYP
MAX
(Note 7)
UNITS
10
MHz
fSCLK
Clock Frequency
0.01
tSCLK
Clock Period
100
tACQ
Acquisition Time
200
ns
tCONV
Conversion Time
1.6
µs
tCSW
CS Pulse Width
10
ns
tCSS
CS Falling Edge to SCLK Falling Edge Setup Time
10
ns
tCDV
CS Falling Edge to SDATA Valid
20
tCLKDV
SCLK Falling Edge to SDATA Valid
tSDH
SCLK Falling Edge to SDATA Hold
tSW
SCLK Pulse Width
tDISABLE
tQUIET
ns
40
SCLK Falling Edge to SDATA Disable Time
(Note 9)
ns
ns
10
ns
0.4 x tSCLK
ns
Extrapolated back to true bus relinquish
10
Quiet Time Before Sample
35
60
ns
ns
NOTE:
9. During characterization, tDISABLE is measured from the release point with a 10pF load (see Figure 4) and the equivalent timing using the AD7452
loading (25pF) is calculated.
tCSW
CS
tCONV
tCSS
SCLK
1
2
3
13
5
4
tCLKDV
tCDV
14
16
15
tSW
tACQ
tQUIET
SDATA
0
0
0
0
MSB
D2
D1
D0
HI-Z
FIGURE 3. SERIAL INTERFACE TIMING DIAGRAM
VDD
RL
2.85kΩ
OUTPUT
PIN
CL
10pF
FIGURE 4. EQUIVALENT LOAD CIRCUIT
7
FN8255.0
July 26, 2012
ISL267452
Typical Performance Characteristics
75
0
5.25V
8192 POINT FFT
fSAMPLE = 555kSPS
fIN = 92.5kHz
SINAD = 70.9dB
THD = 82.9dB
SFDR = 86.6dB
-20
3.6V
SINAD (dBc)
2.7V
-40
4.75V
AMPLITUDE (dBFS)
70
65
60
-60
-80
-100
-120
-140
55
10
100
INPUT FREQUENCY (kHz)
-160
1k
50
100
150
200
250 277.5
FREQUENCY (kHz)
FIGURE 5. ISL267452 SINAD vs ANALOG INPUT FREQUENCY FOR
VARIOUS SUPPLY VOLTAGES
FIGURE 6. ISL267452 DYNAMIC PERFORMANCE WITH VDD = 3V
0
0
8192 POINT FFT
fSAMPLE = 555kSPS
fIN = 92.5kHz
SINAD = 71.7dB
THD = 85dB
SFDR = 86.2dB
-20
-40
AMPLITUDE (dBFS)
0
-20
-30
CMRR (dB)
-60
-10
-80
-100
-40
-50
-60
-70
-120
-80
-140
-160
-90
0
50
100
150
200
-100
10k
250 277.5
100k
1k
FREQUENCY (Hz)
FREQUENCY (kHz)
FIGURE 7. ISL267452 DYNAMIC PERFORMANCE WITH VDD = 5V
FIGURE 8. CMRR vs FREQUENCY FOR VDD = 5V
1.0
0
250mVP-P SINE WAVE ON VDD
NO DECOUPLING ON VDD
0.8
-20
0.6
0.4
-40
0.2
PSRR (dB)
DNL (LSB)
10k
0.0
-0.2
-60
-80
-0.4
-0.6
-100
-0.8
-1.0
0
1024
2048
3072
4096
CODE
FIGURE 9. TYPICAL DNL FOR THE ISL267452 FOR VDD = 5V
8
-120
0
100
200
300
400
500
600
700
800
900
1000
FREQUENCY (kHz)
FIGURE 10. PSRR vs SUPPLY RIPPLE FREQUENCY WITHOUT SUPPLY
DECOUPLING
FN8255.0
July 26, 2012
ISL267452
Typical Performance Characteristics
(Continued)
3.0
1.0
0.8
2.5
0.6
2.0
0.2
DNL (LSB)
INL (LSB)
0.4
0.0
-0.2
1.5
1.0
Pos DNL
0.5
-0.4
Neg DNL
0.0
-0.6
-0.5
-0.8
-1.0
-1.0
0
1024
2048
3072
0.0
4096
0.5
1.0
CODE
1.5
2.0
2.5
3.0
3.5
VREF (V)
FIGURE 11. TYPICAL INL FOR THE ISL267452 FOR VDD = 5V
FIGURE 12. CHANGE IN DNL vs VREF FOR THE ISL267452 FOR
VDD = 5V
2.5
2.5
2.0
2.0
1.5
DNL (LSB)
INL (LSB)
1.5
POS INL
1.0
0.5
NEG INL
0.0
1.0
POS DNL
0.5
-0.5
NEG DNL
0.0
-1.0
-0.5
-1.5
-1.0
-2.0
0.0
0.5
1.0
1.5
2.0
2.5
0.0
0.5
1.0
VREF (V)
FIGURE 13. CHANGE IN INL vs VREF FOR THE ISL267452 FOR
VDD = 3V
2.0
2.5
FIGURE 14. CHANGE IN DNL vs VREF FOR THE ISL267452 FOR
VDD = 3V
5
6
4
5
3
4
2
3
INL (LSB)
ZERO CODE ERROR (LSB)
1.5
VREF (V)
2
3V
1
POS INL
1
0
-1
NEG INL
-2
0
-3
5V
-1
-4
-5
-2
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VREF (V)
FIGURE 15. CHANGE IN OFFSET ERROR vs REFERENCE VOLTAGE
FOR VDD = 5V AND 3V FOR THE ISL267452
9
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VREF (V)
FIGURE 16. CHANGE IN INL vs VREF FOR THE ISL267452 FOR
VDD = 5V
FN8255.0
July 26, 2012
ISL267452
Typical Performance Characteristics
12.0
(Continued)
70k
11.5
60k
11.0
3V
10.5
50k
10.0
HITS
ENOB (BITS)
65,516
CODES
5V
9.5
40k
9.0
30k
8.5
20k
8.0
10k
7.5
10
CODES
7.0
10
CODES
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
2044
2045
VREF (V)
Functional Description
VIN–
ACQ
CS
ACQ
ACQ
CONV
CONV
2048
2049
2050
FIGURE 18. HISTOGRAM OF 10,000 CONVERSIONS OF A DC INPUT
FOR THE ISL267452 WITH VDD = 5V
An external clock must be applied to the SCLK pin to generate a
conversion result. The allowable frequency range for SCLK is
10kHz to 10MHz (555kSPS). Serial output data is transmitted on
the falling edge of SCLK. The receiving device (FPGA, DSP or
Microcontroller) may latch the data on the rising edge of SCLK to
maximize set-up and hold times.
A stable, low-noise reference voltage must be applied to the
VREF pin to set the full-scale input range and common-mode
voltage. See “Voltage Reference Input” on page 11 for more
details.
ADC Transfer Function
The output coding for the ISL267452 is twos complement. The
first code transition occurs at successive LSB values (i.e., 1 LSB,
2 LSB, and so on). The LSB size of the ISL267452 is
2*VREF/4096. The ideal transfer characteristic of the
ISL267452 is shown in Figure 20.
011...111
SAR
LOGIC
1LSB = 2•VREF/4096
011...110
ADC CODE
DAC
The ISL267452 is based on a successive approximation register
(SAR) architecture utilizing capacitive charge redistribution
digital to analog converters (DACs). Figure 19 shows a simplified
representation of the converter. During the acquisition phase
(ACQ) the differential input is stored on the sampling capacitors
(CS). The comparator is in a balanced state since the switch
across its inputs is closed. The signal is fully acquired after tACQ
has elapsed, and the switches then transition to the conversion
phase (CONV) so the stored voltage may be converted to digital
format. The comparator will become unbalanced when the
differential switch opens and the input switches transition
(assuming that the stored voltage is not exactly at mid-scale).
The comparator output reflects whether the stored voltage is
above or below mid-scale, which sets the value of the MSB. The
SAR logic then forces the capacitive DACs to adjust up or down by
one quarter of full-scale by switching in binarily weighted
capacitors. Again, the comparator output reflects whether the
stored voltage is above or below the new value, setting the value
of the next lowest bit. This process repeats until all 12 bits have
been resolved.
VIN+
2047
CODE
FIGURE 17. CHANGE IN ENOB vs REFERENCE VOLTAGE FOR
VDD = 5V AND 3V FOR THE ISL267452
CONV
2046
000...001
000...000
111...111
100...010
100...001
CS
100...000
DAC
VREF
FIGURE 19. SAR ADC ARCHITECTURAL BLOCK DIAGRAM
–VREF
+ ½LSB
0V
+VREF +VREF
– 1½LSB – 1LSB
ANALOG INPUT
VIN+ – (VIN–)
FIGURE 20. IDEAL TRANSFER CHARACTERISTICS
10
FN8255.0
July 26, 2012
ISL267452
Analog Input
The ISL267452 features a fully differential input with a nominal
full-scale range equal to twice the applied VREF voltage. Each
input swings VREF VP-P, 180° out-of-phase from one another for
a total differential input of 2*VREF (refer to Figure 21).
Differential signaling offers several benefits over a single-ended
input, such as:
• Doubling of the full-scale input range (and therefore the
dynamic range)
• Improved even order harmonic distortion
Note that there is a trade-off between VREF and the allowable
common mode input voltage (VCM). The full-scale input range is
proportional to VREF; therefore the VCM range must be limited
for larger values of VREF in order to keep the absolute maximum
and minimum voltages on the VIN+ and VIN– pins within
specification. Figures 23 and 24 illustrate this relationship for 5V
and 3V operation, respectively. The dashed lines show the
theoretical VCM range based solely on keeping the VIN+ and
VIN– pins within the supply rails. Additional restrictions are
imposed due to the required headroom of the input circuitry,
resulting in practical limits shown by the shaded area.
VCM
• Better noise immunity due to common mode rejection
5.0
VIN+
ISL267452
VCM
4.25V
4.0
VREFP-P
2.0
VIN–
VREFP-P
3.25V
3.0
1.75V
1.0
FIGURE 21. DIFFERENTIAL INPUT SIGNALING
Figure 22 shows the relationship between the reference voltage
and the full-scale input range for two different values of VREF.
VREF
0.5
1.0
1.5
2.0
2.5
3.0
3.5
FIGURE 23. RELATIONSHIP BETWEEN VREF AND VCM FOR VDD = 5V
VCM
V
2.5
5.0
2.5
VIN–
4.0
VIN+
2.0VP-P
3.0
2.0V
2.0
VCM
1.5
2.0
1.0V
1.0
1.0
t
0.5
VREF = 2V
VREF
V
0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
FIGURE 24. RELATIONSHIP BETWEEN VREF AND VCM FOR VDD = 3V
5.0
VIN–
4.0
Voltage Reference Input
VIN+
2.5VP-P
VCM
3.0
2.0
1.0
t
VREF = 2.5V
FIGURE 22. RELATIONSHIP BETWEEN VREF AND FULL-SCALE RANGE
An external low-noise reference voltage must be applied to the VREF
pin to set the full-scale input range of the converter. The reference
input accepts voltages ranging from 0.1V to 2.2V for 3V operation
and 0.1V to 3.5V for 5V operation. The device is specified with a
reference voltage of 2.5V for 5V operation and 2.0V for 3V
operation.
Figures 26 and 27 illustrate possible voltage reference options for
the ISL267452. Figure 26 uses the precision ISL21090 voltage
reference, which exhibits exceptionally low drift and low noise. The
ISL21090 must use a power supply greater than 4.7V. The VREF
input pin of the ISL267452 uses very low current, so the decoupling
capacitor can be small (0.1µF).
Figure 27 illustrates the ISL21010 voltage reference being used
with the ISL267452. The ISL21010 series voltage references have
higher noise and drift than the ISL26090 devices, but they consume
very low operating current and are excellent for battery-powered
applications.
11
FN8255.0
July 26, 2012
ISL267452
100
10
POWER (mW)
VDD = 5V
1
VDD = 3V
0.1
0.01
0
50
100
150
200
250
300
350
THROUGHPUT (kSPS)
FIGURE 25. POWER CONSUMPTION vs THROUGHPUT RATE
5V
+
BULK
0.1µF
0.1µF
1 DNC
DNC
8
2 VIN
DNC
7
3 COMP
VOUT
6
4 GND
TRIM
5
VDD
ISL267452
VREF
2.5V
0.1µF
ISL21090
FIGURE 26. PRECISION VOLTAGE REFERENCE FOR +5V SUPPLY
+3.0V TO +3.6V
OR +5V
VIN
VOUT
+
BULK
1
GND
3
0.1µF
0.1µF
VDD
ISL267452
VREF
2
1.25, 2.048 OR 2.5V
ISL21010
0.1µF
FIGURE 27. VOLTAGE REFERENCE FOR +3.0V TO +3.6V, OR FOR +5V SUPPLY
Converter Operation
The ISL267452 is designed to minimize power consumption by
only powering up the SAR comparator during conversion time.
When the converter is in track mode (its sample capacitors are
tracking the input signal) the SAR comparator is powered down.
The state of the converter is dictated by the logic state of CS.
When CS is high, the SAR comparator is powered down while the
sampling capacitor array is tracking the input. When CS
transitions low, the capacitor array immediately captures the
analog signal that is being tracked. After CS is taken low, the
SCLK pin is toggled 16 times. For the first 3 clocks, the
comparator is powered up and auto-zeroed, then the SAR
decision process is begun. This process uses 12 SCLK cycles.
Each SAR decision is presented to the SDATA output on the next
clock cycle after the SAR decision is performed. The SAR process
12
(12 bits) is completed on SCLK cycle 15. At this point in time, the
SAR comparator is powered down and the capacitor array is
placed back into Track mode. The last SAR comparator decision
is output from SDATA on the 16th SCLK cycle. When the last data
bit is output from SDATA, the output switches to a logic 0 until CS
is taken high, at which time, the SDATA output enters a High-Z
state.
Figure 28 on page 13 illustrates the system timing for the
ISL267452.
FN8255.0
July 26, 2012
ISL267452
FIGURE 28. ISL267452 SYSTEM TIMING
Power-On Reset
Application Hints
When power is first applied, the ISL267452 performs a power-on
reset that requires approximately 2.5ms to execute. After this is
complete, a single dummy conversion must be executed (by
taking CS low) in order to initialize the switched capacitor track
and hold. The dummy conversion cycle will take 1.6µs with an
10MHz SCLK. Once the dummy cycle is complete, the ADC mode
will be determined by the state of CS. Regular conversions can be
started immediately after this dummy cycle is completed and
time has been allowed for proper acquisition.
Grounding and Layout
Acquisition Time
To achieve the maximum sample rate (555kSps) in the
ISL267452 device, the maximum acquisition time is 200ns. For
slower conversion rates, or for conversions performed using a
slower SCLK value than 10MHz, the minimum acquisition time is
200ns. This minimum acquisition time also applies to all the
devices if short cycling is utilized.
Short Cycling
In cases where a lower resolution conversion is acceptable, CS
can be pulled high before all SCLK falling edges have elapsed.
This is referred to as short cycling, and it can be used to further
optimize power dissipation. In this mode, a lower resolution
result will be output, but the ADC will enter static mode sooner
and exhibit a lower average power consumption than if the
complete conversion cycle were carried out. The minimum
acquisition time (tACQ) requirement of 200ns must be met for
the next conversion to be valid.
The printed circuit board that houses the ISL267452 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. This facilitates the
use of ground planes that can be easily separated. A minimum
etch technique is generally best for ground planes since it gives
the best shielding. Digital and analog ground planes should be
joined in only one place, and the connection should be a star
ground point established as close to the GND pin on the
ISL267452 as possible. Avoid running digital lines under the
device, as this will couple noise onto the die. The analog ground
plane should be allowed to run under the ISL267452 to avoid
noise coupling.
The power supply lines to the device should use as large a trace
as possible to provide low impedance paths and reduce the
effects of glitches on the power supply line.
Fast switching signals, such as clocks, should be shielded with
digital ground to avoid radiating noise to other sections of the
board, and clock signals should never run near the analog inputs.
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
reduces the effects of feedthrough through the board. A
microstrip technique is by far the best but is not always possible
with a double-sided board.
In this technique, the component side of the board is dedicated
to ground planes, while signals are placed on the solder side.
Good decoupling is also important. All analog supplies should be
decoupled with μF tantalum capacitors in parallel with 0.1μF
capacitors to GND. To achieve the best from these decoupling
components, they must be placed as close as possible to the
device.
13
FN8255.0
July 26, 2012
ISL267452
Terminology
Aperture Jitter
Signal-to-(Noise + Distortion) Ratio (SINAD)
This is the sample-to-sample variation in the effective point in
time at which the actual sample is taken.
This is the measured ratio of signal-to-(noise + distortion) at the
output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals up
to half the sampling frequency (fs/2), excluding DC. The ratio is
dependent on the number of quantization levels in the
digitization process; the more levels, the smaller the quantization
noise. The theoretical signal-to-(noise + distortion) ratio for an
ideal N-bit converter with a sine wave input is given by
Equation 1:
Signal-to-(Noise + Distortion) = ( 6.02 N + 1.76 )dB
(EQ. 1)
Thus, for a 12-bit converter, this is 74dB.
The full power bandwidth of an ADC is that input frequency at
which the amplitude of the reconstructed fundamental is
reduced by 3dB for a full-scale input.
Common-Mode Rejection Ratio (CMRR)
The common-mode rejection ratio is defined as the ratio of the
power in the ADC output at full-scale frequency, f, to the power of
a 250mVP-P sine wave applied to the common-mode voltage of
VIN+ and VIN– of frequency fs:
CMRR ( dB ) = 10 log ( Pfl ⁄ Pfs )
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the ISL267452, it is defined
as Equation 2:
V 22 + V 32 + V 42 + V 52 + V 62
THD ( dB ) = 20 log ----------------------------------------------------------------------V 12
Full Power Bandwidth
(EQ. 2)
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5, and V6 are the rms amplitudes of the second to the sixth
harmonics.
(EQ. 3)
Pf is the power at the frequency f in the ADC output; Pfs is the
power at frequency fs in the ADC output.
Integral Nonlinearity (INL)
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function.
Differential Nonlinearity (DNL)
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Peak Harmonic or Spurious Noise (SFDR)
Zero-Code Error
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding DC) to the rms value of the
fundamental (also referred to as Spurious Free Dynamic Range
(SFDR)). Normally, the value of this specification is determined by
the largest harmonic in the spectrum, but for ADCs where the
harmonics are buried in the noise floor, it will be a noise peak.
This is the deviation of the midscale code transition (111...111 to
000...000) from the ideal VIN+ – VIN– (i.e., 0 LSB).
Intermodulation Distortion
Negative Gain Error
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m and n = 0, 1, 2 or 3. Intermodulation distortion terms are those
for which neither m nor n are equal to zero. For example, the
second order terms include (fa + fb) and (fa – fb), while the third
order terms include (2fa + fb), (2fa – fb), (fa + 2fb), and (fa –2fb).
This is the deviation of the first code transition (100...000 to
100...001) from the ideal VIN+ – VIN– (i.e., – REF + 1 LSB), after
the zero code error has been adjusted out.
The ISL267452 is tested using the CCIF standard, where two
input frequencies near the top end of the input bandwidth are
used. In this case, the second order terms are usually distanced
in frequency from the original sine waves, while the third order
terms are usually at a frequency close to the input frequencies.
As a result, the second and third order terms are specified
separately. The calculation of the intermodulation distortion is as
per the THD specification, where it is the ratio of the rms sum of
the individual distortion products to the rms amplitude of the
sum of the fundamentals expressed in dBs.
Positive Gain Error
This is the deviation of the last code transition (011...110 to
011...111) from the ideal VIN+ – VIN– (i.e., +REF – 1 LSB), after
the zero code error has been adjusted out.
Track and Hold Acquisition Time
The track and hold acquisition time is the minimum time
required for the track and hold amplifier to remain in track mode
for its output to reach and settle to within 0.5 LSB of the applied
input signal.
Power Supply Rejection Ratio (PSRR)
The power supply rejection ratio is defined as the ratio of the
power in the ADC output at full-scale frequency, f, to ADC VDD
supply of frequency fS. The frequency of this input varies from
1kHz to 1MHz.
PSRR ( dB ) = 10 log ( Pf ⁄ Pfs )
(EQ. 4)
Pf is the power at frequency f in the ADC output; Pfs is the power
at frequency fs in the ADC output.
Aperture Delay
This is the amount of time from the leading edge of the sampling
clock until the ADC actually takes the sample.
14
FN8255.0
July 26, 2012
ISL267452
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
July 26, 2012
FN8255.0
CHANGE
Initial Release.
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on
intersil.com: ISL267452
To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff
FITs are available from our website at: http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
15
FN8255.0
July 26, 2012
ISL267452
Small Outline Transistor Plastic Packages (SOT23-8)
0.20 (0.008)
CL
6
7
VIEW C
INCHES
5
CL
CL
E
1
2
8 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
e
b
8
P8.064
M C
3
E1
MIN
MAX
MIN
MAX
NOTES
A
0.036
0.057
0.90
1.45
-
A1
0.000
0.0059
0.00
0.15
-
A2
0.036
0.051
0.90
1.30
-
b
0.009
0.015
0.22
0.38
-
b1
0.009
0.013
0.22
0.33
c
0.003
0.009
0.08
0.22
6
4
e1
C
D
CL
A
MILLIMETERS
SYMBOL
A2
A1
SEATING
PLANE
-C-
0.10 (0.004)
c1
0.003
0.008
0.08
0.20
6
D
0.111
0.118
2.80
3.00
3
E
0.103
0.118
2.60
3.00
-
E1
0.060
0.067
1.50
1.70
3
e
0.0256 Ref
0.65 Ref
-
e1
0.0768 Ref
1.95 Ref
-
L
C
0.014
0.022
0.35
0.55
L1
0.024 Ref.
0.60 Ref.
L2
0.010 Ref.
0.25 Ref.
N
8
8
5
WITH
b
R
0.004
-
0.10
PLATING
b1
R1
0.004
0.010
0.10
0.25
α
0o
8o
0o
8o
c
c1
4
-
Rev. 2 9/03
NOTES:
BASE METAL
1. Dimensioning and tolerance per ASME Y14.5M-1994.
2. Package conforms to EIAJ SC-74 and JEDEC MO178BA.
4X θ1
3. Dimensions D and E1 are exclusive of mold flash, protrusions, or gate
burrs.
R1
4. Footlength L measured at reference to gauge plane.
5. “N” is the number of terminal positions.
R
GAUGE PLANE
SEATING
PLANE
L
C
L1
α
6. These Dimensions apply to the flat section of the lead between 0.08mm
and 0.15mm from the lead tip.
7. Controlling dimension: MILLIMETER. Converted inch dimensions
are for reference only
L2
4X θ1
VIEW C
16
FN8255.0
July 26, 2012
Similar pages