DATASHEET

DATASHEET
16-Bit Long-Reach Video Automotive Grade SERDES
with Bi-directional Side-Channel
ISL76321
Features
The ISL76321 is a serializer/deserializer of LVCMOS parallel
video data. The video data presented to the serializer on the
parallel LVCMOS bus is serialized into a high-speed differential
signal. This differential signal is converted back to parallel video
at the remote end by the deserializer. It also transports auxiliary
data bi-directionally over the same link during the video vertical
retrace interval. I2C bus mastering allows the placement of
external slave devices on the remote side of the link. An I2C
controller can be placed on either side of the link allowing
bidirectional I2C communication through the link to the external
devices on the other side. Both chips can be fully configured from
a single controller or independently by local controllers.
• 16-bit RGB transport over a single differential pair
Related Literature
• ISL34341 Data Sheet “WSVGA 24-Bit Long-Reach Video
SERDES with Bi-directional Side-Channel”
• 6MHz to 50MHz pixel clock rates
• AEC-Q100 qualified component
• Bi-directional auxiliary data transport without extra bandwidth
and over the same differential pair
• Hot-plugging with automatic resynchronization every HSYNC
• I2C bus mastering to the remote side of the link with a
controller on either the serializer or deserializer
• Selectable clock edge for parallel data output
• DC-balanced with industry standard 8b/10b line code allows
AC-coupling, providing immunity against ground shifts
• 16 programmable settings each for transmitter amplitude
boost and pre-emphasis and receiver equalization, allow for
longer cable lengths and higher data rates
• Slew rate control and spread spectrum capability on outputs
reduce the potential for EMI
• Same device for serializer and deserializer simplifies inventory
Applications
• Video entertainment systems
• Remote cameras
RSTB/PDB
VDD_CR
VDD_CDR
VDD_P
VDD_IO
16
RGB
SERIOP
VIDEO
TARGET
DE
VIDEO_TX
I2CA1
I2CA0
3.16k
GND_CR
GND_AN
GND_P
GND_TX
GND_CDR
GND_IO
VSYNC
HSYNC
PCLK_OUT
PCLK_IN
TEST_EN
REF_CLK
ISL76321
SERION DESERIALIZER
REF_RES
27nF
SERION
VIDEO_TX
1.8V VDD_IO
27nF
27nF
I2CA1
I2CA0
TEST_EN
REF_RES
3.16k
VDD_AN
VDD_TX
27nF
SERIOP
ISL76321
SERIALIZER
GND_CR
GND_AN
GND_P
GND_TX
GND_CDR
GND_IO
VSYNC
HSYNC
DE
PCLK_IN
RSTB/PDB
VDD_CR
VDD_CDR
RGB
VIDEO
SOURCE
3.3V
1.8V VDD_IO
VDD_P
VDD_IO
VDD_TX
16
VDD_AN
3.3V
VDD_IO
FIGURE 1. TYPICAL APPLICATION
May 1, 2015
FN7803.2
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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ISL76321
Block Diagram
SCL
I2C
SDA
VCM
GENERATOR
RAM
SERIOP
PREEMPHASIS
TX
3
V/H/DE
TDM
8b/10b
RGB
SERION
MUX
DEMUX
16
RX
EQ
VIDEO_TX
(HI)
CDR
PCLK_IN
(REF_CLK WHEN
VIDEO_TX IS LO)
x20
PCLK_ OUT
x20
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ISL76321
Pin Configuration
GND_IO
RGBA7
RGBA6
RGBA5
RGBA4
RGBA3
RGBA2
RGBA1
RGBA0
PCLK_OUT
VDD_IO
GND_IO
ISL76321
(48 LD QFN)
TOP VIEW
48
47
46
45
44
43
42
41
40
39
38
37
VDD_IO
1
36 VDD_CDR
RGBC0
2
35 GND_CDR
RGBC1
3
34 VDD_TX
RGBC2
4
33 SERIOP
RGBC3
5
32 SERION
RGBC4
6
31 GND_TX
RGBC5
7
30 VDD_AN
RGBC6
8
29 GND_AN
RGBC7
9
28 REF_RES
STATUS 10
27 MASTER
16
17
18
19
20
21
VSYNC
VHSYNCPOL
VIDEO_TX
PCLK_IN
GND_P
22
23
24
SDA
15
SCL
14
VDD_P
13
HSYNC
25 I2CA1
DATAEN
RSTB/PDB 12
VDD_CR
26 I2CA0
GND_CR
TEST_EN 11
Pin Descriptions
DESCRIPTION
PIN NUMBER
PIN NAME
47, 46
45, 44
43, 42
41, 40
9, 8
7, 6
5, 4
3, 2
RGBA7, RGBA6
RGBA5, RGBA4
RGBA3, RGBA2
RGBA1, RGBA0
RGBC7, RGBC6
RGBC5, RGBC4
RGBC3, RGBC2
RGBC1, RGBC0
Parallel video data LVCMOS inputs with Hysteresis Parallel video data LVCMOS outputs
16
HSYNC
Horizontal (line) Sync LVCMOS input with Hysteresis Horizontal (line) Sync LVCMOS output
17
VSYNC
Vertical (frame) Sync LVCMOS input with Hysteresis Vertical (frame) Sync LVCMOS output
15
DATAEN
Video Data Enable LVCMOS input with Hysteresis
Video Data Enable LVCMOS output
20
PCLK_IN
Pixel clock LVCMOS input
PLL reference clock LVCMOS input
39
PCLK_OUT
Default; not used
Recovered clock LVCMOS output
33, 32
SERIOP, SERION
High-speed differential serial I/O
High speed differential serial I/O
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SERIALIZER
DESERIALIZER
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May 1, 2015
ISL76321
Pin Descriptions (Continued)
DESCRIPTION
PIN NUMBER
PIN NAME
SERIALIZER
18
VHSYNCPOL
19
VIDEO_TX
24, 23
SDA, SCL (Note 1)
I2C Interface Pins (I2C DATA, I2C CLK), weak internal pull-up
25, 26
I2CA[1:0] (Note 1)
I2C Device Address
27
MASTER
12
RSTB/PDB
10
STATUS
28
REF_RES
21
GND_P (Note 2)
PLL Ground
37, 48
GND_IO (Note 2)
Digital (Parallel and Control) Ground
35
GND_CDR (Note 2)
31
GND_TX (Note 2)
Analog (Serial) Output Ground
29
GND_AN (Note 2)
Analog Bias Ground
13
GND_CR (Note 2)
Core Logic Ground
14
VDD_CR
Core Logic VDD
34
VDD_TX
Analog (Serial) Output VDD
30
VDD_AN
Analog Bias VDD
36
VDD_CDR
1, 38
VDD_IO (Note 1)
22
VDD_P
11
TEST_EN
Exposed Pad
PAD
DESERIALIZER
CMOS input for HSYNC and VSYNC Polarity
1: HSYNC & VSYNC active low
0: HSYNC & VSYNC active high
CMOS input for video flow direction
1: Video serializer
0: Video deserializer
I2C Master Mode
1: Master
0: Slave
CMOS input for Reset and Power-down. For normal operation, this pin should be driven high. When this
pin is taken low, the device will be reset. If this pin stays low, the device will be in PD mode.
CMOS output for Receiver Status:
1: Valid 8b/10b data received
0: No valid data detected
Note: serializer and deserializer switch roles during side-channel reverse traffic
Analog bias setting resistor connection; use 3.16kΩ ±1% to ground
Analog (Serial) Data Recovery Ground
Analog (Serial) Data Recovery VDD
Digital (Parallel and Control) VDD
PLL VDD
Must be connected to ground
Must be connected to ground, not an electrical connection
NOTES:
1. Pins with the same name are internally connected together. However, this connection must NOT be used for connecting together external components
or features.
2. The various differently-named Ground pins are internally weakly connected. They must be tied together externally. The different names are provided
to assist in minimizing the current loops involved in bypassing the associated supply VDD pins. In particular, for ESD testing, they should be
considered a common connection.
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ISL76321
Ordering Information
PART NUMBER
(Notes 3, 4, 5)
ISL76321ARZ
PART
MARKING
ISL76321 ARZ
TEMP. RANGE
(°C)
-40 to +105
PACKAGE
(RoHS Compliant)
48 Ld QFN
PKG.
DWG. #
L48.7x7C
NOTES:
3. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pbfree products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
5. For Moisture Sensitivity Level (MSL), please see device information page for ISL76321. For more information on MSL please see techbrief TB363.
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ISL76321
Absolute Maximum Ratings
Thermal Information
Supply Voltage
VDD_P to GND_P, VDD_TX to GND_TX, VDD_IO to GND_IO . . -0.5V to 4.6V
VDD_CDR to GND_CDR, VDD_CR to GND_CR . . . . . . . . . . . . . . . . -0.5V to 2.5V
Between any pair of GND_P, GND_TX, GND_IO, GND_CDR,
GND_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.1V to 0.1V
3.3V Tolerant LVTTL/LVCMOS
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD_IO +0.3V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . .-0.3V to VDD_IO + 0.3V
Differential Output Current . . . . . . . . . . . . . . . . . . . . Short Circuit Protected
LVTTL/LVCMOS Outputs. . . . . . . . . . . . . . . . . . . . . . . Short Circuit Protected
ESD Rating
Human Body Model (Tested per JESD22-A114E)
All pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4kV
SERIOP/N
(All VDD Connected, all GND Connected) . . . . . . . . . . . . . . . . . . . . . . 8kV
Machine Model (Tested per JESD-A115-A) . . . . . . . . . . . . . . . . . . . . 200V
Charge Device Model (Tested per AEC-Q100-011-B) . . . . . . . . . . . 2000V
Latch-up (Tested per JESD-78B; Class2, Level A) . . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
JA
JC (°C/W)
QFN Package (Notes 6, 7) . . . . . . . . . . . . . .
32
3.7
Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327mW
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+125°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
6. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
7. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Unless otherwise indicated, all data is for: VDD_CDR = VDD_CR = 1.8V, VDD_IO = 3.3V,
VDD_TX = VDD_P = VDD_AN = 3.3V, TA = +25°C, Ref_Res = 3.16kΩ, High-speed AC-coupling capacitor = 27nF. Boldface limits apply over the operating
temperature range, -40°C to +105°C.
MIN
(Note 10)
TYP
MAX
(Note 10)
UNITS
VDD_CDR, VDD_CR
1.7
1.8
1.9
V
VDD_TX, VDD_P, VDD_AN, VDD_IO
3.0
3.3
3.6
V
PARAMETER
SYMBOL
CONDITIONS
POWER SUPPLY VOLTAGE
SERIALIZER POWER SUPPLY CURRENTS
Total 1.8V Supply Current
PCLK_IN = 45MHz
62
80
mA
Total 3.3V Supply Current
(Note 8)
40
52
mA
Total 1.8V Supply Current
PCLK_IN = 45MHz
66
76
mA
Total 3.3V Supply Current
(Note 8)
50
63
mA
RSTB = GND
10
mA
0.5
mA
DESERIALIZER POWER SUPPLY CURRENTS
POWER-DOWN SUPPLY CURRENT
Total 1.8V Power-Down Supply Current
Total 3.3V Power-Down Supply Current
PARALLEL INTERFACE
High Level Input Voltage
VIH
Low Level Input Voltage
VIL
Input Leakage Current
IIN
High Level Output Voltage
VOH
IOH = -4.0mA, VDD_IO = 3.0V
Low Level Output Voltage
VOL
IOL = 4.0mA, VDD_IO = 3.6V
Output Short Circuit Current
IOSC
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2.0
-1
V
±0.01
0.8
V
1
µA
2.6
V
0.4
V
35
mA
FN7803.2
May 1, 2015
ISL76321
Electrical Specifications
Unless otherwise indicated, all data is for: VDD_CDR = VDD_CR = 1.8V, VDD_IO = 3.3V,
VDD_TX = VDD_P = VDD_AN = 3.3V, TA = +25°C, Ref_Res = 3.16kΩ, High-speed AC-coupling capacitor = 27nF. Boldface limits apply over the operating
temperature range, -40°C to +105°C. (Continued)
PARAMETER
SYMBOL
Output Rise and Fall Times
tOR/tOF
CONDITIONS
MIN
(Note 10)
TYP
MAX
(Note 10)
UNITS
Slew rate control set to min
CL = 8pF
1
ns
Slew rate control set to max,
CL = 8pF
4
ns
SERIALIZER PARALLEL INTERFACE
PCLK_IN Frequency
fIN
6
PCLK_IN Duty Cycle
tIDC
40
Parallel Input Setup Time
tIS
3.5
ns
Parallel Input Hold Time
tIH
1.0
ns
PCLK_OUT Frequency
fOUT
6
PCLK_OUT Duty Cycle
tODC
50
50
MHz
60
%
DESERIALIZER PARALLEL INTERFACE
PCLK_OUT Period Jitter (rms)
PCLK_OUT Spread Width
PCLK_OUT to Parallel Data Outputs
(includes Sync and DE pins)
Deserializer Output Latency
50
MHz
50
%
tOJ
Clock randomizer off
0.5
%tPCLK
tOSPRD
Clock randomizer on
±20
%tPCLK
tDV
Relative to PCLK_OUT,
(Note 9)
-1.0
tCPD
Inherent in the design
4
9
100
µs
PCLK_OUT is the
recovered clock
1500
5000
ppm
TXCN = 0x00
650
800
5.5
ns
14
PCLK
DESERIALIZER REFERENCE CLOCK (REF_CLK IS FED INTO PCLK_IN)
REF_CLK Lock Time
tPLL
REF_CLK to PCLK_OUT Maximum Frequency
Offset
HIGH-SPEED TRANSMITTER
HS Differential Output Voltage, Transition Bit
HS Differential Output Voltage, Non-Transition
Bit
VODTR
VODNTR
900
mVP-P
TXCN = 0x0F
900
mVP-P
TXCN = 0xF0
1100
mVP-P
TXCN = 0xFF
1300
mVP-P
TXCN = 0x00
650
800
900
mVP-P
TXCN = 0x0F
900
mVP-P
TXCN = 0xF0
430
mVP-P
TXCN = 0xFF
600
mVP-P
V
HS Generated Output Common Mode Voltage
VOCM
2.35
HS Common Mode Serializer-Deserializer
Voltage Difference
VCM
10
20
80
100
120
Ω
4
7
10
PCLK
HS Differential Output Impedance
ROUT
HS Output Latency
tLPD
Inherent in the design
HS Output Rise and Fall Times
tR/tF
20% to 80%
HS Differential Skew
tSKEW
mV
150
ps
<10
ps
HS Output Random Jitter
tRJ
PCLK_IN = 45MHz
6
psrms
HS Output Deterministic Jitter
tDJ
PCLK_IN = 45MHz
25
psP-P
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ISL76321
Electrical Specifications
Unless otherwise indicated, all data is for: VDD_CDR = VDD_CR = 1.8V, VDD_IO = 3.3V,
VDD_TX = VDD_P = VDD_AN = 3.3V, TA = +25°C, Ref_Res = 3.16kΩ, High-speed AC-coupling capacitor = 27nF. Boldface limits apply over the operating
temperature range, -40°C to +105°C. (Continued)
PARAMETER
SYMBOL
CONDITIONS
MIN
(Note 10)
TYP
MAX
(Note 10)
UNITS
HIGH SPEED RECEIVER
HS Differential Input Voltage
VID
HS Generated Input Common Mode Voltage
VICM
HS Differential Input Impedance
RIN
75
mVP-P
2.32
80
HS Maximum Jitter Tolerance
100
V
120
0.50

UIP-P
I2C
I2C Clock Rate (on SCL)
fI2C
100
400
kHz
I2C Clock Pulse Width (HI or LO)
1.3
I2C Clock Low to Data Out Valid
0
I2C Start/Stop Setup/Hold Time
0.6
µs
I2C Data in Setup Time
100
ns
I2C Data in Hold Time
100
ns
I2C Data out Hold Time
100
ms
µs
1
µs
NOTES:
8. IDDIO is nominally 50µA and not included in this total as it is dominated by the loading of the parallel pins.
9. This parameter is the output data skew from the invalid edge of PCLK_OUT. The setup and hold time provided to a system is dependent on the PCLK
frequency and is calculated as follows: 0.5 * fIN - tDV..
10. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
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Timing Diagrams
BIT BOUNDARY
BIT BOUNDARY
BIT BOUNDARY
TXP
VOLTAGE
Tx SETTING
0x0F
0x00
VCM
0xFF
0xF0
TXN
VOD TRANSITION BIT
VOD NON-TRANSITION BIT
FIGURE 2. VOD vs TX SETTING
SERIALIZER MODE
1/FIN
tIDC
PCLK_IN
(RISING EDGE
DEFAULT)
tIS
RGBA[7:0],
RGBC[7:0]
tIH
VALID DATA
VALID DATA
DATA IGNORED DATA IGNORED
tIS
VALID DATA
tIH
HSYNC OR VSYNC
(HVSYNCPOL = ‘0’)
DATAEN
(ACTIVE ‘1’ DEFAULT)
FIGURE 3. PARALLEL VIDEO INPUT TIMING
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ISL76321
DESERIALIZER MODE
1/FOUT
tODC
tOR
PCLK_OUT
(RISING EDGE
DEFAULT)
tOF
tDV
RGBA[7:0],
RGBC[7:0]
VALID DATA
VALID DATA
PREVIOUS DATA HELD
VALID DATA
tDV
HSYNC OR VSYNC
( HVSYNCPOL = ‘0’)
DATAEN
(ACTIVE ‘1’ DEFAULT)
FIGURE 4. PARALLEL VIDEO OUTPUT TIMING
Applications
Detailed Description and Operation
A pair of ISL76321 SERDES transports 16-bit parallel video for
the ISL76321 along with auxiliary data over a single 100Ω
differential cable either to a display or from a camera. Auxiliary
data is transferred in both directions every video frame. This
feature can be used for remote configuration and telemetry.
The benefits include lower EMI, lower costs, greater reliability and
space savings. The same device can be configured to be either a
serializer or deserializer by setting one pin (VIDEO_TX),
simplifying inventory. RGBA/C, VSYNC, HSYNC, and DATAEN pins
are inputs in serializer mode and outputs in deserializer mode.
The video data presented to the serializer on the parallel LVCMOS
bus is serialized into a high-speed differential signal. This
differential signal is converted back to parallel video at the
remote end by the deserializer. The Side Channel data (auxiliary
data) is transferred between the SERDES pair during the first two
lines of the vertical video blanking interval.
impedance, as well as the pre-emphasis and equalization
settings. Functioning links of 25 meters are often possible at the
maximum frequency.
SERIOP and SERION pins incorporate internal differential
termination of the serial signal lines.
SERIO Pin AC-Coupling
AC-coupling minimizes the effects of DC common mode voltage
difference and local power supply variations between two
SERDES. The serializer outputs DC balanced 8b/10b line code,
which allows AC-coupling.
The AC-coupling capacitor on SERIO pins must be 27nF on the
serializer board and 27nF on the deserializer board. The value of
the AC-coupling capacitor is very critical since a value too small
will attenuate the high-speed signal at a low clock rate. A value
too big will slow down the turn around time for the side-channel.
It is an advantage to have the pair of capacitors as closely
matched as possible.
Receiver Reference Clock (REF_CLK)
When the side-channel is enabled, which is the default, there will
be a number of PCLK cycles uncertainty from frame-to-frame.
This should not cause sync problems with most displays, as this
occurs during the vertical front porch of the blanking period.
When properly configured, the SERDES link supports end-to-end
transport with fewer than one error in 1010 bits.
The reference clock (REF_CLK) for the PLL is fed into PCLK_IN
pin. REF_CLK is used to recover the clock from the high-speed
serial stream. REF_CLK is very sensitive to any instability. The
following conditions must be met at all times after power is
applied to the deserializer, or else the deserializer may need a
manual reset:
Differential Signals and Termination
• VDD must be applied and stable
The ISL76321 serializes the 16-bit parallel data plus 3 sync
signals at 20x the PCLK_IN frequency. The extra 2 bits per word
come from the 8b/10b encoding scheme which helps create the
highest quality serial link.
• REF_CLK frequency must be within the limits specified
The high bit rate of the differential serial data requires special
care in the layout of traces on PCBs, in the choice and assembly
of connectors, and in the cables themselves.
Power Supply Sequencing
PCB traces need to be adjacent, matched in length and drawn to
result in a differential 100Ω controlled impedance. For best EMI
performance, the cable should be low loss and have a differential
100Ω impedance. The maximum cable length for a functioning
link is dependent on the PCLK_IN frequency, the cable loss and
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• REF_CLK amplitude must be stable
A simple 3.3V CMOS crystal oscillator can be used for REF_CLK
The 3.3V supply must be higher than the 1.8V supply at all times,
including during power-up and power-down. To meet this
requirement, the 3.3V supply must be powered up before the
1.8V supply.
For the deserializer, REF_CLK must not be applied before the
device is fully powered up. Applying REF_CLK before power-up
FN7803.2
May 1, 2015
ISL76321
may require the deserializer to be manually reset. A 10ms delay
after the 1.8V supply is powered up guarantees normal
operation.
120Ω
Power Supply Bypassing and Layout
The serializer and deserializer functions rely on the stable
functioning of PLLs locked to local reference sources or locked to
an incoming signal. It is important that the various supplies
(VDD_P, VDD_AN, VDD_CDR, VDD_TX) be well bypassed over a
wide range of frequencies, from below the typical loop bandwidth
of the PLL to approaching the signal bit rate of the serial data. A
combination of different values of capacitors from 1000pF to
5µF or more with low ESR characteristics is generally required.
The higher value capacitor, in particular, needs to be chosen
carefully, with special care regarding its ESR. Very good results
can be obtained with multilayer ceramic capacitors (available
from many suppliers) and generally in small outlines (such as the
1210 outline suggested in the schematic shown in Figure 5),
which provide good bypass capabilities down to a few mΩ at
1MHz to 2MHz. Other capacitor technologies may also be
suitable (perhaps niobium oxide), but “classic” electrolytic
capacitors frequently have ESR values of above 1Ω, that nullify
any decoupling effect above the 1kHz to 10kHz frequency range.
Capacitors of 0.1µF offer low impedance in the 10MHz to 20MHz
region, and 1000pF capacitors in the 100MHz to 200MHz region.
In general, one of the lower value capacitors should be used at
each supply pin on the IC. Figure 5 shows the grounding of the
various capacitors to the pin corresponding to the supply pin.
Although all the ground supplies are tied together, the PCB layout
should be arranged to emulate this arrangement (at least for the
smaller value (high frequency) capacitors), as much as possible.
0.1µF
10µF
0.1µF
10µF
0.1µF
10µF
0.1µF
10µF
0.1µF
10µF
0.1µF
120Ω
120Ω
120Ω
The parallel LVCMOS VDD_IO supply is inherently less sensitive,
but since the RGB and SYNC/DATAEN signals can all swing on the
same clock edge, the current in these pins, and the
corresponding GND pins, can undergo substantial current flow
changes. Once again, a combination of different values of
capacitors over a wide range, with low ESR characteristics, is
desirable.
A set of arrangements of this type is shown in Figure 5, where
each supply is bypassed with a ferrite-bead-based choke, and a
range of capacitors. A “choke” is preferable to an “inductor” in
this application, since a high-Q inductor will be likely to cause one
or more resonances with the shunt capacitors, potentially
causing problems at or near those frequencies, while a “lossy”
choke will reflect a high impedance over a wide frequency range.
10µF
120Ω
120Ω
FIGURE 5. POWER SUPPLY BYPASSING
I2C Interface
The I2C interface allows access to internal registers used to
configure the SERDES and to obtain status information. A
serializer must be assigned a different address than its
deserializer counterpart if the side channel is used. The upper 5
bits are permanently set to 011 11 and the lower 2 bits
determined by pins as follows:
0
1
1
1
1
I2CA1
I2CA0
R/W
Thus, 4 SERDES can reside on the same bus. By convention,
when all address pins are tied low, the device address is referred
to as 0x78.
SCL and SDA are open drain to allow multiple devices to share
the bus. If not used, SCL and SDA should be tied to VDD_IO.
Side Channel Interface
The Side Channel is a mechanism for transferring data between
the two chips on each end of the link. This data is transferred
during video blanking so none of the video bandwidth is used. It
has three basic uses:
• Remote SERDES configuration
• Data exchanges between two processors
• Master Mode I2C commands to remote slaves
This interface allows the user to initialize registers, control and
monitor both SERDES chips from a single microcontroller which
can reside on either side of the serial link. This feature is used to
automatically transport the remote side SERDES chip’s status
back to a local register. The Side Channel needs to be enabled
(the default) for this to work. In the case where there is a
microcontroller on each side of the of the link, data can be
buffered and exchanged between the two. Up to 224 bytes can
be sent in each direction during each VSYNC active period.
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Master Mode
Exposed Pad
This is a mode activated by strapping the MASTER pin to a ‘1’ on
the ISL76321 on the remote side of the link from the
microcontroller. This is a virtual extension of the I2C interface
across the link that allows the local processor to read and write
slave devices connected to the remote side SERDES I2C bus. No
additional wires or components are needed other than the serial
link. The I2C commands and data are transferred during video
blanking causing no interruptions in the video data. In Master
mode, the data is transported across the link by the Side Channel
so the maximum throughput achievable would be the same. The
SCL and SDA frequency is adjustable through the programming
of a register. If a SERDES chip is configured as a master it is no
longer available for communication by a local microcontroller. It
is assumed that the SERDES is the only master.
While it is not a required electrical connection, it is
recommended that the exposed pad on the bottom of the
package be soldered to the circuit board. This will ensure that the
full power dissipation of the package can be utilized. The pad
should be connected to ground and not left floating. For best
thermal conductivity, 16 vias should connect the footprint for the
exposed pad on the circuit board to the ground plane. This
connection is not required for basic operation of the chip.
COPPER PAD
VIAS
16x
FIGURE 6. LAYOUT FOR THE EXPOSED PAD
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Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest Rev.
DATE
REVISION
CHANGE
May 1, 2015
FN7803.2
Updated AEC Q100 by adding a dash - now reading AEC-Q100 in Features on page 1
“Absolute Maximum Ratings” on page 6 - changed Charge Device Model from Charge Device Model
(Tested per JESD22-C101C) to (Tested per AEC-Q100-011-B)
December 23, 2013
FN7803.1
Page 13
- 2nd line of the disclaimer changed from:
"Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted"
to:
"Intersil Automotive Qualified products are manufactured, assembled and tested utilizing TS16949
quality systems as noted"
January 31, 2011
FN7803.0
Initial Release.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
For additional products, see www.intersil.com/en/products.html
Intersil Automotive Qualified products are manufactured, assembled and tested utilizing TS16949 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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Package Outline Drawing
L48.7x7C
48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (PUNCH QFN)
Rev 0, 1/08
7.00
EXPOSED PAD AREA
A
Z
B
X
6.75
48
48
6
PIN 1
INDEX AREA
6
PIN #1 INDEX AREA
1
6.75
7.00 REF
(4X)
1
7.00
(44X 0.50)
4
0.23
0.15
(4X)
(48X 0.40 ± 0.1mm)
TOP VIEW
0.100
4.10 REF
(4X)
C A B
BOTTOM VIEW
11 °±1° ALL AROUND
PACKAGE OUTLINE
Y
6.75
7.00
4.10
SIDE VIEW
R0.200
(48x 0.20)
(48x 0.60)
C0.400X45°X
(4X)
(0
.1
25
)
O
0.450
(48x 0.23)
UN
D
TYPICAL RECOMMENDED LAND PATTERN
)
(44x 0.50)
7.00
L
(A
LL
AR
R0.200
TYP.
1
R0.200 MAX
ALL AROUND
0.100 C
48
DETAIL "Z"
DETAIL "X"
R0.115
TYP.
0.65
0.85
NOTES:
1.
0.19~ 0.245
SEATING
0.080 C
0.025 ± 0.02
e
b
0.100
C A B
0.050
C
DETAIL "Y"
PLANE
C
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to JESD-MO220.
3. Unless otherwise specified, tolerance : Decimal ± 0.05, body
tolerance ± 0.1
4. Dimension b applies to the metallized terminal and is measured
between 0.18mm and 0.28mm from the terminal tip. Frame
base metal thickness 0.203mm.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
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