an9632

Operation of the HC5523, HC5515
Evaluation Board
TM
Application Note
December 1996
Features
AN9632
Ground Connections
The HC5523/15EVAL has two separate grounds designated as
AGND and BGND. AGND is the analog ground reference for
the SLIC. BGND is the battery ground reference, and is to be
connected to zero potential. All loop current and longitudinal
current flow from this ground. For proper SLIC operation,
AGND and BGND must be connected to a common ground,
with a potential difference not exceeding ±100mV.
• Includes the Ringing Relay
• Toggle Switch Programming for Logic States
• Convenient Monitoring of DET Via LED or Banana Jack
Output
• Logic Terminal Port for Easy Evaluation in Existing
Systems
HC5523/15EVAL Board SLIC Controls
• Includes On-Board Op Amp for Evaluation of Transhybrid
Balance
The design of the HC5523/15EVAL board incorporates five
SPDT switches. Four of the switches control the functional
state of the SLIC and the fifth controls the DET output.
• Pulse Metering Capability
Applications
Mode Control Switches
• Solid State Line Interface for Digital and Analog Telephone
Line Cards
The four switches labeled E0, E1, C1 and C2 are used to set
the operational mode of the HC5523. Three switches labeled
E0, C1 and C2 are used to set the operational mode of the
HC5515. Each switch is a Single Pole Double Throw (SPDT)
switch with a center open position.
Functional Description
The HC5523/15EVAL Subscriber Line Interface Circuit
(SLIC) evaluation board has provisions for full evaluation of
the voice and DC feeding characteristics of the HC5523 and
the HC5515, including the ringing function.
The two inputs labeled E0 and E1 are enable pins. The two
pins labeled C1 and C2 are used to select 1 of 4 operating
states of the SLIC. Refer to the HC5523 or the HC5515 data
sheet for a full description of the functionality of each pin.
SLIC functional control is provided using the toggle switches
E0, E1, C1 and C2. The logic truth tables for the HC5523
and the HC5515 are shown in Table 2 and Table 3
respectively. DET is available at both a banana jack for
monitoring with test instrumentation, as well as an LED for
visual verification.
If off-board mode control of the SLIC is desired, the four
switches can be set to center open position and driven by
logic at the logic terminal port. The logic terminal port is
located just below the toggle switches at the bottom of the
board. A common ground must exist between the
HC5523/15EVAL evaluation board and the off board logic. A
differential ground voltage may result in erroneous logic
states at the SLIC inputs.
Applying Power to the HC5523/15EVAL
Power Supply Connections
The HC5523/15EVAL requires three external power supplies
for operation. The supply voltages are labeled on the
HC5523/15EVAL as VCC +5V, VEE -5V and VBAT. The
typical supply currents, when the SLIC is in the Active mode
and terminated with a 600Ω load, are given in Table 1.
DET Select Switch
A switch is provided on the evaluation board to direct the
DET signal to one of two outputs. With the switch positioned
to the right, DET will illuminate the LED, when positioned to
the left, DET may be monitored at the banana jack using an
oscilloscope.
TABLE 1. POWER SUPPLY INFORMATION
SUPPLY
TYP (V)
TYP (mA)
VCC +5V
+5
11
VEE -5V
-5
1
VBAT, RSG is Open Circuit
-28
27
1. Power Supply Current Verification.
VBAT, RSG is 4.0kΩ
-48
30
2. Active Mode Verification.
Verifying the HC5523/15EVAL Operation
The operation of the HC5523/15EVAL and the sample part
can be verified by performing six tests:
3. Standby Mode Verification.
4. SLIC Gain Verification.
5. Ring Trip Detector Verification.
6. Transhybrid Balance Verification.
4-1
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Copyright
© Intersil Corporation 2000
Application Note 9632
The first four tests require a 600Ω load, an AC volt meter and
an oscilloscope. The last test requires a telephone and a
battery backed AC source. All of the tests require three
external supplies, one each for VCC, VEE, and VBAT.
Verify that the sample HC5523 or the HC5515 included with
the evaluation board is oriented in its socket correctly.
Correct orientation is with pin 1 pointing towards the bottom
of the board.
Application Tip: When terminating tip and ring on the
HC5523/15EVAL, it is handy to assemble terminators using
a Pomona MDP dual banana plug connector as the
terminating resistor receptacle. Refer to Figure 1 for details.
Test No. 2 - Active Mode Verification
This test verifies loop current operation and loop current
detection in the Active mode via the onboard LED.
SETUP:
1. Connect the power supplies to the HC5523/15EVAL.
2. Set VBAT to -48V.
3. Connect AGND and BGND to common ground point.
4. Connect V-REC pin to common ground point.
5. Terminate the HC5523 or the HC5515 with 600Ω load
across Tip and Ring.
6. Set the mode switches to E0 = 0, E1 = 1, C1 = 0, C2 = 1.
7. Position the DET select switch to the right.
GND
DISCUSSION:
A
B
FIGURE 1. TERMINATION ADAPTER
When power is applied to the SLIC a loop current will flow
from tip to ring through the 600Ω load. This loop current
triggers an internal detector that pulls the output of DET low,
illuminating the LED through the +5V supply. Once the LED
illuminates, remove the 600Ω termination and verify that the
LED turns off.
VERIFICATION:
1. LED is on when tip and ring are terminated with 600Ω.
Using the termination shown in Figure 1 provides an
unobtrusive technique for terminating tip and ring while still
providing access to both signals using the banana jack
feature of the MDP connector. Posts are also available that
fit into holes A and B, providing a solderable connection for
the terminating resistor.
Test No. 1 - Power Supply Current Verification
A quick check of evaluation board and the sample is to
measure the currents of each supply voltage. The readings
should be similar to the values listed in Table 1. The
measurements can be made using a series ammeter on
each supply, or power supplies with current displays.
2. LED is off when tip and ring are open circuit.
Test No. 3 - Standby Mode Verification
This test verifies loop current operation and loop current
detection in the Standby state via the banana jack interface.
SETUP:
1. Connect the power supplies to the HC5523/15EVAL.
2. Set VBAT to -48V.
3. Connect AGND and BGND to common ground point.
4. Connect V-REC pin to common ground point.
5. Terminate the HC5523 or the HC5515 with 600Ω load
across Tip and Ring.
6. Set the mode switches to E0 = 0, E1 = 1, C1 = 1, C2 = 1.
SETUP:
1. Connect the power supplies to the HC5523/15EVAL.
2. Set VBAT to -48V.
3. Connect AGND and BGND to common ground point.
7. Position the DET select switch to the left.
8. Connect an oscilloscope or DC voltmeter to the DET jack.
9. Monitor the VBAT supply current.
4. Connect V-REC pin to common ground point.
DISCUSSION:
5. Terminate the HC5523 or the HC5515 with 600Ω load
across Tip and Ring.
When power is applied to the SLIC, loop current will flow
from tip to ring through the 600Ω load. This loop current
triggers an internal detector that pulls the output of DET near
zero volts. Disconnecting the 600Ω termination will cause
DET to be pulled to the VCC rail. In Standby mode, the VBAT
current should be approximately 16.4mA with the 600Ω
termination and 0.8mA without the 600Ω termination.
6. Set the mode switches to E0 = 0, E1 = 1, C1 = 0, C2 = 1.
DISCUSSION:
Once setup is complete, apply power to the
HC5523/15EVAL and verify the supply currents listed in
Table 1. Note that special power supply sequencing is not
required for either the HC5523 or the HC5515.
4-2
Application Note 9632
DISCUSSION:
VERIFICATION:
1. DET is near 0V when terminated with 600Ω.
This test will verify that SLIC is operating properly and that
the SLIC is exhibiting unity gain. Unity gain will only exist if
the SLIC is properly terminated with 600Ω.
The 600Ω termination is not necessary for this test since the
phone provides this nominal impedance when off-hook.
Setting the mode switches as shown above will cause the
RINGRLY pin of the SLIC to energize the relay that is on the
evaluation board. The DT and DR comparator inputs will
sense the flow of DC loop current, causing the Ring Trip
comparator to sense when the phone is either on-hook or
off-hook. Refer to the HC5523 or the HC5515 data sheet for
a full description of the functionality of the Ring Trip Detector.
SETUP:
VERIFICATION:
2. DET is near the VCC rail when not terminated with 600Ω.
3. VBAT current is near 16.4mA when terminated.
4. VBAT current is near 0.8mA when not terminated.
Test No. 4 - SLIC Gain Verification
1. Connect the power supplies to the HC5523/15EVAL.
1. Phone starts ringing when power applied to test setup.
2. Set VBAT to- 48V.
3. Connect AGND and BGND to common ground point.
2. While ringing and on-hook, DET LED is not illuminated.
4. Terminate the HC5523 or the HC5515 with 600Ω load
across Tip and Ring.
• CAUTION: Short time durations of off-hook should be
maintained to protect RRT. In systems, the ring relay is
software controlled to turn off milliseconds after offhook is detected, hence limiting power dissipated in
RRT.
5. Set the mode switches to E0 = 0, E1 = 1, C1 = 0, C2 = 1.
6. Connect a sine wave generator to the V-REC input.
7. Set the generator for 0.775VRMS and 1kHz.
8. Connect an AC voltmeter across tip and ring.
DISCUSSION:
When terminated with 600Ω, the SLIC will exhibit unity gain
from the V-REC input pin to across tip and ring. The unity
gain results from the matched impedance that the 600Ω
termination represents to the internally synthesized 600Ω of
the SLIC. When an open circuit exists, a mismatch occurs
and the gain of the SLIC will double.
VERIFICATION:
3. While ringing, going off-hook will illuminate the LED.
4. When phone is returned to on-hook, LED will turn off.
5. Configure SLIC in Active mode to stop phone from
ringing. Set mode switches to E0 = 0, E1 = 1, C1 = 0,
C2 = 1.
Test No. 6 - Transhybrid Balance Verification
This test will verify the transhybrid balance circuitry for both
the voice path and the pulse metering (TELETAX) path. A
low distortion AC signal and a voltmeter are the only
additional hardware required to complete this test.
VOICE PATH
1. Tip to ring AC voltage of 0.775VRMS when terminated.
2. Tip to ring AC voltage of 1.55VRMS when not terminated.
Test No. 5 - Ring Trip Detector Verification
This test will verify the ringing function of the SLIC. A
telephone and an AC signal source are the only additional
hardware required to complete the test.
SETUP:
SETUP:
1. Connect the power supplies to the HC5523/15EVAL.
2. Set VBAT to -48V.
3. Connect AGND and BGND to common ground point.
4. Terminate the HC5523 or the HC5515 with 600Ω load
across Tip and Ring.
5. Set the mode switches to E0 = 0, E1 = 1, C1 = 0, C2 = 1.
1. Connect the power supplies to the HC5523/15EVAL.
2. Set VBAT to -28V.
3. Connect AGND and BGND to common ground point.
6. Set the AC source to 1VRMS , 1kHz and apply to the
V-REC input.
7. Connect an AC voltmeter between the V-XMIT and GND.
4. Connect V-REC pin to common ground point.
DISCUSSION:
5. Set the mode switches to E0 = 0, E1 = 1, C1 = 1, C2 = 0.
Transhybrid balance is a measure of how well the input
signal is canceled (that being received by the SLIC) from the
transmit signal (that being transmitted from the SLIC).
Without this function, voice communication would be difficult
because of the echo.
6. Connect the telephone across tip and ring.
7. Connect battery backed AC (20 Hz oscillator) to RINGING
(VBAT + 90VRMS) banana jack.
8. Position DET select switch to the right (for LED).
4-3
Application Note 9632
VERIFICATION:
RING TRIP DETECTOR
1. Measure the AC voltage at V-XMIT output.
R1, R2
Generate a bias voltage from VBAT to drive the RD
pin.
R3, R4, RRT
Combine to sense off-hook condition and drive the
RT pin.
CRT
Provides attenuation of the ring signal for stability
of DT pin.
2. Calculate the Transhybrid balance using Equation 1.
V - XMIT
Transhybrid(dB) = 20 x log ----------------------1V RMS
(EQ. 1)
3. The value should be approximately -40dB.
PULSE METERING OPTION
SETUP:
1. Connect the power supplies to the HC5523/15EVAL.
2. Set VBAT to -48V.
3. Connect AGND and BGND to common ground point.
The component values for the Ring Trip Detector circuit do
not require design equations. For information concerning the
functionality of this supervisory function refer to the
“Supervisory Function” section of the HC5523 or the
HC5515 Data Sheet.
4. Terminate the HC5523 or the HC5515 with 600Ω load
across Tip and Ring.
5. Set the mode switches to E0 = 0, E1 = 1, C1 = 0, C2 = 1.
6. Set the AC source to 1VRMS , 12kHz or 16kHz and apply
to the V-PM input.
7. Connect an AC voltmeter between the V-XMIT and GND.
DISCUSSION:
The pulse metering signal is a 12kHz or 16kHz signal that is
injected on to the tip and ring lines. This signal is monitored
by a counter (non-U.S. markets) inside the pay phone, which
tallies up the cost of the call.
VERIFICATION:
1. Measure the AC voltage at V-XMIT output.
2. Calculate the Transhybrid balance using Equation 1.
LOOP CURRENT DETECTOR
RD
Sets the loop current detect threshold for the
SLIC’s internal comparator function.
The value of RD programs the loop current detect threshold
for the SLIC. Since the internal comparator has hysteresis,
there are two equations that apply to the value of RD. One
equation is for on-hook to off-hook threshold, and the other
is for off-hook to on-hook threshold. The equations for each
condition are as follows:
On-Hook to Off-Hook Threshold
465
R D = -------------------------------------------------------------------------I ON – HOOK to OFF – HOOK
(EQ. 2)
Off-Hook to On-Hook Threshold
3. The value should be approximately -25dB.
Passive Components
375
R D = -------------------------------------------------------------------------I OFF – HOOK to ON – HOOK
The HC5523/15EVAL design incorporates all of the external
components necessary for using the HC5523 or the HC5515
in normal applications. A brief description of each
component is provided below. The components will be
grouped by function to provide further insight to the
operation of the HC5523/15EVAL board.
For details concerning the design equations refer to the
“Supervisory Function” section of the HC5523 or the
HC5515 Data Sheet. As delivered, the HC5523/15EVAL is
configured for a loop current detect level of 11.9mA for onhook to off-hook, and 9.6mA for off-hook to on-hook.
SATURATION GUARD RESISTOR
TWO WIRE SIDE, TIP AND RING
Relay
Allows injection of ringing signal.
PTC
Provides thermal protection for relay to ground
path during extended periods of use. The PTC is
not provided with HC5523/15EVAL board.
RF1, RF2
Feed resistors that limit the current into the tip and
ring inputs of the SLIC.
D1, D4
Provide transient protection on the tip and ring
inputs.
CTC, CRC
Provide immunity against high frequency noise on
tip and ring respectively.
The Two Wire Side components are typical telephone
values. Design equations are not used for these
components.
4-4
(EQ. 3)
RSG
Sets the saturation guard for the SLIC.
When operating in systems with a -28V battery, RSG needs to
be an open circuit. When operating in systems with a -48V
battery, RSG needs to be 4.0kΩ as per the following equation:
5
5 • 10
R SG = ------------------------------------------------------------------ – 17300
V BAT – V MAR – 16.66V
(EQ. 4)
Application Note 9632
For details concerning the design equations refer to the
“Constant Loop Current (DC) Path” section of the HC5523 or
the HC5515 Data Sheet. As delivered, the HC5523/15EVAL
is configured for a saturation guard of 4V on both the tip side
and ring side, resulting in a VMARGIN of 8V for VBAT of -48V.
FOUR WIRE SIDE, SLIC IMPEDANCE MATCHING
RT
V RX
Z B = – R TX • ----------V TX
Performs a voltage to current conversion of the
receive signal. Selected to maintain unity gain
from 4-wire to 2-wire side when SLIC is terminated
with 600Ω.
The values of RT and RRX have been selected for a 600Ω
system. These values can be modified for different
impedances. Also, complex impedance matching is possible
using these components. For information on impedance
matching of the SLIC, refer to the “(AC) 2-Wire Impedance”
section of the HC5523 or the HC5515 Data Sheet.
Where VRX/VTX equals 1/ A4-4 .
ZT
- + 2R F + Z L
Z RX -----------1000
Z B = R TX • ----------- • -------------------------------------------ZT
Z L + 2R F
CDC
(EQ. 8)
Example:
Given: RTX = 20kΩ, ZRX = 280kΩ, ZT = 562kΩ and ZL =
600Ω and RF = 20Ω .
The value of ZB = 18.7kΩ 1%.
RFB
RTX
VTX
CONSTANT FEED CURRENT PROGRAMMING
RDC1, RDC2
(EQ. 7)
Therefore,
Sets the synthesized impedance across the tip
and ring terminals.
RRX
The value of ZB is then
I2
-
+
Sets the constant feed current that flows from tip to
ring when a DC path is present during off-hook
conditions. Resistance is split to allow capacitor for
filtering (CDC).
Filter capacitor to attenuate high frequency noise
that is fed back from tip and ring.
+
VTX
I1
HC5523
-
or
ZT
ZB
HC5515
+
VRX
-
The constant feed current is programmed using the sum of
RDC1 and RDC2. The design equation used to set the loop
current is shown below.
2.5V
I L = -------------------------------------- × 1000
R DC1 + R DC2
RSN
ZRX
CODEC/
FILTER
(EQ. 5)
FIGURE 2. TRANSHYBRID CIRCUIT
For details concerning the design equations for loop current
as well as the selection of CDC refer to the “Constant Loop
Current (DC) Path” section of the HC5523 or the HC5515
Data Sheet. As delivered, the constant feed current is set at
30mA.
TRANSHYBRID BALANCE
U2
Op-amp used for transhybrid balance.
RTX, RB, FB,
RPM
Used as part of transhybrid balance circuitry that is
located off board.
Transhybrid balance is accomplished by using an external
op amp (U2, usually part of the CODEC) and by the
inversion of the signal from the 4-wire receive port (RSN) to
the 4-wire transmit port (VTX). The input signal will be
subtracted from the output signal if I1 equals I2 (Figure 2).
Node analysis yields the following equation:
V TX V RX
----------- + ----------- = 0
R TX Z B
(EQ. 6)
4-5
Application Note 9632
Logic Truth Table
Ringing and Standby. Each state, except Open Circuit, has
options available selecting the supervisory signal that drives
the DET pin. The supervisory signals are Ground Key Detect
(HC5523 only), Loop Current Detect and Ring Trip Detect.
The logic truth tables for the HC5523 and the HC5515 are
shown in Table 2 and Table 3 respectively. The SLIC has four
operating states. The states are Open Circuit, Active,
HC5523/15 SLIC Operating States
TABLE 2. HC5523 LOGIC TRUTH TABLE
E0
E1
C1
C2
0
0
0
0
Open Circuit
SLIC OPERATING STATE
No Active Detector
ACTIVE DETECTOR
Logic Level High
DET OUTPUT
0
0
0
1
Active
Ground Key Detector
Ground Key Status
0
0
1
0
Ringing
No Active Detector
Logic Level High
0
0
1
1
Standby
Ground Key Detector
Ground Key Status
0
1
0
0
Open Circuit
No Active Detector
Logic Level High
0
1
0
1
Active
Loop Current Detector
Loop Current Status
0
1
1
0
Ringing
Ring Trip Detector
Ring Trip Status
0
1
1
1
Standby
Loop Current Detector
Loop Current Status
1
0
0
0
Open Circuit
No Active Detector
1
0
0
1
Active
Ground Key Detector
1
0
1
0
Ringing
No Active Detector
1
0
1
1
Standby
Ground Key Detector
Logic Level High
1
1
0
0
Open Circuit
No Active Detector
1
1
0
1
Active
Loop Current Detector
1
1
1
0
Ringing
Ring Trip Detector
1
1
1
1
Standby
Loop Current Detector
TABLE 3. HC5515 LOGIC TRUTH TABLE
E0
C1
C2
0
0
0
Open Circuit
No Active Detector
Logic Level High
0
0
1
Active
Loop Current Detector
Loop Current Status
0
1
0
Ringing
Ring Trip Detector
Ring Trip Status
0
1
1
Standby
Loop Current Detector
Loop Current Status
1
0
0
Open Circuit
No Active Detector
1
0
1
Active
Loop Current Detector
1
1
0
Ringing
Ring Trip Detector
1
1
1
Standby
Loop Current Detector
4-6
SLIC OPERATING STATE
ACTIVE DETECTOR
DET OUTPUT
Logic Level High
Application Note 9632
RRT
CRT
CHP
R1
RFB
R3
RD
U1
21 HPT
-5V
R2
R4
VBAT
RF1
22 RD
VTX 19
23 DT
VEE 18
25 DR
RSN 16
D2
RF2
D1
CRC
D4
NOTE 1
+5V
5V
RELAY
VBAT
D5
RINGING
(VBAT + 90VRMS)
RSG
V-XMIT
RB
RRX
V-REC
RDC1
RPM1
RPM2
VPM
RDC 14
28 RINGX
RDC2
2 BGND
C1 13
4 VCC
C2 12
CDC
DET
SPST
5 RINGRLY
PTC
RT
6
2
3 +
DET 11
6 VBAT
EO 9
7 RSG
E1 8
LED
510Ω
LED ON
DET LOW
-5V
†
E1
E0
DET
†
†
†
-5V
C2
RING
CTC
D3
-5V
AGND 15
27 TIPX
U2
RTX
C1
TIP
HPR 20
†
LOGIC TERMINAL PORT
SPST
CENTER OFF
NOTE:
1. The anodes of D3 and D4 may be connected directly to the VBAT supply if the application is exposed to only low energy transients. For harsher
environments it is recommended that the anodes of D3 and D4 be shorted to ground through a transzorb or surgector.
FIGURE 3. DEMO BOARD SCHEMATIC
HC5523/15EVAL Evaluation Board Parts List
TABLE 4. EVALUATION BOARD PARTS LIST
COMPONENT
VALUE
TOLERANCE
RATING
COMPONENT
VALUE
TOLERANCE
RATING
U1 - SLIC
HC5523 or HC5515
RPM2
18.7kΩ
1%
1/4W
U2
CA741C Op Amp
RRT
150Ω
5%
2W
RF1, RF2
20Ω
R1, R3
1% match
1/2W
RSG, VBAT = -48V
4.0kΩ
1%
1/4W
200kΩ
5%
1/4W
RDC1, RDC2
41.2kΩF
5%
1/4W
R2
910kΩ
5%
1/4W
CDC
1.5µF
20%
63V, (npo)
R4
1.2MΩ
5%
1/4W
CHP
10nF
20%
100V, (npo)
RB
18.7kΩ
1%
1/4W
CRT
0.39µF
20%
100V, (npo)
RD
39kΩ
5%
1/4W
CTC, CRC
2200pF
20%
100V, (npo)
RFB
20.0kΩ
1%
1/4W
D1 - D4
1N4007 or Equivalent
RRX
280kΩ
1%
1/4W
D5
1N914
N/A
N/A
RT
562kΩ
1%
1/4W
PTC
Shorted
N/A
N/A
RTX
20kΩ
1%
1/4W
KR
2C Contacts, 12V Coil
RLED
510Ω
10%
1/4W
Textool Socket
228-5523
RPM1
280kΩ
1%
1/4W
4-7
100V, 3A
N/A
Application Note 9632
HC5523/15EVAL Evaluation Board Layout
FIGURE 4. SILK SCREEN
FIGURE 5. TOP SIDE
NOTE: Board dimensions not actual size.
4-8
Application Note 9632
HC5523/15EVAL Evaluation Board Layout
(Continued)
FIGURE 6. BOTTOM SIDE
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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4-9
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