DATASHEET

HC5549
®
Data Sheet
October 21, 2004
Low Power SLIC with Battery Switch
Features
The HC5549 Subscriber line
interface circuit is a 100V
diellectrically isolated bipolar
integrated circuit for use in
short loop ISDN, PABX and
Pairgain applications. The HC5549 has been optimized for low
power as required for battery backed remote terminals or for
applications requiring emergency powering from the line such
as European ISDN NT1+ designs.
• Dual Battery Operation
FN4539.3
• Single Additional +5V Supply
• Low Standby Power Consumption (48V, 35mW)
• On Hook Transmission
• Tip and Ring Disconnect
• Soft or Hard Polarity Reversal
• Supports 12kHz or 16kHz Pulse Metering
A high and low voltage battery supply may be connected to
the HC5549 so that power dissipation can be lowered in the
off hook condition in these short loop applications. The high
battery supply can be used in the on-hook condition to allow
interfacing to fax and answering machines that require 48V
to detect end of call status. The HC5549 also has a low
power standby state with very low power consumption
(35mW) resulting in exceptionally low battery drain while
providing continued loop supervision.
• Ring Relay Driver
• On Chip 2-wire AC/DC Loopback
• 0°C to 70°C or -40°C to 85°C Ambient Temp Range
• Low External Component Count
• Pb-Free Available (RoHS Compliant)
Applications
The HC5549 provides loop current, ground key and ring trip
detect functions as well as an alarm output to indicate
thermal overload.
• ISDN NT1+ Terminals
• Pairgain Remote Termination
• PABX and Key Systems
2-wire to 4-wire and 4-wire to 2-wire conversion is provided
and impedance matching is achieved using a single external
network. The HC5549 is compatible with dual and single
supply switched capacitor or DSP codec/filters.
Related Literature
• AC SPICE Macromodel
Block Diagram
POL
ILIM
TIP
RING
SW+
SW-
CDC
VBL
VBH
DC
CONTROL
BATTERY
SWITCH
RINGING
PORT
VRS
2-WIRE
PORT
TRANSMIT
SENSING
4-WIRE
PORT
VRX
VTX
-IN
VFB
TEST
ACCESS
DETECTOR
LOGIC
CONTROL
LOGIC
RTD RD E0 DET ALM
1
BSEL
F2
F1
F0
SWC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2000, 2004. All Rights Reserved
RSLIC18™ is a trademark of Intersil Corporation. All other trademarks mentioned are the property of their respective owners.
HC5549
Ordering Information (PLCC Package Only)
48V
BAT
SW
POL
REV
RING
DELAY
DRIVER
2W
LOOP
BACK
LB = 53dB
TEMP.
RANGE °C
HC5549CM
•
•
•
•
•
•
0 to 70
28 Ld PLCC
HC5549CMZ (Note)
•
•
•
•
•
•
0 to 70
28 Ld PLCC (Pb-free) N28.45
HC5549IM
•
•
•
•
•
•
-40 to 85
PART NUMBER
PACKAGE
28 Ld PLCC
PKG.
DWG. #
N28.45
N28.45
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination
finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020C.
Device Operating Modes
OPERATING MODE
F2
F1
F0
E0 = 1
E0 = 0
DESCRIPTION
Low Power Standby
0
0
0
SHD
GKD
MTU compliant standby mode with active loop
detector.
Forward Active
0
0
1
SHD
GKD
Forward battery loop feed.
Unused
0
1
0
n/a
n/a
Reverse Active
0
1
1
SHD
GKD
Reverse battery loop feed.
Ringing
1
0
0
RTD
RTD
Enabler internal ring trip detector.
Unused
1
0
1
n/a
n/a
Reserved internal test mode.
Unused
1
1
0
n/a
n/a
Reserved internal test mode.
Power Denial
1
1
1
n/a
n/a
Device shutdown.
Reserved internal test mode.
Pinout
2
TIP
2
1
ILIM
BGND
3
RD
VBL
4
RING
VBH
HC5549 (PLCC)
TOP VIEW
28 27 26
SW+
5
25 RTD
SW-
6
24 CDC
SWC
7
23 VCC
F2
8
22 -IN
F1
9
21 VFB
12
13
14 15
16
17
18
AGND
BSEL
NC
POL
VRB
20 VTX
19 VRX
DET
10
11
ALM
F0
E0
FN4539.3
HC5549
Absolute Maximum Ratings TA = 25°C
Thermal Information
Maximum Supply Voltages
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V
VCC - VBAT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80V
Maximum Tip/Ring Negative Voltage Pulse (Note 2) . . . . . . . . -115V
Maximum Tip/Ring Positive Voltage Pulse (Note 2). . . . . . . . . . . .8V
Uncommitted Switch Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . -80V
ESD (Human Body Model). . . . . . . . . . . . . . . . . . . . . . . . . . . . 500V
Thermal Resistance (Typical, Note 1)
Operating Conditions
Die Characteristics
Temperature Range
Industrial (I suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 85°C
Commercial (C suffix). . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 75°C
Positive Power Supply (VCC). . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
Negative Power Supply (VBH, VBL) (180, 181, 182) . . -16V to -80V
Uncommitted Switch (loop back or relay driver) . . . . . . +5V to -80V
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VBAT
Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bipolar-DI
θJA (°C/W)
PLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
53
Maximum Junction Temperature Plastic . . . . . . . . . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
(PLCC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
2. Characterized with 2 x 10µs, and 10 x 1000µs first level lightning surge waveforms (GR-1089-CORE).
3. These parameters are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial
design release and upon design changes which would affect these characteristics.
Electrical Specifications
Unless Otherwise Specified, TA = -40°C to 85°C, VBL = -24V, VBH = -48V, VCC = +5V, AGND = BGND = 0V, loop
current limit = 25mA. All AC Parameters are specified at 600Ω 2-wire terminating impedance over the frequency
band of 300Hz to 3.4kHz. Protection resistors = 0Ω.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
480
-
-
kΩ
160
-
-
kΩ
-
-
1
Ω
RINGING PARAMETERS
VRB Input Impedance (Note 3)
AC TRANSMISSION PARAMETERS (Forward Active and Reverse Active, BSEL = 0, unless otherwise specified.)
Receive Input Impedance (Note 3)
Transmit Output Impedance (Note 3)
4-Wire Port Overload Level
THD = 1%
3.1
3.5
-
VPK
2-Wire Port Overload Level
THD = 1%
3.1
3.5
-
VPK
2-Wire Return Loss
300Hz ≤ f < 1kHz
25
32
-
dB
1kHz ≤ f ≤ 3.4kHz
17
22
-
dB
Longitudinal Current Capability (Per Wire)
Test for False Detect
-
20
-
mARMS
Test for False Detect, Low Power Standby, BSEL =
0
-
10
-
mARMS
2-Wire Longitudinal Balance
Tested per IEEE455-1985, with 368Ω per wire.
53
-
-
dB
4-Wire Longitudinal Balance
Tested per IEEE455-1985, with 368Ω per wire.
59
-
-
dB
4-Wire to 2-Wire Insertion Loss
-0.2
0
+0.3
-
2-Wire to 4-Wire Insertion Loss
-6.22
-6.02
-5.82
-
4-Wire to 4-Wire Insertion Loss
-6.32
-6.02
-5.82
dB
+3 to -40dBm, 1kHz
-
±0.025
-
dB
-40 to -50dBm, 1kHz
-
±0.050
-
dB
-50 to -55dBm, 1kHz
-
±0.100
-
dB
C-Message
-
16
19
dBrnC
Psophometric
-
-74
-71
dBmp
2-Wire to 4-Wire Level Linearity
4-Wire to 2-Wire Level Linearity
Referenced to -10dBm
Idle Channel Noise 2-Wire
3
FN4539.3
HC5549
Electrical Specifications
Unless Otherwise Specified, TA = -40°C to 85°C, VBL = -24V, VBH = -48V, VCC = +5V, AGND = BGND = 0V, loop
current limit = 25mA. All AC Parameters are specified at 600Ω 2-wire terminating impedance over the frequency
band of 300Hz to 3.4kHz. Protection resistors = 0Ω. (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
15
-
45
mA
DC PARAMETERS
Loop Current Limit Programming Range
Max Low Battery = -52V, BSEL = 0
Loop Current Accuracy
IL = 25mA, BSEL = 0
-
-
± 10
%
Loop Current During Low Power Standby
Forward polarity only.
17
-
26
mA
Open Circuit Voltage
(|Tip - Ring|)
BSEL = 0
14
15.5
17
V
BSEL = 1
37.5
40
42.5
V
Low Power Standby Open Circuit Voltage (Tip - Ring)
BSEL = 1
43
45
47
V
-
-
± 10
%
2.3
2.6
2.9
V
Switch Hook Programming Range
5
-
15
mA
Switch Hook Programming Accuracy
-
-
10
%
Dial Pulse Distortion
-
1
-
%
Ring Trip Programming Current Accuracy
Ring Trip Comparator Threshold
Ground Key Threshold
-
12
-
mA
IC junction temperature
-
175
-
°C
IL = 45 mA
-
-
0.60
V
Input Low Voltage
-
-
0.8
V
Input High Voltage
2.0
-
-
V
Thermal Alarm Output
RELAY DRIVER
On Voltage
LOGIC INPUTS (F0, F1, F2, E0, SWC)
Input Low Current
VIL = 0.4V
-20
-
-
µA
Input High Current
VIH = 2.4V
-
-
5
µA
Output Low Voltage
IOL = 5mA
-
-
0.4
V
Output High Voltage
IOH = 100µA
2.4
-
-
V
LOGIC OUTPUTS (DET, ALM)
SUPPLY CURRENTS (Supply currents not listed are considered negligible and do not contribute significantly to total power dissipation. All
measurements made under open circuit load conditions.)
Low Power Standby
ICC
2.0
3.7
6.0
mA
-
0.375
0.600
mA
2.5
4.0
6.0
mA
-
1.0
2.5
mA
3.5
4.5
8.0
mA
IBL , BSEL = 1
-
0.7
2.0
mA
IBH , BSEL = 1
-
1.0
2.5
mA
0.5
3.0
6.0
mA
IBL, BSEL = 1 or 0
-
0.2
0.5
mA
ILL
-
-
10.0
mA
IBL, VBL = -24V
-
-
25.0
mA
IBH , BSEL = 1
Forward or Reverse (Note 5)
ICC
IBL , BSEL = 0
Forward
ICC
Power Denial
ICC
Forward Lookback
4
FN4539.3
HC5549
Electrical Specifications
Unless Otherwise Specified, TA = -40°C to 85°C, VBL = -24V, VBH = -48V, VCC = +5V, AGND = BGND = 0V, loop
current limit = 25mA. All AC Parameters are specified at 600Ω 2-wire terminating impedance over the frequency
band of 300Hz to 3.4kHz. Protection resistors = 0Ω. (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ON HOOK POWER DISSIPATION
Forward or Reverse
BSEL = 0
-
44
60
mW
Forward or Reverse
BSEL = 1
-
90
150
mW
Low Power Standby
BSEL = 1
-
37
60
mW
BSEL = 0
-
290
310
mW
f = 300Hz
-
40
-
dB
f = 1kHz
-
35
-
dB
f = 3.4kHz
-
28
-
dB
f = 300Hz
-
45
-
dB
f = 1kHz
-
43
-
dB
OFF HOOK POWER DISSIPATION
Forward or Reverse
POWER SUPPLY REJECTION RATIO
VCC to 2-Wire
VCC to 4-Wire
f = 3.4kHz
-
33
-
dB
VBL to 2-Wire
300Hz ≤ f ≤ 3.4kHz
-
30
-
dB
VBL to 4-Wire
300Hz ≤ f ≤ 3.4kHz
-
35
-
dB
VBH to 2-Wire
300Hz ≤ f ≤ 3.4kHz
-
33
-
dB
VBH to 4-Wire
300Hz ≤ f ≤ 1kHz
-
40
-
dB
1kHz < f ≤ 3.4kHz
-
45
-
dB
Design Equations
Loop Current Limit
SWITCH HOOK DETECT
The loop current limit of the device is programmed by the
external resistor RIL. The value of RIL can be calculated
using Equation 3.
The switch hook detect threshold is set by a single external
resistor, RSH . Equation 1 is used to calculate the value of RSH.
1760
R IL = ------------I LIM
Loop Supervision Thresholds
(EQ. 1)
R SH = 600 ⁄ I SH
The term ISH is the desired DC loop current threshold. The
loop current threshold programming range is from 5mA to
15mA.
GROUND KEY DETECT
The ground key detector senses a DC current imbalance
between the Tip and Ring terminals when the ring terminal is
connected to ground. The ground key detect threshold is not
externally programmable and is internally fixed to 12mA
regardless of the switch hook threshold.
RING TRIP DETECT
The ring trip detect threshold is set by a single external
resistor, RRT. IRT should be set between the peak ringing
current and the peak off hook current while still ringing.
(EQ. 3)
The term ILIM is the desired loop current limit. The loop
current limit programming range is from 15mA to 45mA.
Impedance Matching
The impedance of the device is programmed with the
external component RS . RS is the gain setting resistor for
the feedback amplifier that provides impedance matching. If
complex impedance matching is required, then a complex
network can be substituted for RS .
RESISTIVE IMPEDANCE SYNTHESIS
The source impedance of the device, ZO , can be calculated
in Equation 4.
R S = 400 ( ZO )
(EQ. 4)
The required impedance is defined by the terminating
impedance and protection resistors as shown in Equation 5.
(EQ. 2)
R RT = 1800 ⁄ I RT
The capacitor CRT, in parallel with RRT, will set the ring trip
response time.
5
Z O = Z L – 2R P
(EQ. 5)
FN4539.3
HC5549
Low Power Standby
4-WIRE TO 2-WIRE GAIN
The 4-wire to 2-wire gain is defined as the receive gain. It is
a function of the terminating impedance, synthesized
impedance and protection resistors. Equation 6 calculates
the receive gain, G42.
ZL


G 42 = – 2  ------------------------------------------
Z
+
2R
 O
P + Z L
(EQ. 6)
When the device source impedance and protection resistors
equals the terminating impedance, the receive gain equals
unity.
2-WIRE TO 4-WIRE GAIN
Overview
The low power standby mode (LPS, 000) should be used
during idle line conditions. The device is designed to operate
from the high battery during this mode. Most of the internal
circuitry is powered down, resulting in low power dissipation.
If the 2-wire (tip/ring) DC voltage requirements are not
critical during idle line conditions, the device may be
operated from the low battery. Operation from the low battery
will decrease the standby power dissipation.
TABLE 1. DEVICE INTERFACES DURING LPS
INTERFACE
The 2-wire to 4-wire gain (G24) is the gain from tip and ring to
the VTX output. The transmit gain is calculated in Equation 7.
ZO


G 24 = –  ------------------------------------------
 Z O + 2RP + Z L
(EQ. 7)
ON
OFF
NOTES
Receive
x
Ringing
x
AC transmission, impedance
matching and ringing are
disabled during this mode.
Transmit
x
2-Wire
x
Amplifiers disabled.
When the protection resistors are set to zero, the transmit
gain is -6dB.
Loop Detect
x
Switch hook or ground key.
TRANSHYBRID GAIN
2-WIRE INTERFACE
The transhybrid gain is defined as the 4-wire to 4-wire gain
(G44).
During LPS, the 2-wire interface is maintained with internal
switches and voltage references. The Tip and Ring
amplifiers are turned off to conserve power. The device will
provide MTU compliance, loop current and loop supervision.
Figure 2 represents the internal circuitry providing the 2-wire
interface during low power standby.
ZO


G 44 = –  ---------------------------------------
 Z O + 2R P + Z L
(EQ. 8)
When the protection resistors are set to zero, the transhybrid
gain is -6dB.
GND
COMPLEX IMPEDANCE SYNTHESIS
Substituting the impedance programming resistor, RS, with a
complex programming network provides complex
impedance synthesis.
2-WIRE
NETWORK
C2
PROGRAMMING
NETWORK
CP
R1
600Ω
TIP AMP
TIP
RING
RING AMP
RS
R2
600Ω
RP
MTU REF
FIGURE 1. COMPLEX PROGRAMMING NETWORK
The reference designators in the programming network
match the evaluation board. The component RS has a
different design equation than the RS used for resistive
impedance synthesis. The design equations for each
component are provided below.
(EQ. 9)
R S = 400 × ( R 1 – 2 ( R P ) )
R P = 400 × R 2
(EQ. 10)
C P = C 2 ⁄ 400
(EQ. 11)
6
FIGURE 2. LPS 2-WIRE INTERFACE CIRCUIT DIAGRAM
MTU Compliance
Maintenance Termination Unit or MTU compliance places
DC voltage requirements on the 2-wire terminals during idle
line conditions. The minimum idle voltage is 42.75V. The
high side of the MTU range is 56V. The voltage is expressed
as the difference between Tip and Ring.
The Tip voltage is held near ground through a 600Ω resistor
and switch. The Ring voltage is limited to a maximum of
-49V (by MTU REF) when operating from either the high or
low battery. A switch and 600Ω resistor connect the MTU
reference to the Ring terminal. When the high battery
FN4539.3
HC5549
voltage exceeds the MTU reference of -49V (typically), the
Ring terminal will be clamped by the internal reference. The
same Ring relationships apply when operating from the low
battery voltage. For high battery voltages (VBH) less than or
equal to the internal MTU reference threshold:
(EQ. 12)
V RING = V BH + 4
Loop Current
During LPS, the device will provide current to a load. The
current path is through resistors and switches, and will be
function of the off hook loop resistance (RLOOP). This
includes the off hook phone resistance and copper loop
resistance. The current available during LPS is determined
by Equation 13.
I LOOP = ( – 1 – ( – 49 ) ) ⁄ ( 600 + 600 + R LOOP )
(EQ. 13)
Internal current limiting of the standby switches will limit the
maximum current to 20mA.
Another loop current related parameter is longitudinal
current capability. The longitudinal current capability is
reduced to 10mARMS per pin. The reduction in longitudinal
current capability is a result of turning off the Tip and Ring
amplifiers.
The on hook power dissipation of the device during LPS is
determined by the operating voltages and quiescent currents
and is calculated using Equation 14.
(EQ. 14)
On-Hook Transmission
The primary purpose of on hook transmission will be to
support caller ID and other advanced signalling features.
The transmission over load level while on hook is 3.5VPEAK .
When operating from the high battery, the DC voltages at Tip
and Ring are MTU compliant. The typical Tip voltage is -4V
and the Ring voltage is a function of the battery voltage for
battery voltages less than -60V as shown in Equation 17.
(EQ. 17)
V RING = V BH + 4
Loop supervision is provided by the switch hook detector at
the DET output. When DET goes low, the low battery should
be selected for DC loop feed and voice transmission.
The design implements a voltage feed current sense
architecture. The device controls the voltage across Tip and
Ring based on the sensing of load current. Resistors are
placed in series with Tip and Ring outputs to provide the
current sensing. The diagram below illustrates the concept.
RA
VIN
RCS
-
VOUT
+
RL
RC
-
+
KS
Standby Current Power dissipation
Any standby line current, ISLC , introduces an additional
power dissipation term PSLC . Equation 15 illustrates the
power contribution is zero when the standby line current is
zero.
(EQ. 15)
If the battery voltage is less than -49V (the MTU clamp is
off), the standby line current power contribution reduces to
Equation 16.
P SLC = I SLC × ( V BH + 1 + I SLC x1200 )
The forward active mode (FA, 001) is the primary AC
transmission mode of the device. On hook transmission, DC
loop feed and voice transmission are supported during forward
active. Loop supervision is provided by either the switch hook
detector (E0 = 1) or the ground key detector (E0 = 0). The
device may be operated from either high or low battery for onhook transmission and low battery for loop feed.
RB
The quiescent current terms are specified in the electrical
tables for each operating mode. Load power dissipation is
not a factor since this is an on hook mode. Some
applications may specify a standby current. The standby
current may be a charging current required for modern
telephone electronics.
P SLC = I SLC × ( V BH – 49 + 1 + I SLC x1200 )
Overview
Feed Architecture
On Hook Power Dissipation
P LPS = V BH × I BHQ + V BL × I BLQ + V CC × I CCQ
Forward Active
FIGURE 3. VOLTAGE FEED CURRENT SENSE DIAGRAM
By monitoring the current at the amplifier output, a negative
feedback mechanism sets the output voltage for a defined
load. The amplifier gains are set by resistor ratios (RA , RB ,
RC) providing all the performance benefits of matched
resistors. The internal sense resistor, RCS , is much smaller
than the gain resistors and is typically 20Ω for this device.
The feedback mechanism, KS , represents the amplifier
configuration providing the negative feedback.
(EQ. 16)
Most applications do not specify charging current
requirements during standby. When specified, the typical
charging current may be as high as 5mA.
7
FN4539.3
HC5549
DC Loop Feed
The feedback mechanism for monitoring the DC portion of
the loop current is the loop detector. A low pass filter is used
in the feedback to block voice band signals from interfering
with the loop current limit function. The pole of the low pass
filter is set by the external capacitor CDC . The value of the
external capacitor should be 4.7µF.
Most applications will operate the device from low battery
while off hook. The DC feed characteristic of the device will
drive Tip and Ring towards half battery to regulate the DC
loop current. For light loads, Tip will be near -4V and Ring
will be near VVBL + 4V. The following diagram shows the DC
feed characteristic.
VTR(OC)
VTR , DC (V)
m = (∆VTR/∆IL) = 10kΩ
The maximum loop impedance for a programmed loop
current is defined as RKNEE .
V TR ( OC )
R KNEE = ----------------------I LIM
(EQ. 21)
When RKNEE is exceeded, the device will transition from
constant current feed to constant voltage, resistive feed. The
line segment IB represents the resistive feed portion of the
load characteristic.
V TR ( OC )
I B = ----------------------R LOOP
(EQ. 22)
Voice Transmission
The feedback mechanism for monitoring the AC portion of
the loop current consists of two amplifiers, the sense
amplifier (SA) and the transmit amplifier (TA). The AC
feedback signal is used for impedance synthesis. A detailed
model of the AC feed back loop is provided below.
R
R
VRX
ILIM
ILOOP (mA)
20
TIP
FIGURE 4. DC FEED CHARACTERISTIC
RING
20
IA
ISC
ILOOP (mA)
2RP
RLOOP (Ω)
The slope of the feed characteristic and the battery voltage
define the maximum loop current on the shortest possible
loop as the short circuit current ISC.
(EQ. 19)
The term ILIM is the programmed current limit, 1760/RIL. The
line segment IA represents the constant current region of the
loop current limit function.
V TR ( OC ) – R LOOP I LIM
I A = I LIM + -------------------------------------------------------------10e3
8
R
3R
-IN
0.75R
3R
3R
3R
+
R/2
CFB
8K
-
VFB
VSA
FIGURE 6. AC SIGNAL TRANSMISSION MODEL
The sense amp output voltage, VSA , as a function of Tip and
Ring voltage and load is calculated using Equation 23.
RKNEE
FIGURE 5. ILOOP VERSUS RLOOP LOAD CHARACTERISTIC
V TR ( OC ) – 2R P I LIM
I SC = I LIM + ----------------------------------------------------10e3
RS
The gain of the transmit amplifier, set by RS , determines the
programmed impedance of the device. The capacitor CFB
blocks the DC component of the loop current. The ground
symbols in the model represent AC grounds, not actual DC
potentials.
IB
ILIM
TA
-
The curve of Figure 5 determines the actual loop current for
a given set of loop conditions. The loop conditions are
determined by the low battery voltage and the DC loop
impedance. The DC loop impedance is the sum of the
protection resistance, copper resistance (ohms/foot) and the
telephone off hook DC resistance.
VTX
+
-
(EQ. 18)
V TR ( OC ) = V BL – 8
R
1:1
+
The point on the y-axis labeled VTR(OC) is the open circuit
Tip to Ring voltage and is defined by the feed battery
voltage.
-
+
(EQ. 20)
10
V SA = – ( V T – V R ) -----ZL
(EQ. 23)
The transmit amplifier provides the programmable gain
required for impedance synthesis. In addition, the output of
this amplifier interfaces to the CODEC transmit input. The
output voltage is calculated using Equation 24.
RS
V VTX = – V SA  ----------
 8e3
(EQ. 24)
Once the impedance matching components have been
selected using the design equations, the above equations
provide additional insight as to the expected AC node
voltages for a specific Tip and Ring load.
FN4539.3
HC5549
Transhybrid Balance
The final step in completing the impedance synthesis design
is calculating the necessary gains for transhybrid balance.
The AC feed back loop produces an echo at the VTX output
of the signal injected at VRX . The echo must be cancelled to
maintain voice quality. Most applications will use a summing
amplifier in the CODEC front end as shown below to cancel
the echo signal.
R
RA
VRX
R
1:1
RB
VTX
TA
RX OUT
RF
-
TX IN
-
+
+2.4V
-IN
CODEC
HC5518x
FIGURE 7. TRANSHYBRID BALANCE INTERFACE
The resistor ratio, RF /RB , provides the final adjustment for
the transmit gain, GTX . The transmit gain is calculated using
Equation 25.
 R F
G TX = – G 24  --------
 R B
(EQ. 29)
P FA ( IB ) = P FA ( Q ) + ( V BL xI B ) – ( R LOOP xI 2 B )
Since the current relationships are different for constant
current versus constant voltage, the region of device
operation is critical to valid power dissipation calculations.
Reverse Active
Overview
+
RS
If the loop length is greater than RKNEE , the device is operating
in the constant voltage, resistive feed region. The power
dissipated in this region is calculated using Equation 29.
(EQ. 25)
Most applications set RF = RB , hence the device 2-wire to
4-wire equals the transmit gain. Typically RB is greater than
20kΩ to prevent loading of the device transmit output.
The reverse active mode (RA, 011) provides the same
functionality as the forward active mode. On hook
transmission, DC loop feed and voice transmission are
supported. Loop supervision is provided by either the switch
hook detector (E0 = 1) or the ground key detector (E0 = 0).
The device may be operated from either high or low battery.
During reverse active the Tip and Ring DC voltage
characteristics exchange roles. That is, Ring is typically 4V
below ground and Tip is typically 4V more positive than
battery. Otherwise, all feed and voice transmission
characteristics are identical to forward active.
Silent Polarity Reversal
Changing from forward active to reverse active or vice versa
is referred to as polarity reversal. Many applications require
slew rate control of the polarity reversal event. Requirements
range from minimizing cross talk to protocol signalling.
The resistor ratio, RF /RA , is determined by the transhybrid
gain of the device, G44 . RF is previously defined by the
transmit gain requirement and RA is calculated using
Equation 26.
The device uses an external low voltage capacitor, CPOL , to
set the reversal time. Once programmed, the reversal time
will remain nearly constant over various load conditions. In
addition, the reversal timing capacitor is isolated from the AC
loop, therefore loop stability is not impacted.
RB
R A = --------G 44
The internal circuitry used to set the polarity reversal time is
shown below.
(EQ. 26)
Power Dissipation
I1
The power dissipated by the device during on hook
transmission is strictly a function of the quiescent currents
for each supply voltage during Forward Active operation.
+ V BL × I BLQ + V CC × I CCQ
P FAQ = V BH × I
BHQ
(EQ. 27)
Off hook power dissipation is increased above the quiescent
power dissipation by the DC load. If the loop length is less
than or equal to RKNEE , the device is providing constant
current, IA , and the power dissipation is calculated using
Equation 28.
P FA ( IA ) = P FA ( Q ) + ( V BL xI A ) – ( R LOOP xI 2 A )
9
(EQ. 28)
POL
75kΩ
CPOL
I2
FIGURE 8. REVERSAL TIMING CONTROL
During forward active, the current from source I1 charges
the external timing capacitor CPOL and the switch is open.
The internal resistor provides a clamping function for
voltages on the POL node. During reverse active, the switch
closes and I2 (roughly twice I1) pulls current from I1 and the
timing capacitor. The current at the POL node provides the
FN4539.3
HC5549
drive to a differential pair which controls the reversal time of
the Tip and Ring DC voltages.
∆time
C POL = ---------------75000
(EQ. 30)
Where ∆time is the required reversal time. Polarized
capacitors may be used for CPOL . The low voltage at the
POL pin and minimal voltage excursion ±0.75V, are well
suited to polarized capacitors.
Power Dissipation
The power dissipation equations for forward active operation
also apply to the reverse active mode.
Ringing
Overview
The ringing mode (RNG, 100) provides the low side return
path for externally supplied battery backed ringing. The
ringing signal must be injected through a relay at the ring
terminal. The device should be operated from the low battery
voltage during this mode to minimize the overall power
dissipation during ringing. Current flowing through the Tip
terminal will provide the necessary ring trip information.
Ringing Bias Input
The ringing bias input, VRB, is a high impedance input. The
VRB input is only selected during the ringing mode. The gain
from the VRB input to the Tip output is typically 40V/V. The
following equation shows the relationship of the Tip output
voltage to the VRB input voltage.
VBL
V TIP = ------------ + 40 × VRB
2
(EQ. 31)
A positive DC voltage at VRB is required to shift the Tip
output voltage towards ground to provide the low side ringing
return path. Tying the logic input F2 to VRB provides the
positive voltage to offset Tip during ringing. A voltage divider
is suggested to provide control the actual voltage applied to VRB.
Logic Control
Ringing patterns consist of silent intervals. The ringing to
silent pattern is called the ringing cadence. During the silent
portion of ringing, the device can be programmed to any
other operating mode. The most likely candidates are low
power standby or forward active. Depending on system
requirements, the low or high battery may be selected.
Loop supervision is provided with the ring trip detector. The
ring trip detector senses the change in loop current when the
phone is taken off hook. The loop detector full wave rectifies
the ringing current, which is then filtered with external
components RRT and CRT. The resistor RRT sets the trip
threshold and the capacitor CRT sets the trip response time.
Most applications will require a trip response time less than
150 milliseconds.
Three very distinct actions occur when the devices detects a
ring trip. First, the DET output is latched low. The latching
10
mechanism eliminates the need for software filtering of the
detector output. The latch is cleared when the operating
mode is changed externally. Second, the VRS input is
disabled, removing the Tip biasing signal from the line. Third,
the device is internally forced to the forward active mode.
Power Dissipation
The power dissipation during ringing is dictated by the load
driving requirements and the ringing waveform. The key to
valid power calculations is the correct definition of average
and rms currents. The average current defines the high
battery supply current. The rms current defines the load
current.
The cadence provides a time averaging reduction in the
peak power. The total power dissipation consists of ringing
power, Pr, and the silent interval power, Ps.
tr
ts
P RNG = P r ⋅ -------------- + P s ⋅ -------------tr + ts
tr + ts
(EQ. 32)
The terms, tr and ts, represent the cadence. The ringing
interval is tr and the silent interval is ts. The typical cadence
ratio tr:ts is 1:2.
The quiescent power of the device in the ringing mode is
defined in Equation 34.
P r ( Q ) = VBH ⋅ IBH Q + VBL ⋅ IBL Q + VCC ⋅ ICC Q
(EQ. 33)
During ringing, the device is operated from the low battery,
therefore the VBH power contribution is negligible. The total
power during the ringing interval is the sum of the quiescent
power and loading power:
2
V rms
P r = P r ( Q ) + VBL ⋅ I AVG – ----------------------------------------Z
+R
REN
(EQ. 34)
LOOP
For sinusoidal waveforms, the average current, IAVG, is
defined in equation 36.
V rms ⋅ 2
2
I AVG =  --- ----------------------------------------- π Z
+R
REN
(EQ. 35)
LOOP
The only amplifier providing load current during ringing is the
Tip amplifier. Therefore the total power contribution from the
device is half the average power required by the load.
V rms ⋅ 2
1
I AVG =  --- ----------------------------------------- π Z
+R
REN
(EQ. 36)
LOOP
The silent interval power dissipation will be determined by
the quiescent power of the selected operating mode.
Power Denial
Overview
The power denial mode (111) will shutdown the entire device
except for the logic interface. Loop supervision is not
provided. This mode may be used as a sleep mode or to
FN4539.3
HC5549
shutdown in the presence of a persistent thermal alarm.
Switching between high and low battery will have no effect
during power denial.
Uncommitted Switch
Functionality
The uncommitted switch is a three terminal device designed
for flexibility. The independent logic control input, SWC,
allows switch operation regardless of device operating
mode. The switch is activated by a logic low. The positive
and negative terminals of the device are labeled SW+ and
SW- respectively.
During power denial, both the Tip and Ring amplifiers are
disabled, representing high impedances. The voltages at
both outputs are near ground.
Thermal Shutdown
In the event the safe die temperature is exceeded, the ALM
output will go low and DET will go high and the part will
automatically shut down. When the device cools, ALM will
go high and DET will reflect the loop status. If the thermal
fault persists, ALM will go low again and the part will
shutdown. Programming power denial will permanently
shutdown the device and stop the self cooling cycling.
Overview
Relay Driver
The uncommitted switch may be used as a relay driver by
connecting SW+ to the relay coil and SW- to ground. The
switch is designed to have a maximum on voltage of 0.6V
with a load current of 45mA.
+5V
RELAY
Battery Switching
Overview
SW+
The integrated battery switch selects between the high
battery (VBH) and low battery (VBL). The battery switch is
controlled with the logic input BSEL. When BSEL is a logic
high, the high battery is selected and when a logic low, the
low battery is selected. All operating modes of the device will
operate from high or low battery except forward loop back.
Functionality
The logic control is independent of the operating mode
decode. Independent logic control provides the most
flexibility and will support all application configurations.
When changing device operating states, battery switching
should occur simultaneously with or prior to changing the
operating mode. In most cases, this will minimize overall
power dissipation and prevent glitches on the DET output.
The only external component required to support the battery
switch is a diode in series with the VBH supply lead. In the
event that high battery is removed, the diode allows the
device to transition to low battery operation.
SWC
SW-
FIGURE 9. EXTERNAL RELAY SWITCHING
Since the device provides the ringing waveform, the relay
functions which may be supported include subscriber
disconnect, test access or line interface bypass. An external
snubber diode is not required when using the uncommitted
switch as a relay driver.
Test Load
The switch may be used to connect test loads across Tip
and Ring. The test loads can provide external test
termination for the device. Proper connection of the
uncommitted switch to Tip and Ring is shown below.
TIP
RING
Low Battery Operation
All off hook operating conditions and ringing should use the
low battery. The prime benefit will be reduced power
dissipation. The typical low battery for the device is -24V.
However this may be increased to support longer loop
lengths or high loop current requirements. Standby
conditions may also operate from the low battery if MTU
compliance is not required, further reducing standby power
dissipation.
High Battery Operation
The high battery should be used for standby conditions
which must provide MTU compliance. During standby
operation the power consumption is typically 40 mW with 48V battery. If standby requirements do not require high
battery operation, then a lower battery will result in lower
standby power.
11
TEST
LOAD
SW+
SW-
SWC
FIGURE 10. TEST LOAD SWITCHING
The diode in series with the test load blocks current from
flowing through the uncommitted switch when the polarity of
the Tip and Ring terminals are reversed. In addition to the
reverse active state, the polarity of Tip and Ring are
reversed for half of the ringing cycle. With independent logic
control and the blocking diode, the uncommitted switch may
be continuously connected to the Tip and Ring terminals.
FN4539.3
HC5549
Basic Application Circuit
CPS1
CPS2
D1
CPS3
VCC
RP1
VBL
VBH
CRX
TIP
VRX
U1
PROTECTION
NETWORK
VRB
HC5549
RP2
CTX
RING
-48V
RRT
RSH
RIL
RS
-IN
SW-
CFB
VFB
RTD
SWC
RD
BSEL
E0
ILIM
F0
F1
CDC
VCC
CDC
CPOL
RB2
VTX
SW+
CRT
RB1
F2
DET
POL
ALM
CIL
AGND
BGND
FIGURE 11. HC5549 BASIC APPLICATION CIRCUIT
Basic Application Circuit Component List
COMPONENT
VALUE
TOLERANCE
RATING
U1
HC5549
N/A
N/A
RRT
20kΩ
1%
RSH
49.9kΩ
RIL
COMPONENT
VALUE
TOLERANCE
RATING
n/a
n/a
n/a
n/a
0.1W
CDC
4.7µF
20%
10V
1%
0.1W
CPS1
0.1µF
20%
>100V
71.5kΩ
1%
0.1W
CPS2, CPS3
0.1µF
20%
100V
RS
210kΩ
1%
0.1W
D1
1N400X type with breakdown > 100V.
CRX, CRS, CTX, CRT,
CPOL, CFB
0.47µF
20%
10V
RP1, RP2
Protection resistor values are application
dependent and will be determined by protection
requirements. Standard applications will use ≥
35Ω per side.
Design Parameters: Ring Trip Threshold = 90 mA peak., Switch Hook Threshold = 12 mA, Loop Current Limit = 24.6 mA, Synthesize Device
Impedance = 210kΩ/400= 525Ω, with 39Ω protection resistors, impedance across Tip and Ring terminals = 603Ω.
12
FN4539.3
HC5549
Pin Description
PLCC
SYMBOL
1
TIP
2
BGND
3
VBL
DESCRIPTION
TIP power amplifier output.
Battery Ground - To be connected to zero potential. All loop current and longitudinal current flow from this ground.
Internally separate from AGND but it is recommended that it is connected to the same potential as AGND.
Low battery supply connection.
4
VBH
High battery supply connection.
5
SW+
Uncommitted switch positive terminal.
6
SW-
Uncommitted switch negative terminal.
7
SWC
Switch control input. This TTL compatible input controls the uncommitted switch, with a logic “0” enabling the switch and
logic “1” disabling the switch.
8
F2
Mode control input - MSB. F2-F0 for the TTL compatible parallel control interface for controlling the various modes of
operation of the device.
9
F1
Mode control input.
10
F0
Mode control input.
11
E0
Detector Output Selection Input. This TTL input controls the multiplexing of the SHD (E0=1) and GKD (E0 =0) comparator
outputs to the DET output based upon the state at the F2-F0 pins.
12
DET
Detector Output - This TTL output provides hook status of the loop based upon the selected operating mode. The
detected output will either be switch hook, ground key or ring trip.
13
ALM
Thermal Shutdown Alarm. This pin signals the internal die temperature has exceeded safe operating temperature and
the device has been powered down automatically.
14
AGND
Analog ground reference. This pin should be externally connected to BGND.
15
BSEL
Selects between high and low battery, with a logic “1” selecting the high battery and logic “0” the low battery.
16
NC
This pin is a “no connect” and should remain floating proper device operation.
17
POL
Capacitor connected to this pin sets the polarity reversal slew rate.
18
VRB
Ringing Bias Input - Analog input to offset Tip output towards ground while in Ringing Mode.
19
VRX
Analog Receive Voltage - 4-wire analog audio input voltage. AC couples to codec.
20
VTX
Transmit output voltage - Output of impedance matching amplifier, AC couples to codec.
21
VFB
Feedback voltage for impedance matching. This voltage is scaled to accomplish impedance matching.
22
-IN
23
VCC
Positive voltage power supply.
24
CDC
DC Biasing Filter Capacitor - Connects between this pin and VCC.
25
RTD
Ring trip filter network.
26
ILIM
Loop Current Limit programming resistor.
27
RD
Switch hook detection threshold programming resistor.
28
RING
Impedance matching amplifier summing node.
RING power amplifier output.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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13
FN4539.3
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