DATASHEET

EL1509
®
Data Sheet
March 26, 2007
FN7015.2
Medium Power Differential Line Driver
Features
The EL1509 is a dual operational amplifier designed for
customer premise line driving in DMT ADSL solutions. This
device features a high drive capability of 250mA while
consuming only 7.1mA of supply current per amplifier and
operating from a single 5V to 12V supply. This driver
achieves a typical distortion of less than -85dBc, at 150kHz
into a 25Ω load. The EL1509 is available in the industry
standard 8 Ld SOIC as well as the thermally-enhanced 8 Ld
DFN package. Both are specified for operation over the full
-40°C to +85°C temperature range.
• Drives up to 250mA from a +12V supply
The EL1509 is ideal for ADSL, SDSL, HDSL2 and VDSL line
driving applications.
PART NUMBER
• -85dBc typical driver output distortion at full output at
150kHz
• Low quiescent current of 7.5mA per amplifier
• Pb-free plus anneal available (RoHS compliant)
Applications
• ADSL G.lite CO line driving
• ADSL full rate CPE line driving
• G.SHDSL, HDSL2 line driver
Ordering Information
PART
MARKING
• 20VP-P differential output drive into 100Ω
TAPE &
REEL PACKAGE
PKG.
DWG. #
EL1509CS
1509CS
-
8 Ld SOIC
MDP0027
EL1509CS-T7
1509CS
7”
8 Ld SOIC
MDP0027
EL1509CS-T13
1509CS
13"
8 Ld SOIC
MDP0027
EL1509CSZ
(See Note)
1509CSZ
-
8 Ld SOIC
(Pb-Free)
MDP0027
EL1509CSZ-T7
(See Note)
1509CSZ
7”
8 Ld SOIC
(Pb-Free)
MDP0027
EL1509CSZ-T13 1509CSZ
(See Note)
13"
• Video distribution amplifier
• Video twisted-pair line driver
Pinouts
EL1509
(8 LD SOIC)
TOP VIEW
OUTA 1
8 VS
-
INA- 2
8 Ld SOIC
(Pb-Free)
MDP0027
7 OUTB
+
INA+ 3
6 INB-
EL1509CL
1509CL
-
8 Ld DFN
MDP0047
EL1509CL-T7
1509CL
7"
8 Ld DFN
MDP0047
EL1509CL-T13
1509CL
13"
8 Ld DFN
MDP0047
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
GND
+
4
5 INB+
EL1509
(8 LD DFN)
TOP VIEW
OUTA
1
INA-
2
INA+
3
GND
4
8 VS
7 OUTB
+
1
AMP A
+
AMP B
6 INB5 INB+
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002-2004, 2007. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
EL1509
Absolute Maximum Ratings (TA = +25°C)
VS+ Voltage to Ground . . . . . . . . . . . . . . . . . . . . . . -0.3V to +14.6V
VIN+ Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND to VS+
Current into any Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8mA
Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 75mA
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . . . . . .-60°C to +150°C
Operating Junction Temperature . . . . . . . . . . . . . . .-40°C to +150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
VS = +12V, RF = 1.5kΩ, RL = 100Ω connected to mid supply, TA = 25°C, unless otherwise specified.
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
BW
-3dB Bandwidth
AV = +4
70
MHz
HD
Total Harmonic Distortion
f = 150kHz, VO = 16VP-P, RL = 25Ω
-85
dBc
dG
Differential Gain
AV = +2, RL = 37.5Ω
0.15
%
dθ
Differential Phase
AV = +2, RL = 37.5Ω
0.1
°
SR
Slewrate
VOUT from -3V to +3V
500
V/µs
350
DC PERFORMANCE
VOS
Offset Voltage
-20
20
mV
ΔVOS
VOS Mismatch
-10
10
mV
ROL
Transimpedance
2.5
MΩ
VOUT from -4.5V to +4.5V
0.7
1.4
INPUT CHARACTERISTICS
IB+
Non-Inverting Input Bias Current
-5
5
µA
IB-
Inverting Input Bias Current
-30
30
µA
ΔIB-
IB- Mismatch
-30
30
µA
eN
Input Noise Voltage
2.8
nV/√ Hz
iN
-Input Noise Current
19
pA/√ Hz
OUTPUT CHARACTERISTICS
VOUT
IOUT
Loaded Output Swing (single ended)
VS = ±6V, RL = 100Ω to GND
±4.8
±5
V
VS = ±6V, RL = 25Ω to GND
±4.4
±4.7
V
450
mA
Output Current
RL = 0Ω
VS
Supply Voltage
Single Supply
IS
Supply Current
All Outputs at Mid Supply
SUPPLY
2
5
14.2
12
V
18
mA
FN7015.2
March 26, 2007
EL1509
Typical Performance Curves
28
20
16
24
RF=1kΩ
RF=1.5kΩ
RF=2kΩ
AV=10
VS=±6V
RL=100Ω
RF=1.5kΩ
GAIN (dB)
GAIN (dB)
24
28
AV=10
VS=±6V
RL=100Ω
16
RF=2kΩ
12
12
8
100K
1M
10M
8
100K
100M
FREQUENCY (Hz)
RF=1kΩ
18
14
RF=2kΩ
10
AV=5
VS=±6V
RL=100Ω
RF=1.5kΩ
RF=1.5kΩ
GAIN (dB)
GAIN (dB)
100M
22
AV=5
VS=±6V
RL=100Ω
6
RF=1kΩ
14
10
RF=2kΩ
6
2
100K
1M
10M
2
100K
100M
FREQUENCY (Hz)
1M
10M
100M
FREQUENCY (Hz)
FIGURE 3. DIFFERENTIAL FREQUENCY RESPONSE vs RF
(EL1509CS)
FIGURE 4. DIFFERENTIAL FREQUENCY RESPONSE vs RF
(EL1509CL)
22
22
AV=5
VS=±6V
RL=100Ω
RF=1.5kΩ
CL=22pF
CL=10pF
14
CL=0pF
10
6
2
100K
18
GAIN (dB)
GAIN (dB)
10M
FIGURE 2. DIFFERENTIAL FREQUENCY RESPONSE vs RF
(EL1509CL)
22
18
1M
FREQUENCY (Hz)
FIGURE 1. DIFFERENTIAL FREQUENCY RESPONSE vs RF
(EL1509CS)
18
RF=1kΩ
20
AV=5
VS=±6V
RL=100Ω
RF=1.5kΩ
CL=22pF
CL=10pF
14
CL=0pF
10
6
1M
10M
100M
FREQUENCY (Hz)
FIGURE 5. DIFFERENTIAL FREQUENCY RESPONSE vs CL
(EL1509CS)
3
2
100K
1M
10M
100M
FREQUENCY (Hz)
FIGURE 6. DIFFERENTIAL FREQUENCY RESPONSE vs CL
(EL1509CL)
FN7015.2
March 26, 2007
EL1509
Typical Performance Curves
55
-45
AV=5
RF=1.5kΩ
RL=100Ω
53
51
-55
HD (dB)
EL1509CL
49
BW (MHz)
VS=±2.5V
AV=5
RF=1.5kΩ
RL=100Ω
f=1MHz
-50
47
45
EL1509CS
43
-60
-65
HD3
-70
41
-75
39
HD2
-80
37
35
2.5
-85
3
3.5
4
4.5
5
5.5
1
6
1.5
2
2.5
±VS (V)
FIGURE 7. DIFFERENTIAL BANDWIDTH vs SUPPLY VOLTAGE
3.5
4
4.5
5.5
-45
AV=5
RF=1.5kΩ
RL=100Ω
3
-55
EL1509CS
-60
HD (dB)
2
1
0
VS=±6V
AV=5
RF=1.5kΩ
RL=100Ω
f=1MHz
-50
-65
-70
HD3
-75
EL1509CL
-80
-1
HD2
-85
-90
-2
2.5
3
3.5
4
4.5
5
5.5
1
6
3
5
7
FIGURE 9. DIFFERENTIAL PEAKING vs SUPPLY VOLTAGE
-45
-55
13
-45
15
17
19
-55
THD (dB)
VS=±2.5V
-70
-75
-60
VS=±2.5V
-65
VS=±6V
-70
VS=±6V
-80
AV=5V
RF=1.5kΩ
RL=100Ω
f=1MHz
-50
-60
-65
11
FIGURE 10. DIFFERENTIAL HARMONIC DISTORTION vs
DIFFERENTIAL OUTPUT VOLTAGE (ALL
PACKAGES)
AV=5
RF=1.5kΩ
RL=100Ω
f=150kHz
-50
9
VOP-P (V)
±VS (V)
THD (dB)
5
FIGURE 8. DIFFERENTIAL HARMONIC DISTORTION vs
DIFFERENTIAL OUTPUT VOLTAGE (ALL
PACKAGES)
4
PEAKING (dB)
3
VOP-P (V)
-75
-85
-90
-80
1
3
5
7
11
9
13
15
17
19
21
VOP-P (V)
FIGURE 11. DIFFERENTIAL TOTAL HARMONIC DISTORTION
vs DIFFERENTIAL OUTPUT VOLTAGE (ALL
PACKAGES)
4
1
3
5
7
9
11
13
15
17
19
VOP-P (V)
FIGURE 12. DIFFERENTIAL TOTAL HARMONIC DISTORTION
vs DIFFERENTIAL OUTPUT (ALL PACKAGES)
FN7015.2
March 26, 2007
EL1509
Typical Performance Curves
-10
100
VOLTAGE NOISE (nV/√Hz),
CURRENT NOISE (pA/√Hz)
-20
ISOLATION (dB)
-30
-40
-50
B→A
-60
-70
A→B
-80
-90
IB10
EN
IB+
-100
-110
10K
100K
10M
1M
1
10
100M
100
1K
FIGURE 13. CHANNEL ISOLATION vs FREQUENCY
100K
1M
10M
100M
FIGURE 14. VOLTAGE AND CURRENT NOISE vs FREQUENCY
30
100
OUTPUT IMPEDANCE (Ω)
20
10
0
PSRR (dB)
10K
FREQUENCY (Hz)
FREQUENCY (Hz)
-10
-20
-30
PSRR-
-40
-50
PSRR+
VS=±12V
AV=1
RF=1.5kΩ
10
1
0.1
0.01
-60
-70
10K
100K
1M
10M
0.001
10K
100M
100K
FIGURE 15. POWER SUPPLY REJECTION vs FREQUENCY
MAGNITUDE (Ω)
100K
0.06
0
0.05
-50
-100
-150
10K
-200
1K
-250
1K
10K
100K
1M
10M
-300
100M
FREQUENCY (Hz)
FIGURE 17. TRANSIMEDANCE (ROL) vs FREQUENCY
5
DIFFERENTIAL GAIN (%),
DIFFERENTIAL PHASE (°)
GAIN
PHASE
100
100
100M
FIGURE 16. OUTPUT IMPEDANCE vs FREQUENCY
50
PHASE (°)
10M
1M
10M
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
0.04
GAIN
0.03
PHASE
0.02
0.01
0
0
1
2
3
4
5
NUMBER OF 150Ω LOADS
FIGURE 18. DIFFERENTIAL GAIN & PHASE
FN7015.2
March 26, 2007
EL1509
Typical Performance Curves
10
INPUT BIAS CURRENT (µA)
SUPPLY CURRENT (mA)
14.5
14
13.5
13
8
6
IB-
4
2
0
-2
IB+
-4
-6
-8
12.5
-50
-25
0
25
50
75
100
125
-10
-50
150
-25
0
TEMPERATURE (°C)
25
50
75
100
125
150
TEMPERATURE (°C)
FIGURE 19. SUPPLY CURRENT vs TEMPERATURE
FIGURE 20. INPUT BIAS CURRENT vs TEMPERATURE
5.2
520
510
5.15
SLEW RATE (V/µs)
OUTPUT VOLTAGE (±V)
RL=100Ω
5.1
50.5
5
4.95
4.9
500
490
480
470
460
450
4.85
4.8
-50
-25
0
25
50
75
100
125
440
-50
150
-25
0
TEMPERATURE (°C)
FIGURE 21. OUTPUT VOLTAGE vs TEMPERATURE
50
75
100
125
150
FIGURE 22. SLEW RATE vs TEMPERATURE
7
6
OFFSET VOLTAGE (mV)
16
14
12
IS (mA)
25
TEMPERATURE (°C)
10
8
6
4
2
5
4
3
2
1
0
-1
-2
0
0
1
2
3
4
5
6
7
±VS (V)
FIGURE 23. SUPPLY CURRENT vs SUPPLY VOLTAGE
6
-3
-50
-25
0
25
50
75
100
125
150
TEMPERATURE (°C)
FIGURE 24. OFFSET VOLTAGE vs TEMPERATURE
FN7015.2
March 26, 2007
EL1509
Typical Performance Curves
0.9
POWER DISSIPATION (W)
TRANSIMPEDANCE (MΩ)
3
2.5
2
1.5
1
0.5
JEDEC JESD51-3 AND SEMI G42-88 (SINGLE
LAYER) TEST BOARD
0.8
781mW
0.7
SO
8
16
0.6
0.5
0°
&
DF
N8
C/
W
0.4
0.3
0.2
0.1
0
-50
0
-25
0
25
50
75
100
125
150
TEMPERATURE (°C)
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 25. TRANSIMEDANCE vs TEMPERATURE
FIGURE 26. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY (4-LAYER) TEST BOARD (DFN EXPOSED
DIEPAD SOLDERED TO PCB PER JESD51-5)
POWER DISSIPATION (W)
3.5
2.907W
3
2.5
43
2
1.5
DF
N8
°C
/W
1.136W
S O8
11 0°
C/W
1
0.5
0
0
25
75 85 100
50
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 27. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
Applications Information
Product Description
The EL1509 is a dual operational amplifier designed for
customer premise line driving in DMT ADSL solutions. It is a
dual current mode feedback amplifier with low distortion
while drawing moderately low supply current. It is built using
Elantec's proprietary complimentary bipolar process and is
offered in industry standard pin-outs. Due to the current
feedback architecture, the EL1509 closed-loop 3dB
bandwidth is dependent on the value of the feedback
resistor. First the desired bandwidth is selected by choosing
the feedback resistor, RF, and then the gain is set by picking
the gain resistor, RG. The curves at the beginning of the
Typical Performance Curves section show the effect of
varying both RF and RG. The 3dB bandwidth is somewhat
dependent on the power supply voltage.
7
Power Supply Bypassing and Printed Circuit
Board Layout
As with any high frequency device, good printed circuit
board layout is necessary for optimum performance. Ground
plane construction is highly recommended. Lead lengths
should be as short as possible, below ¼”. The power supply
pins must be well bypassed to reduce the risk of oscillation.
A 1.0µF tantalum capacitor in parallel with a 0.01µF ceramic
capacitor is adequate for each supply pin.
For good AC performance, parasitic capacitances should be
kept to a minimum, especially at the inverting input. This
implies keeping the ground plane away from this pin. Carbon
resistors are acceptable, while use of wire-wound resistors
should not be used because of their parasitic inductance.
Similarly, capacitors should be low inductance for best
performance.
FN7015.2
March 26, 2007
EL1509
Capacitance at the Inverting Input
Supply Voltage Range
Due to the topology of the current feedback amplifier, stray
capacitance at the inverting input will affect the AC and
transient performance of the EL1509 when operating in the
non-inverting configuration.
The EL1509 has been designed to operate with supply
voltages from ±2.5V to ±6V. Optimum bandwidth, slew rate,
and video characteristics are obtained at higher supply
voltages. However, at ±2.5V supplies, the 3dB bandwidth at
AV = +2 is a respectable 40MHz.
In the inverting gain mode, added capacitance at the
inverting input has little effect since this point is at a virtual
ground and stray capacitance is therefore not “seen” by the
amplifier.
Single Supply Operation
If a single supply is desired, values from +5V to +12V can be
used as long as the input common mode range is not
exceeded. When using a single supply, be sure to either 1)
DC bias the inputs at an appropriate common mode voltage
and AC couple the signal, or 2) ensure the driving signal is
within the common mode range of the EL1509.
Feedback Resistor Values
The EL1509 has been designed and specified with RF =
1.5kΩ for AV = +5. This value of feedback resistor yields
extremely flat frequency response with little to no peaking
out to 50MHz. As is the case with all current feedback
amplifiers, wider bandwidth, at the expense of slight
peaking, can be obtained by reducing the value of the
feedback resistor. Inversely, larger values of feedback
resistor will cause rolloff to occur at a lower frequency. See
the curves in the Typical Performance Curves section which
show 3dB bandwidth and peaking vs. frequency for various
feedback resistors and various supply voltages.
ADSL CPE Applications
The EL1509 is designed as a line driver for ADSL CPE
modems. It is capable of outputting 250mA of output current
with a typical supply voltage headroom of 1.3V. It can
achieve -85dBc of distortion at low 7.1mA of supply current
per amplifier.
The average line power requirement for the ADSL CPE
application is 13dBm (20mW) into a 100Ω line. The average
line voltage is 1.41VRMS. The ADSL DMT peak to average
ratio (crest factor) of 5.3 implies peak voltage of 7.5V into the
line. Using a differential drive configuration and transformer
coupling with standard back termination, a transformer ratio
of 1:2 is selected. The circuit configuration is as shown
below.
Bandwidth vs Temperature
Whereas many amplifier's supply current and consequently
3dB bandwidth drop off at high temperature, the EL1509 was
designed to have little supply current variations with
temperature. An immediate benefit from this is that the 3dB
bandwidth does not drop off drastically with temperature.
+
-
12.5
TX1
1.5k
AFE
100
464Ω
+
-
1:2
12.5
1.5k
8
FN7015.2
March 26, 2007
EL1509
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M C A B
e
H
C
A2
GAUGE
PLANE
SEATING
PLANE
A1
0.004 C
0.010 M C A B
L
b
0.010
4° ±4°
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
INCHES
SYMBOL
SO-14
SO16 (0.300”)
(SOL-16)
SO20
(SOL-20)
SO24
(SOL-24)
SO28
(SOL-28)
TOLERANCE
NOTES
A
0.068
0.068
0.068
0.104
0.104
0.104
0.104
MAX
-
A1
0.006
0.006
0.006
0.007
0.007
0.007
0.007
±0.003
-
A2
0.057
0.057
0.057
0.092
0.092
0.092
0.092
±0.002
-
b
0.017
0.017
0.017
0.017
0.017
0.017
0.017
±0.003
-
c
0.009
0.009
0.009
0.011
0.011
0.011
0.011
±0.001
-
D
0.193
0.341
0.390
0.406
0.504
0.606
0.704
±0.004
1, 3
E
0.236
0.236
0.236
0.406
0.406
0.406
0.406
±0.008
-
E1
0.154
0.154
0.154
0.295
0.295
0.295
0.295
±0.004
2, 3
e
0.050
0.050
0.050
0.050
0.050
0.050
0.050
Basic
-
L
0.025
0.025
0.025
0.030
0.030
0.030
0.030
±0.009
-
L1
0.041
0.041
0.041
0.056
0.056
0.056
0.056
Basic
-
h
0.013
0.013
0.013
0.020
0.020
0.020
0.020
Reference
-
16
20
24
28
Reference
-
N
SO-8
SO16
(0.150”)
8
14
16
Rev. M 2/07
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
9
FN7015.2
March 26, 2007
EL1509
Dual Flat No-Lead Package Family (DFN)
MDP0047
A
DUAL FLAT NO-LEAD PACKAGE FAMILY (JEDEC REG: MO-229)
D
MILLIMETERS
N N-1
0.075 C
2X
PIN #1
I.D.
E
1
DFN8
DFN10
TOLERANCE
A
0.85
0.90
±0.10
A1
0.02
0.02
+0.03/-0.02
b
0.30
0.25
±0.05
c
0.20
0.20
Reference
D
4.00
3.00
Basic
D2
3.00
2.25
Reference
E
4.00
3.00
Basic
E2
2.20
1.50
Reference
e
0.80
0.50
Basic
L
0.50
0.50
±0.10
L1
0.10
0
Maximum
2
0.075 C
B
2X
TOP VIEW
(D2)
4
SYMBOL
L1
N-1
N
L
(N LEADS)
Rev. 2 2/07
NOTES:
(E2)
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Exposed lead at side of package is a non-functional feature.
PIN #1 I.D.
1
2
5
3
e
b
0.10 M C A B
4. Exposed leads may extend to the edge of the package or be
pulled back. See dimension “L1”.
5. Inward end of lead may be square or circular in shape with radius
(b/2) as shown.
BOTTOM VIEW
0.10
3. Bottom-side pin #1 I.D. may be a diepad chamfer, an extended
tiebar tab, or a small square as shown.
6. N is the total number of leads on the device.
C
C
SEATING
PLANE
0.08
C
SEE DETAIL "X"
(N LEADS
& EXPOSED PAD)
2
C
A
(c)
A1
DETAIL X
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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
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10
FN7015.2
March 26, 2007
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