DATASHEET

EL1510
®
Data Sheet
March 26, 2007
FN7122.2
Medium Power Differential Line Driver
Features
The EL1510 is a dual operational amplifier designed for
central office and customer premise line driving in both
SDSL and ADSL solutions. This device features a high drive
capability of 250mA while consuming only 7.5mA of supply
current per amplifier, operating from ±12V supplies. This
driver achieves a typical distortion of less than -85dBc, at
150kHz into a 25Ω load. The EL1510 is available in the
power 8 Ld DFN package and is specified for operation over
the full -40°C to +85°C temperature range. The DFN
package has the potential for a very low junction to ambient
thermal resistance of 43°C/W, making it suitable for high
power applications. The EL1510 is in the 8 Ld SOIC
package and thus is limited to applications where the power
dissipation in the device is less than 781mW.
• 40VP-P differential output drive into 100Ω
The EL1510 is ideal for CPE modem applications in ADSL,
HDSL2, G.SHDSL, and VDSL.
• -85dBc typical driver output distortion at full output at
150kHz
• Low quiescent current of 7.5mA per amplifier
• Pb-free plus anneal available (RoHS compliant)
Applications
• ADSL G.lite CO line driving
• G.SHDSL, HDSL2 line drivers
• ADSL full rate CPE line driving
• Video distribution amplifiers
• Video twisted-pair line drivers
Ordering Information
Pinouts
PART NUMBER
PART
TAPE &
MARKING REEL
PACKAGE
PKG.
DWG. #
EL1510CS
1510CS
-
8 Ld SOIC
MDP0027
EL1510CS-T7
1510CS
7”
8 Ld SOIC
MDP0027
EL1510CS-T13
1510CS
13”
8 Ld SOIC
MDP0027
7 OUTB
EL1510CSZ
(See Note)
1510CSZ
-
8 Ld SOIC
(Pb-Free)
MDP0027
6 INB-
EL1510CSZ-T7
(See Note)
1510CSZ
7”
8 Ld SOIC
(Pb-Free)
MDP0027
EL1510CSZ-T13 1510CSZ
(See Note)
13”
8 Ld SOIC
(Pb-Free)
MDP0027
EL1510
(8 LD SOIC)
TOP VIEW
OUTA 1
8 VS
INA- 2
+
INA+ 3
GND
5 INB+
+
4
EL1510
(8 LD DFN)
TOP VIEW
OUTA
1
INA-
2
INA+
3
+
-
Amp A
GND
+
4
8
VS
7
OUTB
6
INB-
5
INB+
EL1510CL
1510CL
-
8 Ld DFN
MDP0047
EL1510CL-T7
1510CL
7”
8 Ld DFN
MDP0047
EL1510CL-T13
1510CL
13”
8 Ld DFN
MDP0047
NOTE: Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with
both SnPb and Pb-free soldering operations. Intersil Pb-free products
are MSL classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J STD-020C.
Amp B
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002, 2004, 2007. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
EL1510
Absolute Maximum Ratings (TA = +25°C)
VS+ Voltage to Ground . . . . . . . . . . . . . . . . . . . . . . -0.3V to +26.4V
VIN+ Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND to VS+
Current into any Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8mA
Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 75mA
Ambient Operating Temperature Range . . . . . . . . . .-40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . . . . . .-60°C to +150°C
Operating Junction Temperature . . . . . . . . . . . . . . .-40°C to +150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
VS = ±12V, RF = 1.5kΩ, RL = 100Ω to mid supply, TA = 25°C unless otherwise specified.
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
BW
-3dB Bandwidth
AV = +4
70
MHz
HD
Total Harmonic Distortion
f = 1MHz, VO = 16VP-P, RL = 50Ω
-75
dBc
dG
Differential Gain
AV = +2, RL = 37.5Ω
0.17
%
dθ
Differential Phase
AV = +2, RL = 37.5Ω
0.1
°
SR
Slewrate
VOUT from -4.5V to +4.5V
500
V/µs
350
DC PERFORMANCE
VOS
Offset Voltage
-17
17
mV
ΔVOS
VOS Mismatch
-10
10
mV
ROL
Transimpedance
3.5
MΩ
VOUT from -4.5V to +4.5V
1
2
INPUT CHARACTERISTICS
IB+
Non-Inverting Input Bias Current
-5
5
µA
IB-
Inverting Input Bias Current
-30
30
µA
ΔIB-
IB- Mismatch
-20
20
µA
eN
Input Noise Voltage
2.8
nV/√ Hz
iN+
+Input Noise Current
1.8
pA/√ Hz
iN-
-Input Noise Current
19
pA/√ Hz
OUTPUT CHARACTERISTICS
VOUT
Loaded Output Swing Single Ended
RL = 100Ω to GND
±10.3
±10.9
V
VOUT P
Loaded Output Swing Single Ended
RL = 25Ω to GND
9.5
10.2
V
VOUT N
Loaded Output Swing Single Ended
RL = 25Ω to GND
-8.2
-9.8
V
IOUT
Output Current
RL = 0Ω
500
mA
VS
Supply Voltage
Single Supply
IS
Supply Current per Amplifier
All Outputs at 0V
SUPPLY
2
5
7.5
24
V
9
mA
FN7122.2
March 26, 2007
EL1510
Typical Performance Curves
28
24
55
VS=±12V
AV=10
RL=100Ω
51
49
20
RF=1kΩ
16
BW (MHz)
RF=1.5kΩ
GAIN (dB)
AV=5
RF=1.5kΩ
RL=100Ω
53
8 Ld DFN
47
45
43
RF=2kΩ
8 Ld SO
41
12
39
37
8
100K
35
1M
10M
100M
5
6
8
7
FIGURE 1. DIFFERENTIAL FREQUENCY RESPONSE vs RF
11
12
FIGURE 2. DIFFERENTIAL BANDWIDTH vs SUPPLY VOLTAGE
16
22
18
10
9
±VS (V)
FREQUENCY (Hz)
VS=±12V
AV=5
RL=100Ω
14
12
RF=1kΩ
14
10
IS (mA)
GAIN (dB)
RF=1.5kΩ
10
8
6
RF=2kΩ
4
6
2
2
100K
0
1M
10M
100M
0
1
2
4
3
5
FREQUENCY (Hz)
8
9
10 11 12 13
FIGURE 4. SUPPLY CURRENT vs SUPPLY VOLTAGE
-45
22
VS=±12V
AV=5
RL=100Ω
RF=1.5kΩ
CL=22pF
VS=±6V
AV=5
RF=1.5kΩ
RL=100Ω
f=1MHz
-50
-55
CL=10pF
-60
14
THD (dB)
GAIN (dB)
7
±VS (V)
FIGURE 3. DIFFERENTIAL FREQUENCY RESPONSE vs RF
18
6
10
CL=0pF
-65
-70
VS=±6V
VS=±12V
-75
-80
6
-85
2
100K
-90
1M
10M
100M
FREQUENCY (Hz)
FIGURE 5. DIFFERENTIAL FREQUENCY RESPONSE vs CL
3
1
5
9
13
17
21
25
29
33
37
41
45
VOP-P (V)
FIGURE 6. DIFFERENTIAL TOTAL HARMONIC DISTORTION
vs DIFFERENTIAL OUTPUT VOLTAGE - ALL
PACKAGES
FN7122.2
March 26, 2007
EL1510
Typical Performance Curves
(Continued)
-50
-40
VS=±6V
AV=5
RF=1.5kΩ
RL=100Ω
f=1MHz
-55
-60
-60
-70
THD (dB)
-65
HD (dB)
VS=±12V
RLOAD=200Ω (DIFF)
AV=10 & 15
-50
HD3
-75
-70
100kHz
-80
HD2
-90
-85
-90
50kHz
-100
1
3
5
7
9
11
13
15
17
19
0
5
10
15
25
FIGURE 8. DISTORTION RESULTS
FIGURE 7. DIFFERENTIAL HARMONIC DISTORTION vs
DIFFERENTIAL OUTPUT VOLTAGE - ALL
PACKAGES
-50
-30
VS=±12V
AV=5
RF=1.5kΩ
RL=100Ω
f=1MHz
-60
VS=±6V
RLOAD=200Ω (DIFF)
AV=10 & 15
-40
-50
-65
THD (dB)
-55
HD3
-70
-75
-60
100kHz
-70
200kHz
-80
-80
-85
HD2
50kHz
-90
-90
1
5
9
13
17
21
25
29
33
37
41
0
45
1
2
3
VOP-P (V)
4
5
6
7
8
9
10
VOUT PTP (V)
FIGURE 10. DISTORTION RESULTS
FIGURE 9. DIFFERENTIAL HARMONIC DISTORTION vs
DIFFERENTIAL OUTPUT VOLTAGE - ALL
PACKAGES
100
-50
-60
OUTPUT IMPEDANCE (Ω)
AV=5
RF=1.5kΩ
RL=100Ω
f=1MHz
-55
THD (dB)
20
VOUT PTP (V)
VOP-P (V)
HD (dB)
200kHz
-80
-65
VS=±6V
-70
VS=±12V
-75
10
VS=±12V
AV=1
RF=1.5kΩ
1
0.1
0.01
-80
-85
1
5
9
13
17
21
25
29
33
37
41
45
VOP-P (V)
FIGURE 11. DIFFERENTIAL TOTAL HARMONIC DISTORTION
vs DIFFERENTIAL OUTPUT VOLTAGE - ALL
PACKAGES
4
0.001
10K
100K
1M
10M
100M
FREQUENCY (Hz)
FIGURE 12. OUTPUT IMPEDANCE vs FREQUENCY
FN7122.2
March 26, 2007
EL1510
Typical Performance Curves
(Continued)
100
VOLTAGE NOISE (nV/√Hz),
CURRENT NOISE (pA/√Hz)
CHANNEL SEPARATION (dB)
-10
-30
-50
-70
B→A
A→B
-90
IB-
10
EN
IB+
1
-110
10K
100K
1M
10M
10
100M
100
1K
10K
100K
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 13. CHANNEL SEPARATION vs FREQUENCY
FIGURE 14. VOLTAGE AND CURRENT NOISE vs FREQUENCY
20
0.18
0.16
DIFFERENTIAL GAIN (%)
PSRR (dB)
0
-20
-40
PSRR-
PSRR+
-60
VS=±12V
0.14
VS=±6V
0.12
0.1
0.08
0.06
0.04
0.02
02
-80
10K
100K
1M
10M
0
100M
1
2
3
4
5
NUMBER of 150Ω LOADS
FREQUENCY (Hz)
FIGURE 15. PSRR vs FREQUENCY
FIGURE 16. DIFFERENTIAL GAIN
0.12
40
10M
PHASE
-80
100K
-120
-160
10K
GAIN
-200
-240
1K
PHASE (°)
MAGNITUDE (Ω)
-40
DIFFERENTIAL PHASE (°)
0
1M
0.1
0.08
VS=±6V
0.06
VS=±12V
0.04
0.02
-280
100
1K
10K
100K
1M
10M
-320
100M
FREQUENCY (Hz)
FIGURE 17. TRANSIMPEDANCE (ROL) vs FREQUENCY
5
0
0
1
2
3
4
5
NUMBER of 150Ω LOADS
FIGURE 18. DIFFERENTIAL PHASE
FN7122.2
March 26, 2007
EL1510
(Continued)
16
490
15.5
470
SLEW RATE (V/µs)
SUPPLY CURRENT (mA)
Typical Performance Curves
15
14.5
14
13.5
13
-50
450
430
410
390
370
-25
0
25
50
75
100
125
350
-50
150
-25
0
DIE TEMPERATURE (°C)
FIGURE 19. SUPPLY CURRENT vs TEMPERATURE
50
75
100
125
150
FIGURE 20. SLEW RATE vs TEMPERATURE
11.1
18
VS=±12V
RL=200Ω
16
14
11
12
10
VOUT
INPUT BIAS CURRENT (µA)
25
DIE TEMPERATURE (°C)
8
IB-
6
10.9
4
10.8
2
IB+
0
-2
-50
-25
0
25
50
75
100
125
10.7
-50
150
0
FIGURE 21. INPUT BIAS CURRENT vs TEMPERATURE
100
150
FIGURE 22. OUTPUT VOLTAGE vs TEMPERATURE
10
-10.6
VS=±12V
RL=200Ω
8
6
-10.8
VOUT
OFFSET VOLTAGE (mV)
50
DIE TEMPERATURE (°C)
DIE TEMPERATURE (°C)
4
2
-11
0
-2
-50
-25
0
25
50
75
100
125
DIE TEMPERATURE (°C)
FIGURE 23. OFFSET VOLTAGE vs TEMPERATURE
6
150
-11.2
-50
0
50
100
150
DIE TEMPERATURE (°C)
FIGURE 24. OUTPUT VOLTAGE vs TEMPERATURE
FN7122.2
March 26, 2007
EL1510
Typical Performance Curves
(Continued)
3.5
1.8
1.6
POWER DISSIPATION (W)
TRANSIMPEDANCE (MΩ)
3
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
2.5
2
1.5
1
0.5
1.4
1.136W
1.2
1
θJ
0.8
SO
8
10
°C
/W
A =1
0.6
0.4
0.2
0
-50
-25
0
25
50
75
100
125
0
150
0
25
75 85
50
100
125
150
DIE TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
FIGURE 25. TRANSIMPEDANCE vs TEMPERATURE
4.5
FIGURE 26. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD - DFN EXPOSED
DIEPAD SOLDERED TO PCB PER JESD51-5
1.2
POWER DISSIPATION (W)
POWER DISSIPATION (W)
4
3.5
2.907W
3
DF
N8
θJ
A =4
3 °C
/W
2.5
2
1.5
1
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1
781mW
0.8
SO
θJ
0.6
A =1
8&
60
DF
N8
°C
/W
0.4
0.2
0.5
0
0
0
25
75 85
50
100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 27. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
Applications Information
Product Description
The EL1510 is a dual operational amplifier designed for line
driving in DMT ADSL solutions. It is a dual current mode
feedback amplifier with low distortion while drawing
moderately low supply current. It is built using Elantec's
proprietary complimentary bipolar process and is offered in
industry standard pin-outs. Due to the current feedback
architecture, the EL1510 closed-loop 3dB bandwidth is
dependent on the value of the feedback resistor. First the
desired bandwidth is selected by choosing the feedback
resistor, RF, and then the gain is set by picking the gain
resistor, RG. The curves at the beginning of the Typical
Performance Curves section show the effect of varying both
RF and RG. The 3dB bandwidth is somewhat dependent on
the power supply voltage.
7
0
25
50
75 85
100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 28. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
Power Supply Bypassing and Printed Circuit
Board Layout
As with any high frequency device, good printed circuit
board layout is necessary for optimum performance. Ground
plane construction is highly recommended. Lead lengths
should be as short as possible, below ¼”. The power supply
pins must be well bypassed to reduce the risk of oscillation.
A 1.0µF tantalum capacitor in parallel with a 0.01µF ceramic
capacitor is adequate for each supply pin.
For good AC performance, parasitic capacitances should be
kept to a minimum, especially at the inverting input. This
implies keeping the ground plane away from this pin. Carbon
resistors are acceptable, while use of wire-wound resistors
should not be used because of their parasitic inductance.
Similarly, capacitors should be low inductance for best
performance.
FN7122.2
March 26, 2007
EL1510
Capacitance at the Inverting Input
Supply Voltage Range and Operation
Due to the topology of the current feedback amplifier, stray
capacitance at the inverting input will affect the AC and
transient performance of the EL1510 when operating in the
non-inverting configuration.
The EL1510 has been designed to operate with supply
voltages from ±2.5V to ±12V. If a single supply is desired,
values from +5V to +24V can be used as long as the input
common mode range is not exceeded. When using a single
supply, be sure to either 1) DC bias the inputs at an
appropriate common mode voltage and AC couple the
signal, or 2) ensure the driving signal is within the common
mode range of the EL1510.
In the inverting gain mode, added capacitance at the
inverting input has little effect since this point is at a virtual
ground and stray capacitance is therefore not “seen” by the
amplifier.
Feedback Resistor Values
The EL1510 has been designed and specified with
RF=1.5kΩ for AV=+5. This value of feedback resistor yields
extremely flat frequency response with no peaking out to
40MHz. As is the case with all current feedback amplifiers,
wider bandwidth, at the expense of slight peaking, can be
obtained by reducing the value of the feedback resistor.
Inversely, larger values of feedback resistor will cause rolloff
to occur at a lower frequency. See the curves in the Typical
Performance Curves section which show 3dB bandwidth and
peaking vs frequency for various feedback resistors and
various supply voltages.
Bandwidth vs Temperature
Whereas many amplifiers’ supply current and consequently
3dB bandwidth drop-off at high temperature, the EL1510
was designed to have little supply current variations with
temperature. An immediate benefit from this is that the 3dB
bandwidth does not drop off drastically with temperature.
ADSL CPE Applications
The EL1510 is designed as a line driver for ADSL CPE
modems. It is capable of outputting 400mA of output current
with a typical supply voltage headroom of 1.8V. It can
achieve -85dBc of distortion at low 7.5mA of supply current
per amplifier.
The average line power requirement for the ADSL CPE
application is 13dBm (20mW) into a 100Ω line. The average
line voltage is 1.41VRMS. The ADSL DMT peak to average
ratio (crest factor) of 5.3 implies peak voltage of 7.5V into the
line. Using a differential drive configuration and transformer
coupling with standard back termination, a transformer ratio
of 1:1 is selected. The circuit configuration is as shown
below.
+
-
50
1.5k
TX1
AFE
100
300Ω
+
-
1:1
50
1.5k
8
FN7122.2
March 26, 2007
EL1510
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M C A B
e
H
C
A2
GAUGE
PLANE
SEATING
PLANE
A1
0.004 C
0.010 M C A B
L
b
0.010
4° ±4°
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
INCHES
SYMBOL
SO-14
SO16 (0.300”)
(SOL-16)
SO20
(SOL-20)
SO24
(SOL-24)
SO28
(SOL-28)
TOLERANCE
NOTES
A
0.068
0.068
0.068
0.104
0.104
0.104
0.104
MAX
-
A1
0.006
0.006
0.006
0.007
0.007
0.007
0.007
±0.003
-
A2
0.057
0.057
0.057
0.092
0.092
0.092
0.092
±0.002
-
b
0.017
0.017
0.017
0.017
0.017
0.017
0.017
±0.003
-
c
0.009
0.009
0.009
0.011
0.011
0.011
0.011
±0.001
-
D
0.193
0.341
0.390
0.406
0.504
0.606
0.704
±0.004
1, 3
E
0.236
0.236
0.236
0.406
0.406
0.406
0.406
±0.008
-
E1
0.154
0.154
0.154
0.295
0.295
0.295
0.295
±0.004
2, 3
e
0.050
0.050
0.050
0.050
0.050
0.050
0.050
Basic
-
L
0.025
0.025
0.025
0.030
0.030
0.030
0.030
±0.009
-
L1
0.041
0.041
0.041
0.056
0.056
0.056
0.056
Basic
-
h
0.013
0.013
0.013
0.020
0.020
0.020
0.020
Reference
-
16
20
24
28
Reference
-
N
SO-8
SO16
(0.150”)
8
14
16
Rev. M 2/07
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
9
FN7122.2
March 26, 2007
EL1510
Dual Flat No-Lead Package Family (DFN)
MDP0047
A
DUAL FLAT NO-LEAD PACKAGE FAMILY (JEDEC REG: MO-229)
D
MILLIMETERS
N N-1
0.075 C
2X
PIN #1
I.D.
E
1
DFN8
DFN10
TOLERANCE
A
0.85
0.90
±0.10
A1
0.02
0.02
+0.03/-0.02
b
0.30
0.25
±0.05
c
0.20
0.20
Reference
D
4.00
3.00
Basic
D2
3.00
2.25
Reference
E
4.00
3.00
Basic
E2
2.20
1.50
Reference
e
0.80
0.50
Basic
L
0.50
0.50
±0.10
L1
0.10
0
Maximum
2
0.075 C
B
2X
TOP VIEW
(D2)
4
SYMBOL
L1
N-1
N
L
(N LEADS)
Rev. 2 2/07
NOTES:
(E2)
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Exposed lead at side of package is a non-functional feature.
PIN #1 I.D.
1
2
5
3
e
b
0.10 M C A B
4. Exposed leads may extend to the edge of the package or be
pulled back. See dimension “L1”.
5. Inward end of lead may be square or circular in shape with radius
(b/2) as shown.
BOTTOM VIEW
0.10
3. Bottom-side pin #1 I.D. may be a diepad chamfer, an extended
tiebar tab, or a small square as shown.
6. N is the total number of leads on the device.
C
C
SEATING
PLANE
0.08
C
SEE DETAIL "X"
(N LEADS
& EXPOSED PAD)
2
C
A
(c)
A1
DETAIL X
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
10
FN7122.2
March 26, 2007
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