DATASHEET

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ENDED ACEMENT PA
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MENDE L1533
RECOM
IS
DATASHEET
Dual Channel Differential DSL Line Driver
ISL1532
Features
The ISL1532 is a dual channel differential amplifier designed
for driving full rate ADSL2+ signals at very low power
dissipation. The high drive capability of 450mA makes this
driver ideal for DMT designs. It contains two pairs of wideband,
high-voltage, current mode feedback amplifiers designed on
Intersil’s HS30 Bipolar SOI process for low power consumption
in DSL systems.
• 450mA output drive capability
These drivers achieve an MTPR distortion measurement of
better than 70dB, while consuming typically 5mA per DSL
channel of total supply current. This supply current can be set
using a resistor on the IADJ pin. Two other pins (C0 and C1) can
also be used to adjust supply current to one of four preset
modes (full-IS, 3/4-IS, 1/2-IS and full power-down). C0 and C1
inputs are design to pull high initially. Floating these inputs will
put the device in disable mode. This is contrary to EL1528
where C0 and C1 inputs pull low initially and is in the enable
state when C0 and C1 pins are floated.
• 44.4VP-P differential output drive into 100Ω
• ±5V to ±15V supply operation
• MTPR of -70dB
• Operates down to 2mA per amplifier supply current
• Current control pins
• Channel separation
- 80dB at 500kHz
• Direct pin-to-pin replacement for EL1528
• RoHS compliant
Applications
• Dual port ADSL2+ line drivers
• HDSL line drivers
The ISL1532 operates on ±5V to ±15V supplies and retains its
bandwidth and linearity over the complete supply range.
The device is supplied in a thermally-enhanced 20 Ld HTSSOP
and the small footprint (4x5mm) 24 Ld QFN packages. The
ISL1532 is specified for operation across the full -40°C to
+85°C temperature range.
The ISL1532 provides larger output swing at heavy loads,
higher slew rate and higher bandwidth while maintaining
pin-to-pin drop-in compatibility with the EL1528. The ISL1532
integrates 50k pull-up resistors on C0 and C1 pins.
TOP VIEW
2 VOUTA
TOP VIEW
2 NC
ISL1532
(20 LD HTSSOP)
2 VS-
ISL1532
(24 LD QFN)
2 C0AB
2 C1AB
Pin Configurations
VINA+ 1
1 VINA-
VINB+ 2
1 VINB-
GND 3
1 VOUTB
THERMAL
PAD
IADJ 4
1 VOUTC
1 VOUTD
NC 1
VIND+ 7
NC 11
1 VIND-
VS+ 1
VINC+ 6
C0CD 9
1 VINC-
C1CD 8
NC 5
C0AB 1
2 VS-
C1AB 2
1 VOUT
VINA+ 3
1 VINA-
VINB+ 4
1 VINB-
GND 5
IADJ 6
THERMAL
PAD*
1 VOUT
1 VOUT
VINC+ 7
1 VINC-
VIND+ 8
1 VIND-
C1CD 9
1 VOUT
C0CD 1
11 VS+
*THERMAL PAD INTERNALLY CONNECTED TO GND
May 1, 2015
FN6173.4
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2006, 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL1532
Ordering Information
PART NUMBER
(Notes 2, 3)
PART MARKING
TEMP RANGE
(°C)
PACKAGE
(RoHS Compliant)
PKG. DWG. #
ISL1532IRZ
1532 IRZ
-40°C to +85°C
24 Ld QFN
MDP0046
ISL1532IRZ-T7 (Notes 1)
1532 IRZ
-40°C to +85°C
24 Ld QFN
MDP0046
ISL1532IRZ-T13 (Notes 1)
1532 IRZ
-40°C to +85°C
24 Ld QFN
MDP0046
ISL1532IVEZ
1532 IVEZ
-40°C to +85°C
20 Ld HTSSOP
MDP0048
ISL1532IVEZ-T7 (Notes 1)
1532 IVEZ
-40°C to +85°C
20 Ld HTSSOP
MDP0048
ISL1532IVEZ-T13 (Notes 1)
1532 IVEZ
-40°C to +85°C
20 Ld HTSSOP
MDP0048
ISL1532IVEZ-EVAL
Demo Board
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see product information page for ISL1532. For more information on MSL, please see tech brief TB363.
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2
FN6173.4
May 1, 2015
ISL1532
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
VS+ to VS- Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 30V
VS+ Voltage to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 30V
VS- Voltage to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -30V to 0.3V
Driver VIN+ Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VS- to VS+
C0, C1 Voltage to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V
IADJ Voltage to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 4V
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7) . . . . . . . . . . 3kV
Machine Model (Per EIAJ ED-4701 Method C-111) . . . . . . . . . . . . . 250V
Current into any Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8mA
Output Current from Driver (Static) . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See page 13
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . .-40°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
Electrical Specifications
PARAMETER
VS = ±12V, RF = 3kΩ, RL= 65Ω, IADJ = C0 = C1 = 0V, TA = +25°C. Amplifiers tested separately.
DESCRIPTION
TEST CONDITIONS
MIN
(Note 4)
TYP
MAX
(Note 4)
UNITS
SUPPLY CHARACTERISTICS
IS+ (Full IS)
Positive Supply Current per Amplifier
All outputs at 0V, C0 = C1 = 0V, RADJ = 0
3.75
4.9
6.5
mA
IS- (Full IS)
Negative Supply Current per Amplifier
All outputs at 0V, C0 = C1 = 0V, RADJ = 0
-6.3
-4.7
-3.5
mA
IS+ (3/4 IS)
Positive Supply Current per Amplifier
All outputs at 0V, C0 = 5V, C1 = 0V, RADJ = 0
3.8
mA
IS- (3/4 IS)
Negative Supply Current per Amplifier
All outputs at 0V, C0 = 5V, C1 = 0V, RADJ = 0
-3.5
mA
IS+ (1/2 IS)
Positive Supply Current per Amplifier
All outputs at 0V, C0 = 0V, C1 = 5V, RADJ = 0
1.87
2.6
3.75
mA
IS- (1/2 IS)
Negative Supply Current per Amplifier
All outputs at 0V, C0 = 0V, C1 = 5V, RADJ = 0
-3.75
-2.4
-1.75
mA
IS+ (Power-down)
Positive Supply Current per Amplifier
All outputs at 0V, C0 = C1 = 5V, RADJ = 0
0.25
1.0
mA
IS- (Power-down)
Negative Supply Current per Amplifier
All outputs at 0V, C0 = C1 = 5V, RADJ = 0
IGND
GND Supply Current per Amplifier
All outputs at 0V
-1.0
0
mA
0.25
mA
INPUT CHARACTERISTICS
VOS
Input Offset Voltage
-10
1
+10
mV
VOS
VOS Mismatch
-5
0
+5
mV
IB+
Noninverting Input Bias Current
-15
+14
µA
IB-
Inverting Input Bias Current
-30
+30
µA
IB-
IB- Mismatch
-25
0
+25
µA
ROL
Transimpedance
1
3.4
8
MΩ
eN
Input Noise Voltage
3.5
nV/ Hz
iN
-Input Noise Current
2
pA/ Hz
VIH
Input High Voltage
C0 and C1 inputs, with signal
1.8
V
C0 and C1 inputs, without signal
1.6
V
VIL
Input Low Voltage
C0 and C1 inputs
IIH0, IIH1
Input High Current for C0, C1
C0 = 5V, C1 = 5V
10
20
IIL
Input Low Current for C0 or C1
C0 = 0V, C1 = 0V
-3.0
-0.3
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3
0.8
V
40
µA
µA
FN6173.4
May 1, 2015
ISL1532
Electrical Specifications
PARAMETER
VS = ±12V, RF = 3kΩ, RL= 65Ω, IADJ = C0 = C1 = 0V, TA = +25°C. Amplifiers tested separately. (Continued)
DESCRIPTION
TEST CONDITIONS
MIN
(Note 4)
TYP
MAX
(Note 4)
UNITS
OUTPUT CHARACTERISTICS
VOUT
Loaded Output Swing
(RL Single-ended to GND)
RL = 100Ω
RL = 50Ω (+)
+10.5
RL = 50Ω (-)
RL = 25Ω (+)
±11.1
V
+10.95
V
-10.95
+10.0
-10.5
+10.7
V
V
RL = 25Ω (-)
-10.5
450
mA
-9.6
V
IOL
Linear Output Current
AV = 5, RL = 10Ω, f = 100kHz, THD = -60dBc
(10Ω single-ended)
IOUT
Output Current
VOUT = 1V, RL = 1Ω
1
A
DYNAMIC PERFORMANCE
BW
-3dB Bandwidth
AV = +5, RL-DIFF = 100Ω
50
MHz
HD2
2nd Harmonic Distortion
fC = 1MHz, RF = 5kΩ, AV = 10,
RL-DIFF = 100ΩVOUT = 2VPP-DIFF
-90
dBc
fC = 1MHz, RF = 5kΩ, AV = 10, RL-DIFF = 50Ω
VOUT = 2VP-P-DIFF
-85
dBc
fC = 1MHz, RF = 5kΩ, AV = 10,
RL-DIFF = 100ΩVOUT = 2VP-P-DIFF
-80
dBc
fC = 1MHz, RF = 5kΩ, AV = 10, RL-DIFF = 50Ω
VOUT = 2VP-P-DIFF
-65
dBc
-70
dBc
400
V/µs
HD3
3rd Harmonic Distortion
MTPR
Multi-tone Power Ratio
26kHz to 1.1MHz, RLINE = 100Ω,
PLINE = 20.4dBM
SR
Slew rate (single-ended)
VOUT from -8V to +8V measured at ±4V
200
NOTE:
4. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
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FN6173.4
May 1, 2015
ISL1532
Pin Descriptions
20 Ld HTSSOP
24 Ld QFN
PIN NAME
1
23
C0AB (Note 5)
FUNCTION
CIRCUIT
DSL Channel 1 current control pin
2.6V
VS+
VS+
50k
COAB
20k
VSIADJ
CIRCUIT 1
2
24
C1AB (Note 5)
5, 11, 12, 21
NC
1
VINA+
3
DSL Channel 1 current control pin
(Reference Circuit 1)
Not connected
Amplifier A non-inverting input
VS+
7.5k
VSCIRCUIT 2
4
2
VINB+
6
4
IADJ (Note 6)
Amplifier B non-inverting input
(Reference Circuit 2)
Supply current control pin for both DSL
Channels 1 and 2
VS+
IADJ
VS-
GND
CIRCUIT 3
5
3
GND
7
6
VINC+
Ground connection
8
7
VIND+
Amplifier D non-inverting input
(Reference Circuit 2)
9
8
C1CD (Note 7)
DSL Channel 2 current control pin
(Reference Circuit 1)
10
9
C0CD (Note 7)
DSL Channel 2 current control pin
(Reference Circuit 1)
11
10
VS+
12
13
VOUTD
Amplifier D output
(Reference Circuit 2)
13
14
VIND-
Amplifier D inverting input
(Reference Circuit 2)
14
15
VINC-
Amplifier C inverting input
(Reference Circuit 2)
15
16
VOUTC
Amplifier C output
(Reference Circuit 2)
16
17
VOUTB
Amplifier B output
(Reference Circuit 2)
17
18
VINB-
Amplifier B inverting input
(Reference Circuit 2)
18
19
VINA-
Amplifier A inverting input
(Reference Circuit 2)
19
20
VOUTA
Amplifier A output
(Reference Circuit 2)
20
22
VS-
Amplifier C non-inverting input
(Reference Circuit 2)
Positive supply
Negative supply
NOTES:
5. Amplifiers A and B comprise DSL Channel 1. The C0AB and C1AB control IS settings for DSL Channel 1.
6. IADJ controls bias current (IS) setting for both DSL channels.
7. Amplifiers C and D comprise DSL Channel 2. The C0CD and C1CD control IS settings for DSL Channel 2.
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FN6173.4
May 1, 2015
ISL1532
Typical Performance Curves
AV = 10
VS = ±12V
RL = 100Ω
RADJ = 0Ω
RF = 2kΩ
AV = 10
VS = ±12V
RL = 100Ω
RADJ = 0Ω
RF = 2kΩ
RF = 3kΩ
RF = 3kΩ
RF = 4kΩ
RF = 4kΩ
FIGURE 1. DIFFERENTIAL FREQUENCY RESPONSE vs RF
(FULL IS)
AV = 10
VS = ±12V
RL = 100Ω
RADJ = 0Ω
RF = 2kΩ
RF = 3kΩ
FIGURE 2. DIFFERENTIAL FREQUENCY RESPONSE vs RF (3/4 IS)
RF = 2kΩ
AV = 10
VS = ±12V
RL = 100Ω
AV = 1 COMMON-MODE
RF = 3kΩ
RF = 4kΩ
RF = 4kΩ
FIGURE 3. DIFFERENTIAL FREQUENCY RESPONSE vs RF (1/2 IS)
AV = 10
VS = ±12V
RL = 100Ω
AV = 1 COMMON-MODE
RF = 2kΩ
RF = 3kΩ
AV = 10
VS = ±12V
RL = 100Ω
AV = 1 COMMON-MODE
RF = 2kΩ
RF = 3kΩ
RF = 4kΩ
FIGURE 5. COMMON-MODE FREQUENCY RESPONSE vs
RF (3/4 IS)
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FIGURE 4. COMMON-MODE FREQUENCY RESPONSE vs RF
(FULL IS)
6
RF = 4kΩ
FIGURE 6. COMMON-MODE FREQUENCY RESPONSE vs
RF (1/2 IS)
FN6173.4
May 1, 2015
ISL1532
Typical Performance Curves (Continued)
AV = 5
VS = ±12V
RL = 100Ω
RADJ = 0Ω
AV = 5
VS = ±12V
RL = 100Ω
RADJ = 0Ω
RF = 2kΩ
RF = 2kΩ
RF = 3kΩ
RF = 3kΩ
RF = 4kΩ
RF = 4kΩ
FIGURE 7. DIFFERENTIAL FREQUENCY RESPONSE vs
RF (FULL IS)
AV = 5
VS = ±12V
RL = 100Ω
RADJ = 0Ω
FIGURE 8. DIFFERENTIAL FREQUENCY RESPONSE vs RF (3/4 IS)
AV = 5
VS = ±12V
RL = 100Ω
AV = 1 COMMON_MODE
RF = 2kΩ
RF = 2kΩ
RF = 3kΩ
RF = 3kΩ
RF = 4kΩ
RF = 4kΩ
FIGURE 9. DIFFERENTIAL FREQUENCY RESPONSE vs RF (1/2 IS)
AV = 5
VS = ±12V
RL = 100Ω
AV = 1 COMMON-MODE
RF = 2kΩ
RF = 4kΩ
RF = 3kΩ
FIGURE 10. COMMON-MODE FREQUENCY RESPONSE vs
RF (FULL IS)
AV = 5
VS = ±12V
RL = 100Ω
AV = 1 COMMON-MODE
RF = 2kΩ
RF = 3kΩ
RF = 4kΩ
FIGURE 11. COMMON-MODEFREQUENCY RESPONSE vs
RF (3/4 IS)
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FIGURE 12. COMMON-MODE FREQUENCY RESPONSE vs
RF (1/2 IS)
FN6173.4
May 1, 2015
ISL1532
Typical Performance Curves (Continued)
AV = 5
VS = ±12V
RL = 100Ω
RF = 3kΩ
47pF
27pF
AV = 5
VS = ±12V
RL = 100Ω
RF = 3kΩ
47pF
27pF
15pF
15pF
0pF
FIGURE 13. DIFFERENTIAL FREQUENCY RESPONSE vs
CL (FULL IS)
47pF
27pF
AV = 5
VS = ±12V
RL = 100Ω
RF = 3kΩ
0pF
FIGURE 14. DIFFERENTIAL FREQUENCY RESPONSE vs CL (3/4 IS)
AV = 10
VS = ±12V
RL = 100Ω
RF = 3kΩ
47pF
27pF
15pF
15pF
0pF
0pF
FIGURE 15. DIFFERENTIAL FREQUENCY RESPONSE vs CL (1/2 IS)
AV = 10
VS = ±12V
RL = 100Ω
RF = 3kΩ
47pF
27pF
0pF
FIGURE 17. DIFFERENTIAL FREQUENCY RESPONSE vs CL (3/4 IS)
8
AV = 10
VS = ±12V
RL = 100Ω
RF = 3kΩ
47pF
27pF
15pF
15pF
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FIGURE 16. DIFFERENTIAL FREQUENCY RESPONSE vs
CL (FULL IS)
0pF
FIGURE 18. DIFFERENTIAL FREQUENCY RESPONSE vs CL (1/2 IS)
FN6173.4
May 1, 2015
ISL1532
Typical Performance Curves (Continued)
VS = ±12V
RF = 3kΩ
AV = 10
VS = ±12V
RF = 3kΩ
AV = 10
RL = 475Ω
RL = 475Ω
RL = 365Ω
RL = 365Ω
RL= 220Ω
RL= 220Ω
RL = 100Ω
RL= 100Ω
FIGURE 19. DIFFERENTIAL FREQUENCY RESPONSE vs
RL (FULL IS)
VS = ±12V
RF = 3kΩ
AV = 10
RL= 475Ω
RL= 365Ω
FIGURE 20. DIFFERENTIAL FREQUENCY RESPONSE vs
RL (3/4 IS)
VS = ±12V
RF = 3kΩ
AV = 5
RL= 220Ω
RL= 100Ω
FIGURE 21. DIFFERENTIAL FREQUENCY RESPONSE vs RL (1/2 IS)
RL = 475Ω
RL = 365Ω
RL = 220Ω
RL = 100Ω
FIGURE 23. DIFFERENTIAL FREQUENCY RESPONSE vs RL (3/4 IS)
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RL= 365Ω
RL= 220Ω
RL= 100Ω
VS = ±12V
RF = 3kΩ
AV = 5
RL= 475Ω
FIGURE 22. DIFFERENTIAL FREQUENCY RESPONSE vs
RL (FULL IS)
VS = ±12V
RF = 3kΩ
AV = 5
RL= 475Ω
RL = 365Ω
RL= 220Ω
RL= 100Ω
FIGURE 24. DIFFERENTIAL FREQUENCY RESPONSE vs RL (1/2 IS)
FN6173.4
May 1, 2015
ISL1532
Typical Performance Curves (Continued)
VS = ±12V
FREQ =1MHz
AV = 5
RL = 100Ω
RF = 3kΩ
VS = ±12V
FREQ = 1MHz
AV = 5
RL = 100Ω
RF = 3kΩ
HD3
THD
THD
HD2
HD2
HD3
DIFFERENTIAL VOP-P
DIFFERENTIAL VOP-P
FIGURE 25. HARMONICS DISTORTION vs DIFFERENTIAL OUTPUT
VOLTAGE (FULL IS)
VS = ±12V
FREQ = 1MHz
AV = 5
RL = 100Ω
RF = 3kΩ
FIGURE 26. HARMONICS DISTORTION vs DIFFERENTIAL OUTPUT
VOLTAGE (3/4 IS)
HD2
THD
THD
HD2
HD3
HD3
DIFFERENTIAL VOP-P
DIFFERENTIAL VOP-P
FIGURE 27. HARMONICS DISTORTION vs DIFFERENTIAL OUTPUT
VOLTAGE (1/2 IS)
THD
HD3
HD2
VS = ±6V
FREQ = 1MHz
AV = 5
RL = 100Ω
RF = 3kΩ
DIFFERENTIAL VOP-P
FIGURE 29. HARMONIC DISTORTION vs DIFFERENTIAL OUTPUT
VOLTAGE (3/4 IS)
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VS = ±6V
FREQ = 1MHz
AV = 5
RL = 100Ω
RF = 3kΩ
FIGURE 28. HARMONIC DISTORTION vs DIFFERENTIAL OUTPUT
VOLTAGE (FULL IS)
HD3
THD
HD2
VS = ±6V
FREQ = 1MHz
AV = 5
RL = 100Ω
RF = 3kΩ
DIFFERENTIAL VOP-P
FIGURE 30. HARMONIC DISTORTION vs DIFFERENTIAL OUTPUT
VOLTAGE (1/2 IS)
FN6173.4
May 1, 2015
ISL1532
Typical Performance Curves (Continued)
VS = ±12V
FREQ = 200kHz
AV = 5
RL = 100Ω
RF = 3kΩ
VS = ±12V
FREQ = 200kHz
AV = 5
RL = 100Ω
RF = 3kΩ
HD3
THD
THD
HD3
HD2
HD2
DIFFERENTIAL VOP-P
DIFFERENTIAL VOP-P
FIGURE 31. HARMONIC DISTORTION vs DIFFERENTIAL OUTPUT
VOLTAGE (FULL IS)
VS = ±12V
FREQ = 200kHz
AV = 5
RL = 100Ω
RF = 3kΩ
FIGURE 32. HARMONIC DISTORTION vs DIFFERENTIAL OUTPUT
VOLTAGE (3/4 IS)
FULL POWER MODE
THD
HD2
3/4 POWER MODE
1/2 POWER MODE
HD3
DIFFERENTIAL VOP-P
±V)
FIGURE 33. HARMONIC DISTORTION vs DIFFERENTIAL OUTPUT
VOLTAGE (1/2 IS)
FIGURE 34. SUPPLY CURRENT vs SUPPLY VOLTAGE
100
ROUT (Ω)
10
±12 VDC
1
0.1
±6 VDC
RADJ (Ω)
0.01
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FIGURE 35. QUIESCENT SUPPLY CURRENT vs RADJ
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FIGURE 36. OUTPUT IMPEDANCE vs FREQUENCY
FN6173.4
May 1, 2015
ISL1532
Typical Performance Curves (Continued)
PSRRAB CD
PSRR+
FIGURE 37. CHANNEL SEPARATION vs FREQUENCY
VS = ±12V
AV = 2
RF = 3kΩ
RSET = 0Ω
FIGURE 38. PSRR vs FREQUENCY
VS = ±12V
AV = 2
RF = 3kΩ
RSET = 0Ω
GAIN
GAIN
PHASE
PHASE
RELATIVE GAIN AND PHASE RL = 100Ω
RELATIVE GAIN AND PHASE RL = 100Ω
FIGURE 39. DIFFERENTIAL GAIN/PHASE (FULL IS)
FIGURE 40. DIFFERENTIAL GAIN/PHASE (3/4 IS)
VS = ±12V
AV = 2
RF = 3kΩ
RSET = 0Ω
GAIN
PHASE
EN
IN-
RELATIVE GAIN AND PHASE RL = 100Ω
FIGURE 41. DIFFERENTIAL GAIN/PHASE (1/2 IS)
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FIGURE 42. VOLTAGE AND CURRENT NOISE vs FREQUENCY
FN6173.4
May 1, 2015
ISL1532
Typical Performance Curves (Continued)
POWER DISSIPATION (W)
4
3.571W
3.5
HTSSOP20
JA= +35°C/W
3.378W
3
2.5
QFN24
JA= 37°C/W
2
1.5
1
0.5
0
1.2
POWER DISSIPATION (W)
4.5
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD - QFN AND HTSSOP
EXPOSED DIEPAD SOLDERED TO PCB PER JESD51-5
25
75 85 100
50
125
AMBIENT TEMPERATURE (°C)
FIGURE 43. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
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13
150
1.000W
1
HTSSOP20
JA= 125°C/W
0.8 893mW
0.6
QFN24
JA= 140°C/W
0.4
0.2
0
0
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 44. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FN6173.4
May 1, 2015
ISL1532
Applications Information
TABLE 1. POWER MODES OF THE ISL1532
The ISL1532 consists of two sets of high-power line driver
amplifiers that can be connected for full duplex differential
line transmission. The amplifiers are designed to be used with
signals up to 10MHz and produce low distortion levels. The
ISL1532 has been optimized as a line driver for ADSL2+ CO
application. The driver output stage has been sized to provide
full ADSL2+ CO power level of 20dBM onto the telephone lines.
Realizing that the actual peak output voltages and currents
vary with the line transformer turns ratio, the ISL1532 is
designed to support 450mA of output current, which exceeds
the level required for 1:2 transformer ratio. A typical ADSL2+
interface circuit is shown in Figure 45. Each amplifier has
identical positive gain connections and optimum
common-mode rejection occurs. Further, DC input errors are
duplicated and create common-mode rather than differential
line errors.
DRIVER
INPUT +
+
-
ROUT
LINE +
RLINE
RF
ROUT
+
LINE RF
RECEIVE
OUT +
RECEIVE
OUT -
RECEIVE
AMPLIFIERS
+
+
RF
C0
0
0
IS Full Power Mode
0
1
3/4 IS Power Mode
1
0
1/2 IS Power Mode
1
1
Power-down
OPERATION
Another method for controlling the power consumption of the
ISL1532 is to connect a resistor from the IADJ pin to ground.
When the IADJ pin is grounded (the normal state), the supply
current per channel is as per the Electrical Specifications table
on page 3. When a resistor is inserted, the supply current is
scaled according to the “RSET vs IS” graphs in the Performance
Curves section.
Both methods of power control can be used simultaneously. In
this case, positive and negative supply currents (per amp) are
given by Equation 1:
5.06mA
I S + = 0.34mA + ------------------------------------------------- x
1 +  R SET / 1300 
RF
2RG
DRIVER
INPUT -
C1
R
RIN
R
RIN
FIGURE 45. TYPICAL LINE INTERFACE CONNECTION
Input Connections
The ISL1532 amplifiers are somewhat sensitive to source
impedance. In particular, they do not like being driven by
inductive sources. More than 100nH of source impedance can
cause ringing or even oscillations. This inductance is
equivalent to about 4 inch of unshielded wiring, or 6 inch of
unterminated transmission line. Normal high frequency
construction obviates any such problem.
 3/4C 1 + 1/2C 0 - C 1  C 0  1/4 
-5.06mA
I S - = ------------------------------------------------- x
1 +  R SET / 1300 
 3/4C 1 + 1/2C 0 - C 1  C 0  1/4 
Power Supplies and Dissipation
Due to the high power drive capability of the ISL1532, much
attention needs to be paid to power dissipation. The power that
needs to be dissipated in the ISL1532 has two main
contributors. The first is the quiescent current dissipation. The
second is the dissipation of the output stage.
The quiescent power in the ISL1532 is not constant with
varying outputs. In reality, 50% of the total quiescent supply
current needed to power each driver is converted in to output
current. Therefore, in the Equation 2 we should subtract the
average output current, IO, or 1/2 IQ, whichever is the lowest.
We’ll call this term IX.
P Dquiescent = V S   I S - 2I X 
• VS is the supply voltage (VS+ to VS-)
• IS is the operating supply current (IS+ - IS-) / 2
The ISL1532 contains two forms of power control operation.
Two digital inputs, C0 and C1, can be used to control the supply
current of the ISL1532 drive amplifiers. C0 and C1 inputs are
designed to pull high initially. Floating these inputs will put the
device in disable mode.
• IX is the lesser of IO or 1/2 IQ
Submit Document Feedback
14
(EQ. 2)
Where:
Power Control Function
As the supply current is reduced, the ISL1532 will start to
exhibit slightly higher levels of distortion and the frequency
response will be limited. The four power modes of the ISL1532
are set up as shown in Table 1.
(EQ. 1)
The dissipation in the output stage has two main contributors.
Firstly, there is the average voltage drop across the output
transistor and second, the average output current. For minimal
power dissipation, the user should select the supply voltage and
the line transformer ratio accordingly. The supply voltage should
be kept as low as possible, while the transformer ratio should be
selected so that the peak voltage required from the ISL1532 is
close to the maximum available output swing. There is a trade
off, however, with the selection of transformer ratio. As the ratio
FN6173.4
May 1, 2015
ISL1532
is increased, the receive signal available to the receivers is
reduced.
The JA requirement needs to be calculated. This is done by
using Equations 6:
Once the user has selected the transformer ratio, the
dissipation in the output stages can be selected by using
Equations 3:
T JUNCT - T AMB
 JA = --------------------------------------------P DISS
VS
P Dtransistors = 2  I O   ------- - V O
 2

Where:
(EQ. 3)
Where:
(EQ. 6)
• TJUNCT is the maximum die temperature (+150°C)
• TAMB is the maximum ambient temperature (+85°C)
• VS is the supply voltage (VS+ to VS-)
• PDISS is the dissipation calculated above
• VO is the average output voltage per channel
• IO is the average output current per channel
• JA is the junction to ambient thermal resistance for the
package when mounted on the PCB
The overall power dissipation (PDISS) is obtained by summing
PDquiescent and PDtransistor.
150 - 85
 JA = ------------------------ = 52C/W
1247mW
Estimating Line Driver Power Dissipation in
ADSL2+ CO Applications
Figure 46 shows a typical ADSL CO line driver implementation.
The average line power requirement for the ADSL2+ CO
application is 20dBM (100mW) into a 100Ω line, which is
translated to 3.16VRMS line voltage. The ADSL2+ DMT peak to
average ratio (crest factor) of 5.3 implies peak voltage of
16.7V into the line. Using a differential drive configuration and
transformer coupling with standard back termination, a
transformer ratio of 1:1 is selected. With 1:1 transformer ratio,
the impedance across the driver side of the transformer is
100Ω, the average voltage is 3.16VRMA and the average
current is 31.6mA. The power dissipated in the ISL1532 is a
combination of the quiescent power and the output stage
power when driving the line:
P D = P quiescent + P output-  stage 
P D = V S   I S - 2I X  +  V S - 2  V OUT-  RMS    I OUT-  RMS 
(EQ. 4)
In the full power mode and with 1.5k RADJ resistor, the
ISL1532 consumes typically 2.7mA quiescent current per
amplifier and still able to maintain very low distortion. The
distortion results are shown in typical performance section on
page 6 of the data sheet. When driving a load, a large portion
(about 50%) of the quiescent current becomes output load
current. The total power dissipation per channel is shown by
Equations 5:
P D = 24   2.7mA  2  50%  + 2  31.6mA   12 - 3.16 
Where:
P D = 623mW
(EQ. 5)
TX+
From
AFE
2RG
VS+
RT
VSRF
50
+
-
0.22µF
VS+
RT
VSRF
50
+
-
TXFR
1:1
100
3k
1.5k
TX-
(EQ. 7)
0.22µF
3k
FIGURE 46. TYPICAL ADSL CO LINE DRIVER IMPLEMENTATION
PCB Layout Considerations for QFN and
HTSSOP Packages
The ISL1532 die is packaged in two thermally-efficient
packages: a 24 Ld QFN (leadless plastic) and 20 Ld HTSSOP
packages. Both have the thermal pads underneath the
package and can use PCB surface metal vias areas and
internal ground planes to spread heat away from the package.
The larger the PCB area, the lower the junction temperature of
the device will be. In ADSL applications, multiple layer circuit
boards with internal ground plane are generally used. 13mil
vias are recommended to connect the metal area under the
device with the internal ground plane. Examples of the PCB
layouts for the QFN and HTSSOP packages are shown in
Figures 47 and 48 respectively. +37°C/W (QFN package) and
+35°C/W (HTSSOP package) are obtained with the
ISL1532IVEZ-EVAL demoboard. The demoboard is a 4-layer
board built with 2oz. copper and has a dimension of 4in2.
TB389 shows the QFN package and layout recommendations.
If using the QFN package, the layout and manufacturing
process recommendations should be carefully reviewed.
The total power dissipation for dual channel is:
PDtotal
= 2 x PD
= 1247mW
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15
FN6173.4
May 1, 2015
ISL1532
Output Loading
While the drive amplifiers can output in excess of 500mA
transiently, the internal metallization is not designed to carry
more than 100mA of steady DC current and there is no current
limit mechanism. The device can safely drive RMS sinusoidal
currents of 2 x 100mA, or 200mA. This current is more than
that required to drive line impedances to large output levels,
but output short circuits cannot be tolerated. The series output
resistor will usually limit currents to safe values in the event of
line shorts. Driving lines with no series resistor is a serious
hazard.
TOP METAL
The amplifiers are sensitive to capacitive loading. More than
25pF will cause peaking of the frequency response. The same
is true of badly terminated lines connected without a series
matching resistor.
Power Supplies and Component Placement
INTERNAL GROUND PLANE
FIGURE 47. PCB LAYOUT - QFN PACKAGE
The power supplies should be well bypassed close to the
ISL1532. A 2.2µF tantalum capacitor and a 0.1µF ceramic
capacitor for each supply works well. Since the load currents
are differential, they should not travel through the board
copper and set up ground loops that can return to amplifier
inputs. Due to the class AB output stage design, these currents
have heavy harmonic content. If the ground terminal of the
positive and negative bypass capacitors are connected to each
other directly and then returned to circuit ground, no such
ground loops will occur. This scheme is employed in the layout
of the ISL1532 demonstration board and documentation can
be obtained from the factory.
The parallel combination of the feedback resistor and gain setting
resistor and parasitic capacitance on the inverting input node
forms a pole in the feedback path. If the frequency of this pole is
low, it can lead to frequency peaking. Since the ISL1532 is a
current feedback amplifier, the feedback resistor value is
predetermined by design. The only way to increase the frequency
of this pole is to reduce the parasitic capacitance on the inverting
input node. Ground plane near the inverting input should be
avoided to minimize the parasitic capacitance.
Single Supply Operation
TOP METAL
The ISL1532 can also be powered from a single supply
voltage. When operating in this mode, the GND pins can still be
connected directly to GND and the C0 and C1 pins are relative
to GND. To calculate power dissipation, the equations in the
previous section should be used, with VS equal to half the
supply rail.
Feedback Resistor Value
The bandwidth and peaking of the amplifiers varies with
supply voltage somewhat and with gain settings. The feedback
resistor values can be adjusted to produce an optimal
frequency response. Here is a series of resistor values that
produce an optimal driver frequency response (1dB peaking)
for different supply voltages and gains.
INTERNAL GROUND PLANE
FIGURE 48. PCB LAYOUT - HTSSOP PACKAGE
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16
FN6173.4
May 1, 2015
ISL1532
TABLE 2. OPTIMUM DRIVER FEEDBACK RESISTOR FOR VARIOUS
GAINS AND SUPPLY VOLTAGES
DRIVER VOLTAGE GAIN
SUPPLY VOLTAGE
5
10
±12V
4k
3k
The ISL1532 features improved frequency compensation for all
power modes and applications, allowing stable operation at very
low power levels and eliminating any need for external “snubber”
circuits. Differential circuits, such as ADSL2+ line driver
applications, can be especially prone to common-mode
oscillation. The ISL1532 is specifically compensated to eliminate
this type of instability and allow for reliable operation even at
very low power levels.
Cable Termination Techniques
RL
K = -------------RBM
(EQ. 8)
RG
+
VIN
RP1
RG
VIN
ZL
FIGURE 49. TRADITIONAL CABLE TERMINATION TECHNIQUE
While functional, this passive termination circuit has some
disadvantages. The output impedance of the driver, while small,
can be a noticeable quantity. The backmatch resistor is
necessary to properly terminate the source end of a transmission
line such as a twisted pair, but now the voltage delivered to the
load is split between that backmatch resistance and the load
resistance. Since there is a required voltage level at the load, the
driver must now produce twice the voltage swing. The voltage
swing and power dissipation increases. The power burned in the
backmatch resistor is lost as heat, which causes the total power
dissipation to double. There also is quiescent power used in the
op amp.
An alternative technique of cable termination using positive
feedback is shown in Figure 50. With negative feedback already
in place to set the gain, positive feedback can be used to adjust
the output impedance. Lowering the backmatch resistor without
compromising the total source termination impedance relaxes
the output and supply voltage requirement for the amplifier and
reduces the overall power dissipation. RP1 and RP2 are the only
additions to the passive circuit and provide the positive feedback
for the amplifier. This feedback synthesizes larger output
17
VO
RF
RBM
RP2
VX
IX
VO
RL
RL
VO
RF  


--------=  1 + --------   --------------------------
V IN
R
R
+
R

G  BM
L
Submit Document Feedback
ZL
RL
RP2
+
RP1
RBM
RBM
The stability of the amplifier and the physical backmatch
resistance tolerance typically limit K to around 4 or 5. The output
impedance of the amplifier is increased by the positive feedback,
allowing the backmatch resistance to decrease keeping the total
source impedance constant.
RF
+
RF
FIGURE 50. ACTIVE TERMINATION TECHNIQUE
The traditional circuit for a line driver with passive termination is
shown in Figure 49. RBM is the backmatch resistance added for
proper termination at the source. This backmatch resistance is
typically equal to the value of the cable line characteristic
impedance and the load impedance. The output impedance of
the amplifier is negligible in comparison with the value of the
backmatch resistor it appears in series with. The gain equation
reflects the output voltage across the load resistance with
respect to the input voltage.
RG
impedance for the amplifier, allowing a reduction of the
backmatch resistance. For convenience, a factor K is being
introduced. It is the ratio between the backmatch resistance and
the physical backmatch resistor.
FIGURE 51. MEASURING OUTPUT IMPEDANCE
Figure 51 shows a standard method for measuring the output
impedance of any circuit. Ohm's law applies, therefore a
measured voltage (VX) applied to a node divided by the test
current gives the impedance seen at that node. Ideal op amp
simplifications (input terminals are at the same voltage and
there is no current flowing into the inputs) RP2 is assumed much
larger than the RBM so the current through the positive feedback
loop can be neglected. The voltage at the input terminals is given
by a resistive divider of the output voltage on either side of the
backmatch resistor. These feedback resistors alter the output
resistance for the op amp, allowing reduction in the backmatch
resistance. The derivations are as follows:
R P1
V+ = -----------------------------  V X
R P1 + R P2
RG
V- = ----------------------  V O
RF + RG
R F + R G
VX
R P1

R SOURCE = ------- = R BM /  1 - -----------------------------  ----------------------
IX
R
+
R
RG 

P1
P2
R SOURCE = R L = K  RBM
R P1   R F + R G

K = 1  1 -  -----------------------------   ----------------------
R
 P1 + R P2  R G 
(EQ. 9)
FN6173.4
May 1, 2015
ISL1532
The overall gain of the active termination circuit is:
R P2 /  R P2 + R P1 
 VO 
 --------- = ----------------------------------------------------------------------------------------------V
R P1 
 IN
G + R F 
1  R
 1 + --- /  ---------------------- -  -----------------------------


K  R
 R + R 
G
VIN+
+
-
P2
P1
(EQ. 10)
RBM
VO+
RF
R
P
RG
RG
VIN-
RL
RP
RF
+
RBM
TABLE 3.
VO-
PASSIVE TERMINATION
FIGURE 52. DIFFERENTIAL LINE DRIVER USING ACTIVE
TERMINATION TECHNIQUE
In an ADSL2+ system, the POTS phone line, a twisted pair cable
is used for data transmission. As shown in Figure 52, the
single-ended active terminate line driver is reconfigured to drive
differential lines. The gain resistor is shared to allow accurate
gain matching between the two amplifiers. Applying the same
analysis technique as the single-ended circuit, the following
relationship can be derived:
R F

K = 1 /  1 - --------
R P

1 + RF / RG + RF / RP
 V OUT
 ---------------- = -----------------------------------------------------------V
R F
 IN 

2   1 - --------
R P

Submit Document Feedback
18
Table 3 is a quick comparison of the reduction in voltage and
power requirements for the driver with passive or active
termination. The key specification of a ADSL2+ CO driver are as
follows: Peak output line power is 20dBM, POTS line impedance
is 100Ω and the crest factor for ADSL DMT signal is 14.5dB. This
specification translates to 16.76Vp-p voltage on the line with 5.3
Peak To Average Ratio (PAR) and 31.6mA average output
current. In the passive termination case where the load and
backmatch resistors are the same, the amplifier must provide
33.52Vp-p at its outputs. A high voltage line driver typically needs
4V of total headroom. As a result, the total supply voltage
required is 37.5V. With the necessary output average current,
that translates into 1.185W dissipated in addition to the
quiescent power of the amplifier.
(EQ. 11)
ACTIVE TERMINATION
16.5VP-P into a 100Ω line
16.5VP-P into a 100Ω line
VOUT DRIVER = VRBM + VRLOAD
VOUT DRIVER = VRBM + VRLOAD
RBM = RLOAD
RBM = RLOAD/5
VRBM = VRLOAD
VRBM = VRLOAD/5
VOUT DRIVER = 33.52V
VOUT DRIVER = 20.11V
VSUPPLY = 37.52
VSUPPLY = 24.11
IOUT = 31.6mA
IOUT = 31.6mA
POUT DRIVER = VSUPPLY
* IOUT = 1.185W (plus quiescent
power)
POUT DRIVER = VSUPPLY
* IOUT = 0.714W (plus quiescent
power)
In the active case, a K of 5 is assumed. This reduces the
backmatch resistor to 20% of its value in the passive case. The
peak-to-peak output voltage provided by the driver is reduced to
20.11V which allows the use of the EL1508, a median voltage
line driver. The EL1508 requires 2.5V of headroom. With 2.5V of
supply voltage headroom, the power supply required becomes
22.61. With the same output current drive, the power dissipation
is reduced by 39.7% to 0.714W. While it is true that additional
power is dissipated in the feedback networks, the feedback
resistors are typically much larger than the backmatch resistor
and their losses are negligible.
FN6173.4
May 1, 2015
ISL1532
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE
REVISION
May 1, 2015
FN6173.4
CHANGE
- Updated entire datasheet to Intersil new standard.
- Added revision history and about Intersil verbiage
- Updated Figure 52: switched the inverting (-) and no inverting (+) inputs for both op amps.
-Updated the Package Outline Drawing on page 19 and 20 to the latest revision:
MDP0046- added “MILLIMETERS” to table.
MDP0048- added “MILLIMETERS” to table.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
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For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
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without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
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For information regarding Intersil Corporation and its products, see www.intersil.com
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19
FN6173.4
May 1, 2015
ISL1532
QFN (Quad Flat No-Lead) Package Family
MDP0046
QFN (QUAD FLAT NO-LEAD) PACKAGE FAMILY
(COMPLIANT TO JEDEC MO-220)
A
MILLIMETERS
D
N
(N-1)
(N-2)
B
1
2
3
PIN #1
I.D. MARK
E
(N/2)
2X
0.075 C
2X
0.075 C
N LEADS
TOP VIEW
0.10 M C A B
(N-2)
(N-1)
N
b
L
SYMBOL QFN44 QFN38
TOLERANCE
NOTES
A
0.90
0.90
0.90
0.90
±0.10
-
A1
0.02
0.02
0.02
0.02
+0.03/-0.02
-
b
0.25
0.25
0.23
0.22
±0.02
-
c
0.20
0.20
0.20
0.20
Reference
-
D
7.00
5.00
8.00
5.00
Basic
-
Reference
8
Basic
-
Reference
8
Basic
-
D2
5.10
3.80
5.80 3.60/2.48
E
7.00
7.00
8.00
1
2
3
6.00
E2
5.10
5.80
5.80 4.60/3.40
e
0.50
0.50
0.80
0.50
L
0.55
0.40
0.53
0.50
±0.05
-
N
44
38
32
32
Reference
4
ND
11
7
8
7
Reference
6
NE
11
12
8
9
Reference
5
MILLIMETERS
PIN #1 I.D.
3
QFN32
SYMBOL QFN28 QFN24
QFN20
QFN16
A
0.90
0.90
0.90
0.90
0.90
±0.10
-
A1
0.02
0.02
0.02
0.02
0.02
+0.03/
-0.02
-
b
0.25
0.25
0.30
0.25
0.33
±0.02
-
c
0.20
0.20
0.20
0.20
0.20
Reference
-
D
4.00
4.00
5.00
4.00
4.00
Basic
-
D2
2.65
2.80
3.70
2.70
2.40
Reference
-
(E2)
(N/2)
NE 5
7
(D2)
BOTTOM VIEW
0.10 C
e
C
SEATING
PLANE
TOLERANCE NOTES
E
5.00
5.00
5.00
4.00
4.00
Basic
-
E2
3.65
3.80
3.70
2.70
2.40
Reference
-
e
0.50
0.50
0.65
0.50
0.65
Basic
-
L
0.40
0.40
0.40
0.40
0.60
±0.05
-
N
28
24
20
20
16
Reference
4
ND
6
5
5
5
4
Reference
6
NE
8
7
5
5
4
Reference
5
Rev 11 2/07
0.08 C
N LEADS
& EXPOSED PAD
SEE DETAIL "X"
NOTES:
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Tiebar view shown is a non-functional feature.
SIDE VIEW
3. Bottom-side pin #1 I.D. is a diepad chamfer as shown.
4. N is the total number of terminals on the device.
(c)
C
5. NE is the number of terminals on the “E” side of the package
(or Y-direction).
2
A
(L)
A1
N LEADS
DETAIL X
Submit Document Feedback
6. ND is the number of terminals on the “D” side of the package
(or X-direction). ND = (N/2)-NE.
7. Inward end of terminal may be square or circular in shape with radius
(b/2) as shown.
8. If two values are listed, multiple exposed pad options are available.
Refer to device-specific datasheet.
20
FN6173.4
May 1, 2015
ISL1532
HTSSOP (Heat-Sink TSSOP) Family
0.25 M C A B
D
MDP0048
A
HTSSOP (HEAT-SINK TSSOP) FAMILY
(N/2)+1
N
MILLIMETERS
SYMBOL 14 LD 20 LD 24 LD 28 LD 38 LD TOLERANCE
PIN #1 I.D.
E
E1
0.20 C B A
1
2X
N/2 LEAD TIPS
(N/2)
TOP VIEW
B
D1
EXPOSED
THERMAL PAD
E2
A
1.20
1.20
1.20
1.20
1.20
Max
A1
0.075
0.075
0.075
0.075
0.075
±0.075
A2
0.90
0.90
0.90
0.90
0.90
+0.15/-0.10
b
0.25
0.25
0.25
0.25
0.22
+0.05/-0.06
c
0.15
0.15
0.15
0.15
0.15
+0.05/-0.06
D
5.00
6.50
7.80
9.70
9.70
±0.10
D1
3.2
4.2
4.3
5.0
7.25
Reference
E
6.40
6.40
6.40
6.40
6.40
Basic
E1
4.40
4.40
4.40
4.40
4.40
±0.10
E2
3.0
3.0
3.0
3.0
3.0
Reference
e
0.65
0.65
0.65
0.65
0.50
Basic
L
0.60
0.60
0.60
0.60
0.60
±0.15
L1
1.00
1.00
1.00
1.00
1.00
Reference
N
14
20
24
28
38
Reference
BOTTOM VIEW
Rev. 3 2/07
NOTES:
0.05
e
C
H
1. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15mm per side.
2. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm per
side.
SEATING
PLANE
3. Dimensions “D” and “E1” are measured at Datum Plane H.
0.10 M C A B
b
0.10 C
N LEADS
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
SIDE VIEW
SEE DETAIL “X”
c
END VIEW
L1
A A2
GAUGE
PLANE
0.25
L
A1
0° - 8°
DETAIL X
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21
FN6173.4
May 1, 2015
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