DATASHEET

ISL5585
®
Data Sheet
October 21, 2004
3.3V Ringing SLIC Family for Voice Over
Broadband (VOB)
Features
• 3.3V Operation
The 3.3V family of ringing subscriber line interface circuits
(SLIC) supports analog Plain Old Telephone Service (POTS)
in short and medium loop length, wireless and wireline voice
over broadband applications. Ideally suited for customer
premise equipment, this family of products offers flexibility to
designers with high ringing voltage and low power
consumption system requirements.
The ISL5585 family is capable of operating with 100V ringing
battery supply, which translates directly to the amount of
ringing voltage supplied to the subscriber. With the high
operating voltage, subscriber loop lengths can be extended
to 500Ω (i.e., 5,000 feet) and beyond, allowing this family to
serve emerging Fiber In The Loop (FITL) markets.
Other key features across the product family include: 3.3V
VCC operation, low power consumption, ringing using
sinusoidal or trapezoidal waveforms, robust auto-detection
mechanisms for when subscribers go on or off hook, and
minimal external discrete application components.
Integrated test access features are also offered on selected
products to support loopback testing as well as line
measurement tests.
• Onboard Ringing Generation
• Low Standby Power Consumption (75V, 65mW)
• Programmable Transient Current Limit
• Improved Off Hook Software Interface
• Integrated MTU DC Characteristics
• Low External Component Count
• Silent Polarity Reversal
• Pulse Metering and On Hook Transmission
• Tip Open Ground Start Operation
• Balanced and Unbalanced Ringing
• Thermal Shutdown with Alarm Indicator
• 28 Lead Surface Mount Packaging
• QFN Package:
- Compliant to JEDEC PUB95 MO-220
QFN - Quad Flat No Leads - Package Outline
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
There are ten product offerings of the ISL5585 providing
various grades of ringing battery voltage and longitudinal
balance.
• Pb-Free Available (RoHS Compliant)
Block Diagram
• Short Loop Access Platforms
POL
CDC
VBL
FN6026.6
Applications
• Voice Over Internet Protocol (VoIP)
VBH
• Voice Over Cable and DSL Modems
ILIM
DC
CONTROL
BATTERY
SWITCH
RINGING
PORT
VRS
• Internet Protocol PBX
• FiberTo The Home (FTTH)
TIP
RING
TL
SW+
SW-
• Remote Subscriber Units
2-WIRE
PORT
TRANSIENT
CURRENT
LIMIT
TEST
ACCESS
TRANSMIT
SENSING
AUX
VTX
-IN
VFB
4-WIRE
PORT
• Ethernet Terminal Adapters
Related Literature
• AN1038, User’s Guide for Development Board
DETECTOR
LOGIC
RT SH E0 DET ALM
1
F2
F1
F0
CONTROL
LOGIC
BSEL SWC
• AN9824, Modeling of the AC Loop
• TB379 Thermal Characterization of Packages for ICs
• AN9922, Thermal Characterization and Modeling of the
RSLIC18 in the Micro Leadframe Package
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2002-2004. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
ISL5585
Ordering Information
HIGH BATTERY (VBH)
PART NUMBER
100V
85V
75V
LONGITUDINAL
BALANCE
58dB
53dB
FULL
TEST
TEMP.
RANGE (°C)
PACKAGE
PKG. DWG. #
ISL5585AIM
•
•
•
-40 to 85
28 Ld PLCC
N28.45
ISL5585AIMZ
(See Note)
•
•
•
-40 to 85
28 Ld PLCC
(Pb-free)
N28.45
ISL5585BIM
•
•
•
-40 to 85
28 Ld PLCC
N28.45
ISL5585BIMZ
(See Note)
•
•
•
-40 to 85
28 Ld PLCC
(Pb-free)
N28.45
ISL5585CIM
•
•
•
-40 to 85
28 Ld PLCC
N28.45
ISL5585CIMZ
(See Note)
•
•
•
-40 to 85
28 Ld PLCC
(Pb-free)
N28.45
ISL5585DIM
•
•
•
-40 to 85
28 Ld PLCC
N28.45
ISL5585DIMZ
(See Note)
•
•
•
-40 to 85
28 Ld PLCC
(Pb-free)
N28.45
ISL5585ECM
•
•
0 to 75
28 Ld PLCC
N28.45
ISL5585ECMZ
(See Note)
•
•
0 to 75
28 Ld PLCC
(Pb-free)
N28.45
ISL5585ECR
•
•
0 to 75
32 Pad QFN
L32.7x7*
ISL5585ECRZ
(See Note)
•
•
0 to 75
32 Pad QFN
(Pb-free)
L32.7x7*
ISL5585FCM
•
•
•
0 to 85
28 Ld PLCC
N28.45
ISL5585FCMZ
(See Note)
•
•
•
0 to 85
28 Ld PLCC
(Pb-free)
N28.45
ISL5585FCR
•
•
•
0 to 85
32 Pad QFN
L32.7x7*
ISL5585FCRZ
(See Note)
•
•
•
0 to 85
32 Pad QFN
(Pb-free)
L32.7x7*
ISL5585GCM
•
•
•
0 to 85
28 Ld PLCC
N28.45
ISL5585GCMZ
(See Note)
•
•
•
0 to 85
28 Ld PLCC
(Pb-free)
N28.45
ISL5585GCR
•
•
•
0 to 85
32 pad QFN
L32.7x7*
ISL5585GCRZ
(See Note)
•
•
•
0 to 85
32 pad QFN
(Pb-free)
L32.7x7*
ISL5585 XXX
Evaluation board platform, including CODEC.
Also available in Tape and Reel
*Reference “Special Considerations for the QFN Package” text.
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination
finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pbfree peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020C.
2
ISL5585
Device Operating Modes
MODE
F2
F1
F0
E0 = 1 E0 = 0 ISL5585A
ISL5585B
ISL5585C ISL5585D ISL5585E ISL5585F
ISL5585G
Low Power Standby
0
0
0
SHD
GKD
•
•
•
•
•
•
•
Forward Active
0
0
1
SHD
GKD
•
•
•
•
•
•
•
Unbalanced Ringing
0
1
0
RTD
RTD
Reverse Active
0
1
1
SHD
GKD
•
•
•
•
•
•
•
Ringing
1
0
0
RTD
RTD
•
•
•
•
•
•
•
Forward Loop Back
1
0
1
SHD
GKD
•
•
•
•
•
•
Tip Open
1
1
0
SHD
GKD
•
•
•
•
•
•
Power Denial
1
1
1
n/a
n/a
•
•
•
•
•
•
•
Pinouts
•
26
SH
ILIM
27
SCC
SH
28
RING
RING
1
NC
TIP
2
TIP
BGND
3
BGND
VBL
4
VBL
VBH
ISL5585 (PLCC)
TOP VIEW
VBH
ISL5585 QFN
TOP VIEW
32
31
30
29
28
27
26
25
SW+
1
24 ILIM
SW-
2
23 RT
SWC
3
22 CDC
F2
4
21 VCC
F1
5
20 -IN
-IN
F1
9
21
VFB
F0
6
19 VFB
F0
10
20
VTX
E0
7
18 VTX
E0
11
19
AUX
NC
8
17 AUX
12
13
14
15
16
17
18
9
10
11
12
13
14
15
16
NC
22
VRS
8
POL
F2
TL
VCC
BSEL
23
AGND
7
ALM
SWC
DET
CDC
VRS
24
POL
6
TL
SW-
BSEL
RT
AGND
25
ALM
5
DET
SW+
Pin Description
PLCC
QFN
SYMBOL
DESCRIPTION
1
29
TIP
2
30
BGND
3
31
VBL
Low battery supply connection.
4
32
VBH
High battery supply connection for the most negative battery.
5
1
SW+
Uncommitted switch positive terminal.
6
2
SW-
Uncommitted switch negative terminal.
7
3
SWC
Switch control input. This TTL compatible input controls the uncommitted switch, with a logic “0” enabling the switch
and logic “1” disabling the switch.
8
4
F2
Mode Control Input - MSB. F2-F0 for the TTL compatible parallel control interface for controlling the various modes of
operation of the device.
9
5
F1
Mode control input.
TIP power amplifier output.
Battery Ground - To be connected to zero potential. All loop current and longitudinal current flow from this ground.
Internally separate from AGND. This ground must be connected to the same potential as AGND.
3
ISL5585
Pin Description
(Continued)
PLCC
QFN
SYMBOL
DESCRIPTION
10
6
F0
Mode control input.
11
7
E0
Detector Output Selection Input. This TTL input controls the multiplexing of the SHD (E0 = 1) and GKD (E0 = 0)
comparator outputs to the DET output based upon the state at the F2-F0 pins (see the Device Operating Modes table
shown on page 2).
12
9
DET
Detector Output - This TTL output provides on-hook/off-hook status of the loop based upon the selected operating
mode. The detected output will either be switch hook, ground key or ring trip (see the Device Operating Modes table
shown on page 2). DET will be latched low following a ring trip. Unlatching the DET pin is accomplished by changing
logic state.
13
10
ALM
Thermal Shutdown Alarm. This pin signals the internal die temperature has exceeded safe operating temperature
(approximately 175°C) and the device has been powered down automatically.
14
11
AGND
Analog ground reference. This pin should be externally connected to BGND.
15
12
BSEL
Selects between high and low battery, with a logic “1” selecting the high battery and logic “0” the low battery.
16
13
TL
17
14
POL
External capacitor on this pin sets the polarity reversal time.
18
15
VRS
Ringing Signal Input - Analog input for driving 2-wire interface while in Ring Mode.
19
17
AUX
Auxiliary input - Float if not used.
20
18
VTX
Transmit Output Voltage - Output of impedance matching amplifier, AC couples through a resistor to CODEC.
21
19
VFB
Feedback voltage for impedance matching. This voltage is scaled to accomplish impedance matching. The CFB
capacitor connects between this pin and the -IN pin. The CFB cap needs to be non-polarized for proper device
operation in the Reverse Active mode. Ceramic surface mount capacitors (1206 body style) are available from
Panasonic with a 6.3V voltage rating. These can be used for CFB since it is internally limited to approximately ±3V.
22
20
-IN
Analog Receive Voltage - 4-wire analog audio input voltage. connects to CODEC via receive gain setting resistor RIN
(see Figure 18). Resistor RIN needs to be as close to the -IN pin as possible to minimize parasitic capacitance.
23
21
VCC
Positive voltage power supply,+3.3V
24
22
CDC
DC Biasing Filter Capacitor - Connects between this pin and VCC.The CDC capacitor may be either polarized or non
polarized with a 6.3V voltage rating.
25
23
RT
Ring trip filter network.
26
24
ILIM
Loop Current Limit programming resistor.
27
25
SH
Switch hook detection threshold programming resistor.
---
26
SCC
Substrate Common Connection - Connect this pin to VBH Supply. This pin is used to connect the substrate of the die
and the thermal heatsink plane of the QFN package.
28
27
RING
RING power amplifier output.
Programming pin for the transient current limit feature, set by an external resistor to ground.
4
ISL5585
Absolute Maximum Ratings TA = 25°C
Thermal Information
Maximum Supply Voltages
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V
VCC - VBH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110V
Uncommitted Switch Voltage . . . . . . . . . . . . . . . . . . . . . . . -110V
Maximum Tip/Ring Negative Voltage Pulse (Note 8). . . . . . . VBH -15V
Maximum Tip/Ring Positive Voltage Pulse (Note 8) . . . . . . . . . . . .+8V
ESD (Human Body Model). . . . . . . . . . . . . . . . . . . . . . . . . . . 1000V
Thermal Resistance (Typical)
θJA (°C/W)
θJC (°C/W)
PLCC (Note 1) . . . . . . . . . . . . . . . . . . .
55
N/A
QFN (Note 2) . . . . . . . . . . . . . . . . . . . .
28
1
Maximum Junction Temperature Plastic . . . . . . . . . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
(PLCC - Lead Tips Only)
For Recommended soldering conditions see Tech Brief TB389.
Operating Conditions
Temperature Range
Commercial (C suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 85°C
Industrial (I suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C
Positive Power Supply (VCC) . . . . . . . . . . . . . . . . . . . . +3.3V ±10%
Low Battery Power Supply (VBL) . . . . . . . . . . . . . -16V to -52V, ±5%
High Battery Power Supply (VBH)
ISL5585AIM, CIM, GCM, GCR . . . . . . . . . . . . . . .VBL to 100V, ±5%
ISL5585BIM, DIM. . . . . . . . . . . . . . . . . . . . . . . . VBL to -85V, ±10%
ISL5585ECM, ECR, FCM, FCR. . . . . . . . . . . . . VBL to -75V, ±10%
Uncommitted Switch (loop back or relay driver). . . . . . +5V to -100V
Die Characteristics
Substrate Potential. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VBH
Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bipolar-DI
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. θJC, the
“case temp” is measured at the center of the exposed metal pad on the package underside. See Tech Brief TB379.
Electrical Specifications
Unless Otherwise Specified, TA = -40°C to 85°C for industrial (I) grade and TA = 0°C to 85°C for commercial (C)
grade, VBL = -24V, VBH = -100V, -85V or -75V, VCC = +3.3V, AGND = BGND = 0V, loop current limit = 25mA. All
AC transmission parameters are specified at 600W 2-wire terminating impedance over the frequency band of
300Hz to 3.4kHz. Protection resistors = 0W.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
450
-
-
kΩ
Balanced Ringing, VRS to 2-Wire, RLOAD=∞
78
80
82
V/V
Unbalanced Ringing, VRS to 2-Wire, RLOAD=∞
38
40
42
V/V
Tip, Referenced to VBH/2 + 0.5 (Note 9)
-
± 2.5
-
V
Ring, Referenced to VBH/2 + 0.5
-
± 2.5
-
V
Balanced Ringing, VRS Input=0.840VRMS
-
67
-
VRMS
Unbalanced Ringing, VRS Input=0.840VRMS
-
33.5
-
VRMS
Ringing Voltage Total Distortion
RL=1.3 kΩ, VT-R=|VBH| -5
-
-
4.0
%
4-Wire to 2-Wire Ringing Off Isolation
Active Mode, Referenced to VRS Input
-
90
-
dB
2-Wire to 4-Wire Transmit Isolation
Ringing Mode Referenced to the Differential Ringing
Amplitude
-
80
-
dB
160
-
-
kΩ
-
-
1
Ω
RINGING PARAMETERS
VRS Input Impedance (Note 3)
Differential Ringing Gain (Note 4)
Centering Voltage Accuracy
Open Circuit Ringing Voltage
AC TRANSMISSION PARAMETERS
Auxiliary Input Impedance (Note 3)
Transmit Output Impedance (Note 3)
4-Wire Port Overload Level
THD=1%
-
1.0
-
VPK
2-Wire Port Overload Level
THD=1%
3.1
3.5
-
VPK
5
ISL5585
Electrical Specifications
Unless Otherwise Specified, TA = -40°C to 85°C for industrial (I) grade and TA = 0°C to 85°C for commercial (C)
grade, VBL = -24V, VBH = -100V, -85V or -75V, VCC = +3.3V, AGND = BGND = 0V, loop current limit = 25mA. All
AC transmission parameters are specified at 600W 2-wire terminating impedance over the frequency band of
300Hz to 3.4kHz. Protection resistors = 0W. (Continued)
PARAMETER
TEST CONDITIONS
2-Wire Return Loss
MIN
TYP
MAX
UNITS
300Hz
-
24
-
dB
1kHz
-
40
-
3.4kHz
-
21
-
dB
1
dB
2-Wire Longitudinal Balance (Notes 5, 6)
300Hz to 1kHz
Forward Active, Grade A and B
58
62
-
dB
Forward Active, Grade C, D and E
53
59
-
dB
2-Wire Longitudinal Balance (Notes 5, 6)
1kHz to 3.4kHz
Forward Active, Grade A and B
54
58
-
dB
Forward Active, Grade C, D and E
53
58
-
dB
4-Wire Longitudinal Balance (Notes 5, 6)
300Hz to 1kHz
Forward Active, Grade A and B
58
67
-
dB
Forward Active, Grade C, D and E
53
64
-
dB
4-Wire Longitudinal Balance (Notes 5, 6)
1kHz to 3.4kHz
Forward Active, Grade A and B
54
66
-
dB
Forward Active, Grade C, D and E
53
63
-
dB
2-Wire to 4-Wire Level Linearity
4-Wire to 2-Wire Level Linearity
Referenced to -10dBm
+3 to -40dBm, 1kHz
-
±0.025
-
dB
-40 to -50dBm, 1kHz
-
±0.050
-
dB
-50 to -55dBm, 1kHz
-
±0.100
-
dB
20
-
-
mARMS
4-Wire to 2-Wire Insertion Loss
-0.20
0.00
+0.20
dB
2-Wire to 4-Wire Insertion Loss
-6.22
-6.02
-5.82
dB
4-Wire to 4-Wire Insertion Loss
-6.22
-6.02
-5.82
dB
Forward Active Idle Channel Noise (Note 6) 2-Wire C-Message, T=25°C
-
10
13
dBrnC
4-Wire C-Message, T=25°C
-
4
7
dBrnC
Reverse Active Idle Channel Noise (Note 6) 2-Wire C-Message, T=25°C
-
10
13
dBrnC
4-Wire C-Message, T=25°C
-
4
7
dBrnC
-8.5
-
+8.5
%
Programming Range
15
-
45
mA
Programming Accuracy (1% programming resistor)
-20
-
+20
%
Programming Range
40
-
100
mA
Loop Current During Low Power Standby
Forward Polarity Only
18
-
26
mA
Open Circuit Voltage (|Tip - Ring|)
VBL=-16V
-
8.0
-
VDC
VBL=-24V
14
15.5
17
VDC
VBH > -60V
43
49
-
VDC
-
44.5
-
VDC
43
51.5
-
VDC
Longitudinal Current Capability Per Wire
(Note 3)
OHT, Active
DC PARAMETERS
Off Hook Loop Current Limit
Programming Accuracy(1% programming resistor)
Off Hook Transient Current Limit
Low Power Standby, Open Circuit Voltage
(Tip - Ring)
VBL=-48V
Absolute Open Circuit Voltage
VRG in LPS and FA; VTG in RA; VBH > -60V
-
-53
-56
VDC
IOL=45mA
-
0.20
0.60
V
-
-
52
V
VBH > -60V
TEST ACCESS FUNCTIONS
Switch On Voltage
Loopback Max Battery (VBL or VBH)
6
ISL5585
Electrical Specifications
Unless Otherwise Specified, TA = -40°C to 85°C for industrial (I) grade and TA = 0°C to 85°C for commercial (C)
grade, VBL = -24V, VBH = -100V, -85V or -75V, VCC = +3.3V, AGND = BGND = 0V, loop current limit = 25mA. All
AC transmission parameters are specified at 600W 2-wire terminating impedance over the frequency band of
300Hz to 3.4kHz. Protection resistors = 0W. (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
5
-
15
mA
-10
-
+10
%
-
1.0
-
%
1.12
1.25
1.37
V
-10
-
+10
%
Ground Key Threshold
-
12
-
mA
E0 Transition, DET Output Delay
-
20
-
µs
-
175
-
°C
Input Low Voltage
-
-
0.8
V
Input High Voltage
2.0
-
-
V
LOOP DETECTORS AND SUPERVISORY FUNCTIONS
Switch Hook Programming Range
Switch Hook Programming Accuracy
(1% programming resistor)
Dial Pulse Distortion
Ring Trip Comparator Threshold
Ring Trip Programming Current Accuracy
Thermal Alarm Output
(1% programming resistor)
IC Junction Temperature
LOGIC INPUTS (F0, F1, F2, E0, SWC, BSEL)
Input Low Current
VIL=0.4V
-20
-10
-
µA
Input High Current
VIH=2.4V
-
-
1
µA
Output Low Voltage
IOL=1mA
-
.15
0.4
V
Output High Voltage
IOH=100µA
2.4
2.8
-
V
ICC
-
3.9
6.0
mA
IBH
-
0.66
0.90
mA
ICC
-
4.9
6.5
mA
IBL
-
1.2
2.5
mA
ICC
-
7.0
9.5
mA
IBL
-
0.9
2.0
mA
IBH
-
2.2
3.0
mA
ICC
-
6.4
9.0
mA
IBL
-
1.0
1.3
mA
IBH
-
2.0
3.0
mA
Ringing, BSEL=1 (Unbalanced Ringing, 010) ICC
-
9.3
9.0
mA
IBL
-
1.0
1.3
mA
IBH
-
2.4
3.0
mA
ICC
-
10.3
13.5
mA
IBL
-
23.5
32
mA
ICC
-
3.8
5.5
mA
IBL
-
0.4
1.0
mA
IBH
-
0.6
1.0
mA
LOGIC OUTPUTS (DET, ALM)
SUPPLY CURRENTS
Low Power Standby, BSEL=1
Forward or Reverse Active, BSEL=0
Forward Active, BSEL=1
Ringing, BSEL=1 (Balanced Ringing, 100)
Forward Loopback, BSEL=0
Tip Open, BSEL=1
7
ISL5585
Electrical Specifications
Unless Otherwise Specified, TA = -40°C to 85°C for industrial (I) grade and TA = 0°C to 85°C for commercial (C)
grade, VBL = -24V, VBH = -100V, -85V or -75V, VCC = +3.3V, AGND = BGND = 0V, loop current limit = 25mA. All
AC transmission parameters are specified at 600W 2-wire terminating impedance over the frequency band of
300Hz to 3.4kHz. Protection resistors = 0W. (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ICC
-
4.0
6.0
mA
IBL
-
0.4
1.0
IBH
-
0.4
0.6
mA
Forward or Reverse
VBL=-24V
-
55
-
mW
Low Power Standby
VBH=-100V
-
85
-
mW
VBH=-85V
-
75
-
mW
VBH=-75V
-
65
-
mW
VBH=-100V
-
250
-
mW
VBH=-85V
-
230
-
mW
VBH=-75V
-
225
-
mW
VB =-24V
-
305
-
mW
f=300Hz
-
40
-
dB
f=1kHz
-
35
-
dB
f=3.4kHz
-
28
-
dB
f=300Hz
-
45
-
dB
f=1kHz
-
43
-
dB
f=3.4kHz
-
33
-
dB
VBL to 2-Wire
300Hz ≤ f ≤ 3.4kHz
-
30
-
dB
VBL to 4-Wire
300Hz ≤ f ≤ 3.4kHz
-
35
-
dB
VBH to 2-Wire
300Hz ≤ f ≤ 3.4kHz
-
33
-
dB
VBH to 4-Wire
300Hz ≤ f ≤ 1kHz
-
40
-
dB
1kHz < f ≤ 3.4kHz
-
45
-
dB
Power Denial, BSEL=0 or 1
ON HOOK POWER DISSIPATION (Note 7)
Ringing
OFF HOOK POWER DISSIPATION (Note 7)
Forward or Reverse
POWER SUPPLY REJECTION RATIO
VCC to 2-Wire
VCC to 4-Wire
NOTES:
3. These parameters are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial
design release and upon design changes which would affect these characteristics.
4. Differential Ringing Gain is measured with VRS = 0.795VRMS for -100V devices, VRS = 0.663 VRMS for -85V devices and VRS = 0.575VRMS
for -75V devices.
5. Longitudinal Balance is tested per IEEE455-1985, with 368Ω per Tip and Ring terminal.
6. These parameters are tested 100% at room temperature. These parameters are guaranteed not tested across temperature via statistical
characterization and design.
7. The power dissipation is based on actual device measurements and will be less than worst case calculations based on data sheet supply current
limits.
8. Characterized with 2 x 10µs, and 10 x 1000µs first level lightning surge waveforms (GR-1089-CORE)
9. For Unbalanced Ringing the Tip terminal is offset to 0V and the Ring terminal is centered at Vbh/2 + 0.5V.
8
ISL5585
Design Equations
Switch Hook Detect
The switch hook detect threshold is set by a single external
resistor, RSH . Equation 1 is used to calculate the value of RSH.
(EQ. 1)
R SH = 600 ⁄ I SH
The term ISH is the desired DC loop current threshold. The
loop current threshold programming range is from 5mA to
15mA (40kΩ < RSH<120kΩ).
Ground Key Detect
For example a source current limit setting of 95mA is
programmed with a 18.7kΩ (RTL) resistor connected from the
TL pin of the device to ground. This setting determines the
maximum amount of current which flows from Tip to Ring
during an off hook event until the DC loop current limit
responds. In addition this setting also determines the amount
of current which will flow from Tip or Ring when external
battery faults occur.
Transient Sink Current Programming
The sink current limit is internally offset 20% higher than the
externally programmed source current limit setting.
I SNK = 1.20 × I SRC
(EQ. 5)
The ground key detector senses a DC current imbalance
between the Tip and Ring terminals when the ring terminal is
connected to ground. The ground key detect threshold is not
externally programmable and is internally fixed to 12mA
regardless of the switch hook threshold.
If the source current limit is set to 95mA, the sink current limit
will be 114mA. This setting will determine the maximum current
that flows into Tip or Ring when external ground faults occur.
Ring Trip Detect
Understanding Transient Current Limit
The ring trip detect threshold is set by a single external
resistor, RRT. IRT should be set between the peak ringing
current and the peak off hook current while still ringing.
Each tip and ring amplifier is designed to limit source current
and sink current. Figure 1 shows the functionality of the
circuit for the case of limiting the source current. A similar
diagram applies to the sink current limit with current polarity
changed accordingly.
R RT = 1800 ⁄ I RT
(EQ. 2)
In addition, the ring trip current must be set below the
transient current limit, including tolerances. The capacitor
CRT, in parallel with RRT, will set the ring trip response time.
Loop Current Limit
The loop current limit of the device is programmed by the
external resistor RIL. The value of RIL can be calculated
using Equation 3.
1760
R IL = ------------I LIM
During normal operation, the error current (IERR) is zero and
the output voltage is determined by the signal current (ISIG)
multiplied by the 200K feedback resistor. With the current
polarity as shown for ISIG , the output voltage moves
positivewith respect to half battery. Assuming the amplifier
output is driving a load at a more negative potential, the
amplifier output will source current.
IO/K
(EQ. 3)
IREF = 1.21/TL
IERR
200K
The term ILIM is the desired loop current limit. The loop
current limit programming range is from 15mA to 45mA
(39kΩ < RIL<117kΩ).
TIP or RING
IO
Transient Current Limit
20
+
VB/2
ISIG
The drive current capability of the output tip and ring
amplifiers is programmed by an external resistor RTL. This
output current limit is separate from the DC loop current
limit function. The current limit circuit works in both the
source and sink direction, with an internally fixed offset to
prevent the current limit functions from turning on
simultaneously. The current limit function is provided by
sensing line current and reducing the voltage drive to the
load when the externally set threshold is exceeded, hence
forcing a constant source or sink current.
During excessive output source current flow, the scaled
output current (IO/K) exceeds the reference current (IREF)
forcing an error current (IERR). With the polarity as shown
the error current subtracts from the signal current, which
reduces the amplifier output voltage. By reducing the output
voltage the source current to the load is decreased and the
output current is limited.
Transient Source Current Programming
Setting the Proper Transient Current Limit
The source current is externally programmed as shown in
Equation 4.
Since this feature programs the maximum output current of
the device, the setting must be high enough to allow for
1650
R TL = ------------I SRC
(EQ. 4)
9
FIGURE 1. CURRENT LIMIT FUNCTIONAL DIAGRAM
ISL5585
detection of ring trip or programmed off hook loop current,
whichever is greater.
If loop current is larger than ring trip current (low REN
applications) then the transient current limit should be set at
least 35% higher than the loop current setting. The slightly
higher offset accounts for the slope of the loop current limit
function.
Attention to detail should be exercised when programming
the transient current limit setting. If ring trip detect does not
occur while ringing, then re-examine the transient current
limit and ring trip threshold settings.
DC Loop Feed
The feedback mechanism for monitoring the DC portion of
the loop current is the loop detector. A low pass filter is used
in the feedback to block voice band signals from interfering
with the loop current limit function. The pole of the low pass
filter is set by the external capacitor CDC . The value of the
external capacitor should be 4.7µF, 6.3V rated polarized or
non-polarized capacitor.
Most applications will operate the device from low battery
while off hook. The DC feed characteristic of the device will
drive Tip and Ring towards half battery to regulate the DC
loop current. For light loads or Long Loops, Tip will be near
-4V and Ring will be near VVBL + 5V. Figure 2 shows the DC
feed characteristic in terms of tip to ring voltage and loop
current.
LONG LOOP
IA
LONG LOOP
IB
ILIM
m=11.11k
ILOOP (mA)
To allow for proper ring trip operation, the transient current
limit setting should be set at least 25% higher than the peak
ring trip current setting. Setting the transient current 25%
higher should account for programming tolerances of both
the ring trip threshold and the transient current limit.
SHORT LOOP
ISC
m=Vtr(oc)/Rloop
CONSTANT CURRENT
2RP
RLOOP (Ω)
CONSTANT VOLTAGE
OR
RESISTIVE FEED
RKNEE
FIGURE 3. ILOOP vs. RLOOP LOAD CHARACTERISTIC
The slope of the feed characteristic and the battery voltage
define the maximum loop current on the shortest possible
loop as the short circuit current ISC.
V TR ( OC ) – 2RP I LIM
I SC = I LIM + ----------------------------------------------------11.11k
(EQ. 7)
The term ILIM is the programmed current limit, 1760/RIL. The
line segment IA represents the constant current region of the
loop current limit function.
V TR ( OC ) – R LOOP I LIM
I A = I LIM + -------------------------------------------------------------11.11k
(EQ. 8)
Process variations in the ISL5585 effect the ILIM and
11.11kΩ slope in Equation 8. All units are tested with: a
300Ω load across tip and ring, VBAT=-24V and ILIM set to
25mA. Equation 8 can be used to predict the ideal current at
this setting (25.76mA). All units are tested to be within
±8.5% of this ideal value (23.57mA to 27.95mA).
The maximum loop impedance for a programmed loop
current is defined as RKNEE .
V TR ( OC )
R KNEE = ----------------------I LIM
(EQ. 9)
SHORT LOOP
VTR(OC)
VTR , DC (V)
m = (∆VTR/∆IL) = 11.1kΩ
When RKNEE is exceeded, the device will transition from
constant current feed to constant voltage or resistive feed.
The line segment IB represents the resistive feed portion of
the load characteristic
ILOOP (mA)
V TR ( OC )
I B = ----------------------R LOOP
ILIM
FIGURE 2. DC FEED CHARACTERISTIC
Impedance Matching
The point on the y-axis labeled VTR(OC) is the open circuit
Tip to Ring voltage and is defined by the feed battery voltage
in Equation 6.
(EQ. 6)
V TR ( OC ) = V BL – 9
Figure 3 illustrates the actual loop current for a given set of
loop conditions. The loop conditions are determined by the
low battery voltage and the DC loop impedance. The DC
loop impedance is the sum of the protection resistance,
copper resistance (ohms/foot) and the telephone off hook
DC resistance.
10
(EQ. 10)
The impedance of the device is programmed with the
external component RS . RS is the gain setting resistor for
the Transmit Amplifier that provides impedance matching. If
complex impedance matching is required, then a complex
network can be substituted for RS .
The feedback mechanism for monitoring the AC portion of
the loop current consists of two amplifiers, the Sense
Amplifier (SA) and the Transmit Amplifier (TA). The AC
feedback signal is used for impedance synthesis. A detailed
model of the AC feed back loop is shown in Figure 4.
ISL5585
The gain of the Transmit Amplifier, set by RS , determines
the programmed impedance of the device. The capacitor
CFB blocks the DC component of the loop current. The
ground symbols in the model represent AC grounds, not
actual DC potentials.
The voltage at VTX is equal to:
RS
RS
 RS 
 RS 
V TX = – V IN  ---------- – V SA  -------- = – V IN  ---------- – ( ∆I M 30 )  --------
 8k 
 8k 
 R IN
 R IN
(EQ. 17)
VTR is defined in Figure 4, note polarity assigned to VTR:
The Sense Amplifier is configured as a 4 input differential
amplifier with a gain of 3/4. The voltage at the output of the
sense amplifier (VSA) is calculated using superposition.
VSA1 is the voltage resulting from V1, VSA2 is the voltage
resulting from V2 and so on (reference Figure 4).
3
V SA 1 = – --- ( V 1 )
4
(EQ. 11)
3
V SA 2 = --- ( V 2 )
4
(EQ. 12)
3
V SA 3 = – --- ( V 3 )
4
(EQ. 13)
3
V SA 4 = --- ( V 4 )
4
(EQ. 14)
3
3
V SA = [ ( V 2 – V 1 ) + ( V 4 – V 3 ) ] --- = [ ∆V + ∆V ] --4
4
(EQ. 15)
RS 
 RS 

V TR = 2 ( V TX ) = 2  V IN  ---------- + ( ∆I M 30 )  -------- 

R
8k  
 IN

Setting VIN equal to zero in EQ 18, defining ZO = -VTR/∆IM
and substituting it into EQ18 will enable the user to
determine the required feedback to match the line
impedance at V2W as shown in Equation 19.
2-Wire Impedance Matching
ZO is the source impedance of the device and is defined as.
3
V SA = 2 ( ∆I M × 20 ) --- = ∆I M 30
4
ZL is the line impedance and RP is the external protection
resistor. RS is defined as:
R S = 133.33 ( Z L – 2R P )
IX
-
V2
RSENSE
IX RECEIVE BLOCK
V1
+
20Ω
I
+ M
ZL
IM
-
(EQ. 21)
INTERSIL
ISL5585
+
R
I
+ M
RP
IX
R
AUX
1:1
FEED
AMPLIFIER
Z0
R
-
+
+
V2W
-
(EQ. 20)
Z O = Z L – 2RP
(EQ. 16)
-
-
(EQ. 19)
1
Z O = ------------------ R S
133.33
Where ∆V is equal to IMRSENSE (RSENSE = 20Ω)
TIP
VTR
+
+
VTX
E
- G
- IM +
RING
RP
FEED
AMPLIFIER
RSENSE
V3
V4
+
20Ω
IX
- IM +
+
R
+
VTX
-
FEEDBACK
AMPLIFIER
TA
+
4R
3R
4R
+
4R
3R
RS
-IN
4R
8k
CFB
VFB
VSA = ∆IM30
SENSE
AMPLIFIER
FIGURE 4. AC SIGNAL TRANSMISSION MODEL
11
(EQ. 18)
RIN
VIN
FROM CODEC
ISL5585
Complex Impedance Synthesis
Loop Equation at Tip/Ring interface
Substituting the impedance programming resistor, RS, with a
complex programming network provides complex impedance
synthesis.
2-WIRE
NETWORK
C2
PROGRAMMING
NETWORK
CParallel
R1
(EQ. 31)
V 2W -I M 2R P + V TR = 0
Substitute Equation 30 into Equation 31 and combine terms
Z L + Z O + 2R P
RS
V 2W -------------------------------------- = 2V IN ---------R IN
ZL
(EQ. 32)
where:
RSeries
VIN = The input voltage at the -IN pinthrough resistor RIN.
R2
AUX = Auxiliary input of SLIC. Not used for AC gains.
RParallel
FIGURE 5. COMPLEX PROGRAMMING NETWORK
The reference designators in the programming network
match the evaluation board. The component RS has a
different design equation than the RS used for resistive
impedance synthesis. The design equations for each
component are provided below.
VSA = An internal node voltage that is a function of the loop
current and the output of the Sense Amplifier.
IX = Internal current in the SLIC that is the difference between
the input receive current and the feedback current.
IM = The AC metallic current.
RP = A protection resistor (typical 49.9Ω).
RS = An external resistor/network for matching the line
impedance.
VTR = The tip to ring voltage at the output pins of the SLIC.
R Series = 133.3 × ( R 1 – 2 ( R P ) )
(EQ. 22)
R Parallel = 133.3 × R 2
(EQ. 23)
·
C Parallel = C 2 ⁄ 133.3
V2W = The tip to ring voltage including the voltage across the
protection resistors.
ZL = The line impedance.
(EQ. 24)
ZO = The source impedance of the device.
4-Wire to 2-Wire Gain
Node Equation at ISL5585 AUX input, Figure 4
AUX V TX
I X = ------------- + ----------R
R
(EQ. 25)
Substituting EQ 17 for VTX with AUX =0 and ∆IM= -V2W/ZL
gives us EQ 26. Note: AUX input is not used.
Substitute EQ 17 into EQ 21
V IN  R S   V 2w 30 R S
V TX
I X = ---------- = – ---------  ---------- –  ------------------  -----------
R  R IN  Z L   R8k
R
(EQ. 26)
4-wire to 2-wire gain across the ISL5585 is equal to the V2W
divided by the input voltage VIN, reference Figure 4. The
receive gain is calculated using Equation 32.
Equation 33 expresses the receive gain (VIN to V2W) in
terms of network impedances. From Equation 21, the value
of RS was set to match the line impedance (ZL) to the
ISL5585 plus the protection resistors (Z0 + 2RP). This
results in a 4-wire to 2-wire gain equal to RS/RIN, as shown
in EQ. 33.
ZL
V 2W
ZL
RS
 RS 
G 4-2 = ------------ = 2  ---------- ---------------------------------------- = 2 -------------------- = --------V IN
R
Z
+
Z
+
2
Z
+
Z
R
 IN L
O
RP
L
L
IN
Loop Equation at ISL5585 feed amplifiers and load.
(EQ. 27)
I X R - V TR + I X R = 0
(EQ. 33)
2-Wire to 4-Wire Gain
Substitute EQ 26 into EQ 27
 R S   2V 2w 30 R S
V TR = – 2V IN  ---------- +  ----------------------  --------
 R IN  Z L   8k 
The 2-wire to 4-wire gain is equal to VTX/EG with VIN = 0,
reference Figure 4.
(EQ. 28)
Loop Equation
(EQ. 34)
– E G + Z L I M + 2R P I M – V TR = 0
From Equation 30 with VIN = 0
Substitute Equation 19 for RS/8k in Equation 28.
 R S   2V 2w 30 133.33Z O
V TR = – 2V IN  ---------- +  ----------------------  --------------------------

8k
 R IN  Z L  
(EQ. 29)
Z O V 2W
V TR = -------------------ZL
(EQ. 35)
Substituting Equation 35 into Equation 34 and simplify.
Simplifying
 R S   V 2w
V TR = – 2V IN  ---------- +  ----------- ( Z O )
 R IN  Z L 
12
(EQ. 30)
Z L + 2RP + Z O
E G = – V 2W --------------------------------------ZL
(EQ. 36)
ISL5585
Substituting Equation 19 into Equation 17 (VIN =0) and
defining ∆IM = -V2W/ZL results in Equation 37 for VTX.
V 2W Z L – 2R P
V TX = ------------ -----------------------2
ZL
(EQ. 37)
Combining Equations 36 and 37 results in Equation 38.
V TX
ZO
Z L – 2R P
(EQ. 38)
- = – ----------------------------------------------G 2-4 = ---------- = – ----------------------------------------------EG
2 ( Z L + 2R P + Z O )
2 ( Z L + 2R P + Z O )
A more useful form of the equation is rewritten in terms of
VTX /V2W. A voltage divider equation is written to convert
from EG to V2W as shown in Equation 39.
 Z O + 2 RP 
V 2W =  ---------------------------------------- E G
 Z L + Z O + 2 RP
(EQ. 39)
Substituting ZL = ZO + 2RP and rearranging Equation 39 in
terms of EG results in Equation 40.
(EQ. 40)
E G = 2V 2W
Substituting Equation 40 into Equation 38 results in an
equation for 2-wire to 4-wire gain that’s a function of the
synthesized input impedance of the SLIC and the protection
resistors.
V TX
ZO


G 2-4 = ------------ = –  -------------------------------------------- = 0.416
V 2W
 ( Z L + 2R P + Z O )
(EQ. 41)
If ZL is set to 600Ω, ZO is programmed with RS to be
498.76Ω (66.5kΩ/133.33), and RP is equal to 49.9Ω. This
results in a 2-wire to 4-wire gain of 0.416 or -7.6dB.
When the protection resistors are set to zero, the transmit
gain is -6dB.
Transhybrid Gain
The transhybrid gain is defined as the 4-wire to 4-wire gain
(G44).
G 44 = G 42 × G
24
ZO
 RS  

= –  ----------  ---------------------------------------
R
Z
+
2R
+
Z
 IN  L
P
O
13
(EQ. 42)
Understanding Phase Across the ISL5585
4-Wire to 2-Wire Phase
The phase of a signal through the ISL5585 is dependent
upon whether the source is driving the signal 4-wire to 2-wire
or 2-wire to 4-wire.
Figure 6 illustrates the phase of the input signal across the
ISL5585 when the signal is applied at the -IN pin of the
ISL5585 through the RIN resistor. The Transmit Amplifier
(TA) inverts the signal 180 degrees at the VTX pin. The
feedback around the tip amplifier inverts the signal again on
the tip lead. The input signal will cause AC loop current to
flow through the 20 Ω sense resistors in the direction from
V 1 to V2 and V3 to V4. This results in an inverted signal
(referenced from tip) on the VSA and thus the VFB pin. This
out of phase signal is the signal used by the feedback path to
match the line impedance of the 2-wire side.
2-Wire to 4-Wire Phase
Figure 7 Illustrates the phase of the input signal across the
ISL5585 when the signal is applied across tip and ring.
When you’re driving the 2-wire side with a source the
ISL5585 looks like a predetermined impedance
(programmed with resistor RS). The current flows through
the 20Ω sense resistors in the direction V2 to V1 and V4 to
V3. This results in a non-inverted signal (referenced from tip)
on the VSA and thus the VFB pin. This signal is then
inverted by the TA amplifier and the signal appearing on the
VTX putput is out of phase with the signal on tip.
Summary of the Phase Through the ISL5585
4-Wire to 2-Wire (VIN to V2W) is 180° out of phase
2-Wire to 4-Wire (V2w to VTX) is 180° out of phase
4-Wire to 4-Wire (VIN to VTX) is 180° out of phase
ISL5585
IX
2-WIRE SIDE
TIP
-
IM
R
+
V2
RSENSE
RP
+
V2W
-
INTERSIL
ISL5585
+
-
-
20Ω
IM
+
4-WIRE SIDE
IX RECEIVE BLOCK
V1
+
IX
AUX
R
1:1
FEED
AMPLIFIER
R
VTX
ZL
RING
+
VTX
-
FEED
RSENSE
AMPLIFIER
V3
V4
+
20Ω
I
X
+ IM +
+ IM RP
INPUT
TA
R
RS
+
4R
3R
4R
4R
+
4R
3R
RIN
-IN
VIN
CFB
8k
FROM CODEC
VFB
VSA = ∆IM30
SENSE
AMPLIFIER
FIGURE 6. 4-WIRE TO 2-WIRE SIGNAL PHASE ACROSS THE ISL5585
IX
2-WIRE SIDE
I
+ M
TIP
INPUT
R
-
RP
+
V2W
- IM +
RING
RP
INTERSIL
ISL5585
+
-
V2
RSENSE
20Ω
I
+ M
-
4-WIRE SIDE
IX RECEIVE BLOCK
V1
+
IX
R
FEED
AMPLIFIER
R
VTX
+
VTX
-
FEED
RSENSE
AMPLIFIER
V3
V4
+
20Ω
I
X
I
+
M
+
TA
R
+
4R
AUX
1:1
3R
4R
4R
+
4R
3R
RS
-IN
8k
VIN
CFB
VFB
VSA = ∆IM30
SENSE
AMPLIFIER
FIGURE 7. 2-WIRE TO 4-WIRE SIGNAL PHASE ACROSS THE ISL5585
14
RIN
FROM CODEC
ISL5585
Low Power Standby
Overview
The low power standby mode (LPS, 000) should be used
during idle line conditions. The device is designed to operate
from the high battery during this mode. Most of the internal
circuitry is powered down, resulting in low power dissipation.
If the 2-wire (tip/ring) DC voltage requirements are not
critical during idle line conditions, the device may be
operated from the low battery. Operation from the low battery
will decrease the standby power dissipation.
TABLE 1. DEVICE INTERFACES DURING LPS
INTERFACE
ON
OFF
NOTES
Receive
x
Ringing
x
AC transmission, impedance
matching and ringing are
disabled during this mode.
Transmit
x
2-Wire
x
Amplifiers disabled.
Loop Detect
x
Switch hook or ground key.
2-Wire Interface
During LPS, the 2-wire interface is maintained with internal
switches and voltage references. The Tip and Ring
amplifiers are turned off to conserve power. The device will
provide MTU compliance, loop current and loop supervision.
Figure 8 represents the internal circuitry providing the 2-wire
interface during low power standby.
voltage exceeds the MTU reference of -56V, the Ring
terminal will be clamped by the internal reference (typically 54V). The same Ring relationships apply when operating
from the low battery voltage. For high battery voltages (VBH)
less than or equal to the internal MTU reference threshold:
V RING = V BH + 5
Loop Current
During LPS, the device will provide current to a load. The
current path is through resistors and switches, and is a
function of the off hook loop resistance (RLOOP). This
includes the off hook phone resistance and copper loop
resistance. The current available during LPS is determined
by Equation 44.
I LOOP = ( – 1 – ( – 54 ) ) ⁄ ( 600 + 600 + R LOOP )
(EQ. 44)
Internal current limiting of the standby switches will limit the
maximum current to approximately 20mA.
Another loop current related parameter is longitudinal
current capability. The longitudinal current capability is
reduced. The reduction in longitudinal current capability is a
result of turning off the Tip and Ring amplifiers.
On Hook Power Dissipation
The on hook power dissipation of the device during LPS is
determined by the operating voltages and quiescent currents
and is calculated using Equation 45.
P LPS = V BH × I BHQ + V BL × I BLQ + V CC × I CCQ
GND
(EQ. 43)
(EQ. 45)
600Ω
TIP AMP
TIP
RING
RING AMP
600Ω
MTU REF
FIGURE 8. LPS 2-WIRE INTERFACE CIRCUIT DIAGRAM
MTU Compliance
Maintenance Termination Unit or MTU compliance places
DC voltage requirements on the 2-wire terminals during idle
line conditions. The minimum idle voltage is 42.75V. The
high side of the MTU range is 56V. The voltage is expressed
as the difference between Tip and Ring.
The Tip voltage is held near ground through a 600Ω resistor
and switch. The Ring voltage is limited to a maximum of -56V
(by MTU REF) when operating from either the high or low
battery. A switch and 600Ω resistor connect the MTU
reference to the Ring terminal. When the high battery
15
The quiescent current terms are specified in the electrical
tables for each operating mode. Load power dissipation is
not a factor since this is an on hook mode. Some
applications may specify a standby current. The standby
current may be a charging current required for modern
telephone electronics.
Standby Current Power Dissipation
Any standby line current, ISLC , introduces an additional
power dissipation term PSLC . Equation 46 illustrates the
power contribution is zero when the standby line current is
zero.
P SLC = I SLC × ( V BH – 54 + 1 + I SLC x1200 )
(EQ. 46)
If the battery voltage is less than -54V (the MTU clamp is
off), the standby line current power contribution reduces to
Equation 47.
P SLC = I SLC × ( V BH + 1 + I SLC x1200 )
(EQ. 47)
ISL5585
Most applications do not specify charging current
requirements during standby. When specified, the typical
charging current may be as high as 5mA.
Forward Active
Overview
The final step in completing the impedance synthesis design
is calculating the necessary gains for transhybrid balance.
The AC feed back loop produces an echo at the VTX output
of the signal injected at VIN . The echo must be cancelled to
maintain voice quality. Most applications will use a summing
amplifier in the CODEC front end as shown in Figure 10 to
cancel the echo signal.
R
AUX
R
TA
RS
-IN
On-Hook Transmission
The primary purpose of on hook transmission will be to
support caller ID and other advanced signalling features.
The transmission over load level while on hook is 1 VPEAK .
When operating from the high battery, the DC voltages at Tip
and Ring are MTU compliant. The typical Tip voltage is -4V
and the Ring voltage is a function of the battery voltage for
battery voltages less than -60V as shown in Equation 48.
V RING = V BH + 5
(EQ. 48)
Loop supervision is provided by the switch hook detector at
the DET output. When DET goes low, the low battery should
be selected for DC loop feed and voice transmission.
Feed Architecture
The design implements a voltage feed current sense
architecture. The device controls the voltage across Tip and
Ring based on the sensing of load current.Internal resistors
(RCS) are placed in series with Tip and Ring outputs to
provide the current sensing. The diagram below illustrates
the concept.
RB
RA
VIN
RCS
-
VOUT
+
RL
RC
-
+
KS
FIGURE 9. VOLTAGE FEED CURRENT SENSE DIAGRAM
By monitoring the current at the amplifier output, a negative
feedback mechanism sets the output voltage for a defined
load. The amplifier gains are set by resistor ratios (RA , RB ,
RC) providing all the performance benefits of matched
resistors. The internal sense resistor, RCS , is much smaller
than the gain resistors and is typically 20Ω for this device.
The feedback mechanism, KS , represents the amplifier
configuration providing the negative feedback.
16
RF
RA
VTX
1:1
+
The forward active mode (FA, 001) is the primary AC
transmission mode of the device. On hook transmission, DC
loop feed and voice transmission are supported during forward
active. Loop supervision is provided by either the switch hook
detector (E0 = 1) or the ground key detector (E0 = 0). The
device may be operated from either high or low battery for onhook transmission and low battery for loop feed.
Transhybrid Balance
+
TX IN
RIN
RB
+2.4V
RX OUT
ISL5585
CODEC
FIGURE 10. TRANSHYBRID BALANCE INTERFACE
The resistor ratio, RF /RA , provides the final adjustment for
the transmit gain, GTX (V2w to PCM, Figure 18). The transmit
gain is calculated using Equation 49.
ZO
 R F

  R F
G TX = – G 24  -------- = –  --------------------------------------------  --------
R
(
Z
+
2R
+
Z
)
 A
 L
P
O   R A
(EQ. 49)
Most applications set RF = RA , hence the device 2-wire to
4-wire equals the transmit gain. Typically RA is greater than
20kΩ to prevent loading of the device transmit output. The
value of the RF resistor should greater than the minimum
load spec of the CODEC’s internal amplifier (typical value
30.1kΩ).
The resistor ratio, RF /RB , is determined by the transhybrid
gain of the device, G44 . RF is previously defined by the
transmit gain requirement and RB is calculated using
Equation 50.
RA
 R IN  Z L + 2R P + Z O
- = R A  ----------  ---------------------------------------
R B = --------ZO
G 44
 RS  

(EQ. 50)
Power Dissipation
The power dissipated by the device during on hook
transmission is strictly a function of the quiescent currents
for each supply voltage during Forward Active operation.
+ V BL × I BLQ + V CC × I CCQ
P FAQ = V BH × I
BHQ
(EQ. 51)
Off hook power dissipation is increased above the quiescent
power dissipation by the DC load. If the loop length is less
than or equal to RKNEE , the device is providing constant
current, IA , and the power dissipation is calculated using
Equation 52.
P FA ( IA ) = P FA ( Q ) + ( V BL xI A ) – ( R LOOP xI 2 A )
(EQ. 52)
ISL5585
If the loop length is greater than RKNEE , the device is
operating in the constant voltage, resistive feed region. The
power dissipated in this region is calculated using Equation 53.
P FA ( IB ) = P FA ( Q ) + ( V BL xI B ) – ( R LOOP xI 2 B )
(EQ. 53)
a differential pair which controls the reversal time of the Tip
and Ring DC voltages.
∆time
C POL = ---------------75000
(EQ. 54)
Since the current relationships are different for constant
current versus constant voltage, the region of device
operation is critical to valid power dissipation calculations.
Where ∆time is the required reversal time. Polarized
capacitors may be used for CPOL . The low voltage at the
POL pin and minimal voltage excursion ±0.75V, are well
suited to polarized capacitors.
Reverse Active
Power Dissipation
Overview
The power dissipation equations for forward active operation
also apply to the reverse active mode.
The reverse active mode (RA, 011) provides the same
functionality as the forward active mode. On hook
transmission, DC loop feed and voice transmission are
supported. Loop supervision is provided by either the switch
hook detector (E0 = 1) or the ground key detector (E0 = 0).
The device may be operated from either high or low battery.
During reverse active the Tip and Ring DC voltage
characteristics exchange roles. That is, Ring is typically 4V
below ground and Tip is typically 4V more positive than
battery. Otherwise, all feed and voice transmission
characteristics are identical to forward active.
Silent Polarity Reversal
Changing from forward active to reverse active or vice versa
is referred to as polarity reversal. Many applications require
slew rate control of the polarity reversal event. Requirements
range from minimizing cross talk to protocol signalling.
The device uses an external low voltage capacitor, CPOL , to
set the reversal time. Once programmed, the reversal time
will remain nearly constant over various load conditions. In
addition, the reversal timing capacitor is isolated from the AC
loop, therefore loop stability is not impacted.
Ringing
Overview
The ringing mode (RNG, 100) provides linear amplification to
support a variety of ringing waveforms. A programmable ring
trip function provides loop supervision and auto disconnect
upon ring trip. The device is designed to operate from the
high battery during this mode.
Architecture
The device provides linear amplification to the signal applied
to the ringing input, VRS . The differential ringing gain of the
device is 80V/V. The circuit model for the ringing path is
shown in Figure 12.
The voltage gain from the VRS input to the Tip output is
40V/V. The resistor ratio provides a gain of 8 and the current
mirror provides a gain of 5. The voltage gain from the VRS
input to the Ring output is -40V/V.
R
20
-
+
-
TIP
The internal circuitry used to set the polarity reversal time is
shown in Figure 11.
R/8
+
5:1
20
+
RING
-
I1
VRS
600K
+ VBH
2
POL
R
75kΩ
CPOL
FIGURE 12. LINEAR RINGING MODEL
I2
The equations for the Tip and Ring outputs during ringing
are provided below.
FIGURE 11. REVERSAL TIMING CONTROL
During forward active, the current from source I1 charges the
external timing capacitor CPOL and the switch is open. The
internal resistor provides a clamping function for voltages on
the POL node. During reverse active, the switch closes and
I2 (roughly twice I1) pulls current from I1 and the timing
capacitor. The current at the POL node provides the drive to
17
V BH
V T = ----------+ ( 40 × VRS )
2
(EQ. 55)
V BH
V R = ----------– ( 40 × VRS )
2
(EQ. 56
ISL5585
When the input signal at VRS is zero, the Tip and Ring
amplifier outputs are centered at half battery. The device
provides auto centering for easy implementation of
sinusoidal ringing waveforms. Both AC and DC control of the
Tip and Ring outputs is available during ringing. This feature
allows for DC offsets as part of the ringing waveform.
The terms tR and tS represent the cadence. The ringing
interval is tR and the silent interval is tS . The typical cadence
ratio tR :tS is 1:2.
The quiescent power of the device in the ringing mode is
defined in Equation 58.
P r ( Q ) = V BH × I BHQ + V BL × I BLQ + V CC × I CCQ
Ringing Input
(EQ. 58)
The ringing input, VRS , is a high impedance input. The high
impedance allows the use of low value capacitors for AC
coupling the ring signal. The VRS input is enabled only
during the ringing mode, therefore a free running oscillator
may be connected to VRS at all times.
The total power during the ringing interval is the sum of the
quiescent power and loading power:
When operating from a battery of -100V, each amplifier, Tip
and Ring, will swing a maximum of 95VP-P. Hence, the
maximum signal swing at VRS to achieve full scale ringing is
approximately 2.4VP-P. The low signal levels are compatible
with the output voltage range of the CODEC. The digital
nature of the CODEC ideally suits it for the function of
programmable ringing generator.
For sinusoidal waveforms, the average current, IAVG , is
defined in Equation 60.
Logic Control
Unbalanced Ringing
Ringing patterns consist of silent intervals. The ringing to
silent pattern is called the ringing cadence. During the silent
portion of ringing, the device can be programmed to any
other operating mode. The most likely candidates are low
power standby or forward active. Depending on system
requirements, the low or high battery may be selected.
Loop supervision is provided with the ring trip detector. The ring
trip detector senses the change in loop current when the phone
is taken off hook. The loop detector full wave rectifies the
ringing current, which is then filtered with external components
RRT and CRT. The resistor RRT sets the trip threshold and the
capacitor CRT sets the trip response time. Most applications will
require a trip response time less than 150ms.
Three very distinct actions occur when the devices detects a
ring trip. First, the DET output is latched low. The latching
mechanism eliminates the need for software filtering of the
detector output. The latch is cleared when the operating
mode is changed externally. Second, the VRS input is
disabled, removing the ring signal from the line. Third, the
device is internally forced to the forward active mode.
Power Dissipation
The power dissipation during ringing is dictated by the load
driving requirements and the ringing waveform. The key to valid
power calculations is the correct definition of average and RMS
currents. The average current defines the high battery supply
current. The RMS current defines the load current.
The cadence provides a time averaging reduction in the
peak power. The total power dissipation consists of ringing
power, Pr , and the silent interval power, Ps .
tr
ts
P RNG = P r × -------------- + P s × -------------t +t
t +t
r
s
r
s
18
(EQ. 57)
2
V RMS
P r = P r ( Q ) + V BH × I AVG – ----------------------------------------Z
+R
REN
V RMS × 2
2
I AVG =  --- ----------------------------------------- π Z
+R
REN
(EQ. 59)
LOOP
(EQ. 60)
LOOP
The silent interval power dissipation will be determined by
the quiescent power of the selected operating mode.
The ISL5585GCM offers Unbalanced Ringing mode (010).
This feature accommodates some Analog PBX Trunk Lines
that require the Tip terminal to be held near ground for the
duration of the ringing bursts. The Tip terminal is offset to
0V’s with an internal current source that is applied to the
inverting input of the Tip amplifier. This reduces the
differential ringing gain to 40V/V. The Ring terminal will
center at Vbh/2 and swing from -Vbh to ground. As in
Balanced Ringing, off hook detection is accomplished by
sensing the peak current and comparing it to a preset
threshold. This allows the same sensing, comparing and
threshold circuitry to be used in both Ringing modes. This
mode of operation does not require any additional external
components.
Forward Loop Back
Overview
The Forward Loop Back mode (FLB, 101) provides test
capability for the device. An internal signal path is enabled
allowing for both DC and AC verification. The internal 600Ω
terminating resistor has a tolerance of ±20%. The device is
intended to operate from only the low battery during this
mode.
Architecture
ISL5585
When the forward loop back mode is initiated internal
switches connect a 600Ω load across the outputs of the Tip
and Ring amplifiers.
TIP
TIP AMP
600Ω
RING AMP
RING
DC Verification
When the internal signal path is provided, DC current will
flow from Tip to Ring. The DC current will force DET low,
indicating the presence of loop current. In addition, the ALM
output will also go low. This does not indicate a thermal
alarm condition. Rather, proper logic operation is verified in
the event of a thermal shutdown. In addition to verifying
device functionality, toggling the logic outputs verifies the
interface to the system controller.
AC Verification
FIGURE 13. FORWARD LOOP BACK INTERNAL TERMINATION
The entire AC loop of the device is active during the forward
loop back mode. Therefore a 4-wire to 4-wire level test
capability is provided. Depending on the transhybrid balance
implementation, test coverage is provided by a one or two
step process.
System architectures which cannot disable the transhybrid
function would require a two step process. The first step
would be to send a test tone to the device while on hook and
not in forward loop back mode. The return signal would be
the test level times the gain RF /RA of the transhybrid
amplifier. Since the device would not be terminated,
cancellation would not occur. The second step would be to
program the device to FLB and resend the test tone. The
return signal would be much lower in amplitude than the first
step, indicating the device was active and the internal
termination attenuated the return signal. System
architectures which disable the transhybrid function would
achieve test coverage with a signal step. Once the
transhybrid function is disable, program the device for FLB
and send the test tone. The return signal level is determined
by the 4-wire to 4-wire gain of the device.
Tip Open
Overview
The tip open mode (110) is intended for compatibility for PBX
type interfaces. Used during idle line conditions, the device
does not provide transmission. Loop supervision is provided
by either the switch hook detector (E0 = 1) or the ground key
detector (E0 = 0). The ground key detector will be used in
most applications. The device may be operated from either
high or low battery.
Functionality
During tip open operation, the Tip switch is disabled and the
Ring switch is enabled. The minimum Tip impedance is
30kΩ. The only active path through the device will be the
Ring switch.
In keeping with the MTU characteristics of the device, Ring
will not exceed -56V when operating from the high battery.
Though MTU does not apply to tip open, safety requirements
are satisfied.
19
ISL5585
Power Denial
High Battery Operation
Overview
The power denial mode (111) will shutdown the entire device
except for the logic interface. Loop supervision is not
provided. This mode may be used as a sleep mode or to
shut down in the presence of a persistent thermal alarm.
Switching between high and low battery will have no effect
during power denial.
Functionality
During power denial, both the Tip and Ring amplifiers are
disabled, representing high impedances. The voltages at
both outputs are near ground.
Thermal Shutdown
Other than during ringing, the high battery should be used
for standby conditions which must provide MTU compliance.
During standby operation the power consumption is typically
85mW with -100V battery. If ringing requirements do not
require full 100V operation, then a lower battery will result in
lower standby power.
High Voltage Decoupling
The 100V rating of the device will require a capacitor of
higher voltage rating for decoupling. Suggested decoupling
values for all device pins are 0.1µF. Standard surface mount
ceramic capacitors are rated at 100V. For applications driven
at low cost and small size, the decoupling scheme shown
below could be implemented.
In the event the safe die temperature is exceeded, the ALM
output will go low and DET will go high and the part will
automatically shut down. When the device cools, ALM will
go high and DET will reflect the loop status. If the thermal
fault persists, ALM will go low again and the part will shut
down. Programming power denial will permanently
shutdown the device and stop the self cooling cycling.
0.22µ
0.22µ
VBL
VBH
ISL5585
FIGURE 14. ALTERNATE DECOUPLING SCHEME
Battery Switching
Overview
The integrated battery switch selects between the high
battery and low battery. The battery switch is controlled
with the logic input BSEL. When BSEL is a logic high, the
high battery is selected and when a logic low, the low
battery is selected. All operating modes of the device will
operate from high or low battery except forward loop back,
which requires low battery for thermal reasons.
Functionality
The logic control is independent of the operating mode
decode. Independent logic control provides the most
flexibility and will support all application configurations.
When changing device operating states, battery switching
should occur simultaneously with or prior to changing the
operating mode. In most cases, this will minimize overall
power dissipation and prevent glitches on the DET output.
The only external component required to support the battery
switch is a diode in series with the VBH supply lead. In the
event that high battery is removed, the diode allows the
device to transition to low battery operation.
Low Battery Operation
All off hook operating conditions should use the low battery.
The prime benefit will be reduced power dissipation. The
typical low battery for the device is -24V. However this may
be increased to support longer loop lengths or high loop
current requirements. Standby conditions may also operate
from the low battery if MTU compliance is not required,
further reducing standby power dissipation.
20
It is important to place the external diode between the VBH
pin and the decoupling capacitor. Attaching the decoupling
capacitor directly to the VBH pin will degrade the reliability of
the device. Refer to Figure 14 for the proper arrangement.
This applies to both single and stacked and decoupling
arrangements.
If VBL and VBH are tied together to override the battery
switch function, then the external diode is not needed and
the decoupling may be attached directly to VBH.
Uncommitted Switch
Overview
The uncommitted switch is a three terminal device designed
for flexibility. The independent logic control input, SWC,
allows switch operation regardless of device operating
mode. The switch is activated by a logic low. The positive
and negative terminals of the device are labeled SW+ and
SW- respectively.
Relay Driver
The uncommitted switch may be used as a relay driver by
connecting SW+ to the relay coil and SW- to ground. The
ISL5585
switch is designed to have a maximum on voltage of 0.6V
with a load current of 45mA.
TABLE 2. ISL5585 3V APPLICATION CIRCUIT COMPONENTS
COMPONENT
VALUE
TOL
U1 - Ringing SLIC
ISL5585
N/A
N/A
RTL
18.7kΩ
1%
0.1W
RRT
23.7kΩ
1%
0.1W
RSH
49.9kΩ
1%
0.1W
RIL
71.5kΩ
1%
0.1W
RS
66.5kΩ
1%
0.1W
RF
30.1kΩ
1%
0.1W
RA
36.5kΩ
1%
0.1W
RB
42.2KkΩ
1%
0.1W
Since the device provides the ringing waveform, the relay
functions which may be supported include subscriber
disconnect, test access or line interface bypass. An external
snubber diode is not required when using the uncommitted
switch as a relay driver.
RIN
45.3kΩ
1%
0.1W
CRS , CTX , CRT , CPOL
0.47µF
20%
10V
CDC, CFB
4.7µF
20%
6.3V
CPS1
0.1µF
20%
>100V
0.1µF
20%
100V
Test Load
D1
The switch may be used to connect test loads across Tip and
Ring. The test loads can provide external test termination for
the device. Proper connection of the uncommitted switch to
Tip and Ring is shown below.
RP1 , RP2
Standard applications will use ≥ 49Ω per side. Protection resistor
values are application dependent and will be determined by
protection requirements.
+V
RELAY
SW+
SWC
SW-
FIGURE 15. EXTERNAL RELAY SWITCHING
TIP
RING
CPS2 , CPS3
RATING
1N400X type with breakdown > 100V.
Design Parameters: Ring Trip Threshold = 76mAPEAK , Switch Hook
Threshold = 12mA, Loop Current Limit = 24.6mA, Synthesize Device
Impedance = (3*66.5kΩ)/400 = 498.8Ω, with 49.9Ω protection
resistors, impedance across Tip and Ring terminals = 599Ω.
Transient current limit = 95mA.
Special Considerations for the QFN
Package
TEST
LOAD
SW+
SW-
SWC
FIGURE 16. TEST LOAD SWITCHING
The diode in series with the test load blocks current from
flowing through the uncommitted switch when the polarity of
the Tip and Ring terminals are reversed. In addition to the
reverse active state, the polarity of Tip and Ring are reversed
for half of the ringing cycle. With independent logic control
and the blocking diode, the uncommitted switch may be
continuously connected to the Tip and Ring terminals.
21
The new Quad Flatpack No-lead (QFN) package offers a
significant footprint reduction (65%) and improved thermal
performance with respect to the 28 lead PLCC. To realize the
thermal enhancements and maintain the high voltage
(-100V) performance, the exposed pad on the bottom of the
QFN package should be soldered to a power/heat sink plane
that is electrically connected to the ISL5585 Substrate
Common Connection (SCC) pin. The heat is distributed
evenly across the board by way of the heat sink plane. This
is accomplished by using conductive thermal vias.
Reference technical brief TB379 and AN9922 for additional
information on thermal characterization and board layout
considerations.
ISL5585
CPS1
CPS2
RP1
49.9Ω
+
V2W
-
VCC
VBL
VBH
AUX
TIP
600Ω
U1
RP2
49.9Ω
0.47uF
0.47uF
36.5kΩ
RS
CRT
ISL5585
RB
66.5kΩ
RIN
42.2kΩ
RF
Digital
Gain
0dB
+
45.3kΩ
CFB
0.47uF
VFB
+2.4V
Digital
Gain
0dB
PCM to V2W Gain = +3.33dB, digital gain set to 0dB
SH
CDC
RIL
CPOL
ILIM
POL
CDC
RTL
VRS
AGND
TL
BGND
VCC
V2W to PCM Gain = -9.3 dB, digital gain set to 0dB
0 dBm0, CODEC output voltage = 0.531Vrms
0 dBm0, V2W = 0.7795Vrms
Design Equations
RS = 133.33(ZL - 2RP)
Gain PCM to V2W = RS/RIN = 66.5k/45.3k =1.46
dB Gain =20log (0.7795/ 0.531) = +3.33dB
V2W to PCM Gain = V2W (G2-4)(RF/RA) = (0.7795)(0.416)(30.1k/36.5k) = 0.267
dB Gain =20log (0.267/0.7795) = - 9.3dB
FIGURE 17. ISL5585 3.3V APPLICATION CIRCUIT
22
PCM
TX IN
-IN
RT
RSH
CRS
30.1kΩ
RA
VTX
RING
RRT
CODEC
D1 1N4004
CPS3
PCM
ISL5585
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
2X
L32.7x7
32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VKKC ISSUE C)
0.15 C A
MILLIMETERS
D
A
9
D/2
D1
D1/2
2X
N
6
INDEX
AREA
0.15 C B
1
2
3
E1/2
E
0.15 C B
0.15 C A
B
TOP VIEW
A
/ / 0.10 C
C
0.08 C
SEATING PLANE
9
4X P
0.90
1.00
-
-
0.05
-
A2
-
-
1.00
9
A3
0.20 REF
0.23
0.28
-
9
0.38
5, 8
D
7.00 BSC
-
D1
6.75 BSC
9
4.55
4.70
4.85
7, 8
E
7.00 BSC
-
E1
6.75 BSC
9
4.55
4.70
4.85
0.65 BSC
7, 8
-
k
0.25
-
-
-
L
0.50
0.60
0.75
8
L1
-
-
0.15
10
N
32
2
3
Nd
8
Ne
8
8
P
-
-
0.60
9
NX k
θ
-
-
12
9
D2
7
D2
2 N
3
Rev. 4 8/03
4X P
NOTES:
1
(DATUM A)
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2
3
6
INDEX
AREA
N e
(Ne-1)Xe
REF.
E2
E2/2
NX L
8
0.80
0.10 M C A B
5
NX b
(DATUM B)
A1
A3
SIDE VIEW
NOTES
A
e
A2
MAX
A1
E2
0
4X
TYP
D2
9
2X
2X
MIN
b
E/2
E1
SYMBOL
2. N is the number of terminals.
7
3. Nd and Ne refer to the number of terminals on each D and E.
8
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
9
CORNER
OPTION 4X
(Nd-1)Xe
REF.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
BOTTOM VIEW
A1
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
NX b
5
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
C
L
9. Features and dimensions A2, A3, D1, E1, P & θ are present
when Anvil singulation method is used and not present for saw
singulation.
SECTION "C-C"
C
L
L1
10
L
L1
e
10
L
e
C C
TERMINAL TIP
FOR ODD TERMINAL/SIDE
FOR EVEN TERMINAL/SIDE
23
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
ISL5585
Plastic Leaded Chip Carrier Packages (PLCC)
0.042 (1.07)
0.048 (1.22)
PIN (1) IDENTIFIER
N28.45 (JEDEC MS-018AB ISSUE A)
0.042 (1.07)
0.056 (1.42)
0.004 (0.10)
C
0.025 (0.64)
R
0.045 (1.14)
0.050 (1.27) TP
C
L
D2/E2
C
L
E1 E
D2/E2
VIEW “A”
0.020 (0.51)
MIN
A1
A
D1
D
28 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.165
0.180
4.20
4.57
-
A1
0.090
0.120
2.29
3.04
-
D
0.485
0.495
12.32
12.57
-
D1
0.450
0.456
11.43
11.58
3
D2
0.191
0.219
4.86
5.56
4, 5
E
0.485
0.495
12.32
12.57
-
E1
0.450
0.456
11.43
11.58
3
E2
0.191
0.219
4.86
5.56
4, 5
N
28
28
6
Rev. 2 11/97
SEATING
-C- PLANE
0.020 (0.51) MAX
3 PLCS
0.026 (0.66)
0.032 (0.81)
0.013 (0.33)
0.021 (0.53)
0.025 (0.64)
MIN
0.045 (1.14)
MIN
VIEW “A” TYP.
NOTES:
1. Controlling dimension: INCH. Converted millimeter dimensions are
not necessarily exact.
2. Dimensions and tolerancing per ANSI Y14.5M-1982.
3. Dimensions D1 and E1 do not include mold protrusions. Allowable
mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1
and E1 include mold mismatch and are measured at the extreme
material condition at the body parting line.
4. To be measured at seating plane -C- contact point.
5. Centerline to be determined where center leads exit plastic body.
6. “N” is the number of terminal positions.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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24
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