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ISL5571A
July 2004
FN4920.5
Access High Voltage Switch
Features
The ISL5571A is a solid state device designed to replace the
electromechanical relay used on Subscriber Line Cards. The
device contains two Line Break MOSFET switches, one Ring
Return MOSFET switch and one Ring Access SCR switch.
• Small Size/Surface-Mount Packaging
The ISL5571A is pin-for-pin compatible with the Lucent
L7581AAE LCAS and Clare CPCL7581A Products.
Improvements include: line break switches rON match (0.5
Max) higher dV/dt sensitivity (5000V/s), protection SCR
hold current set to 110mA.
• Low Impulse Noise, Low EMI
• Clean, Bounce-Free Switching
• Line Break Switches
- 0.5Max rON Match
- 28 Max rON
• Built-In Current Limiting, Thermal Shutdown and
Secondary Protection for the SLIC
The line break MOSFETs have very low on resistance
(<16.0Typ) and Ron match (<0.05Typ, 0.5Max) and a
blocking voltage >330V. The Ring Return MOSFET has a
typical Ron of 50and a blocking voltage >330V. The
Ringing Access switch is implemented with a SCR device
with a blocking voltage >480V. The SCR switch inherently
offers low EMI connect and disconnect circuitry. All control
I/Os use TTL thresholds making the device compatible with
3V logic.
• Optimized for Short Loop High REN Applications
The ISL5571A also includes on-chip protection in the form of
an over-voltage clamping circuit, current-limited MOSFET
switches, and thermal shutdown circuitry. The over-voltage
clamping circuit consists of a diode bridge and SCR.
• DLC
• Pb-free Available
Applications
• Central Office
• PBX
• HFC
• FITL
• DAML
Ordering Information
PART
NUMBER
• 3V/5V Logic-Capable I/O
PROT
SCR
TEMP
RANGE (°C)
PACKAGE
TYPE
PKG.
DWG. #
ISL5571AIB
Yes
-40 to 85
16 Ld SOIC
M16.3
ISL5571AIBZ
(Note)
Yes
-40 to 85
16 Ld SOIC
(Pb-free)
M16.3
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J Std-020B.
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Technical Brief TB379 “Thermal Characterization of
Packages for ICs”
• Texas Instruments TISPL758LF3D Data Sheet
• Teccor Electronics Document DO-214AA
Pinout
Add “-T” for tape and reel.
ISL5571A
TOP VIEW
FGND 1
16 VBAT
TBAT
2
15 RBAT
TLINE 3
14 RLINE
NC 4
13 NC
NC 5
12 RRING
TRING 6
1
11 LATCH
VDD 7
10 INPUT
TSD 8
9 DGND
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas LLC 2001, 2002, 2004. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL5571A
Block Diagram
ISL5571A - 16 LEAD SOIC
VBAT
TRING
16
6
LINE BREAK
SW1
TLINE
3
2 TBAT
RING
RETURN
SW3
D1
D3
SCR
RLINE 14
RING
ACCESS
SW4
D2
1 FGND
D4
15 RBAT
LINE BREAK
SW2
7 VDD
CONTROL LOGIC
12
RRING
2
11
10
9
8
LATCH INPUT DGND TSD
ISL5571A
Absolute Maximum Ratings TA = 25°C
Thermal Information
Maximum Supply Voltages
(VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V
(VBAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -19V to -100V
ESD Rating (Human Body Model) . . . . . . . . . . . . . . . . . . . . . . .500V
Thermal Resistance (Typical, Note 1)
Die Characteristics
JA (°C/W)
SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100
Maximum Junction Temperature Plastic . . . . . . . . . . . . . . . . .150°C
Maximum Storage Temperature Range . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300°C
(SOIC - Lead Tips Only)
Substrate Potential. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VBAT
Process . . . . . . . . . . . . . . . . . . . . . . . .6-inch BIMOS Bonded Wafer
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
TA = -40°C to 85°C, Unless Otherwise Specified
TABLE 1. BREAK SWITCHES - ISL5571A - SW1, SW2
PARAMETER
OFF-State Leakage Current:
-40°C
25°C
85°C
ON-Resistance:
-40°C
25°C
85°C
TEST CONDITION
VSWITCH (DIFFERENTIAL) = -310V to GND
VSWITCH (DIFFERENTIAL) = -60V to +250V
VSWITCH (DIFFERENTIAL) = -320V to GND
VSWITCH (DIFFERENTIAL) = -60V to +260V
VSWITCH (DIFFERENTIAL) = -330V to GND
VSWITCH (DIFFERENTIAL) = -60V to +270V
TLINE = 10mA, 40mA, TBAT = -2V
TLINE = 10mA, 40mA, TBAT = -2V
TLINE = 10mA, 40mA, TBAT = -2V
MEASURE
MIN
TYP
MAX
UNITS
ISWITCH
-
-
1
A
ISWITCH
-
-
1
A
ISWITCH
-
-
1
A
VON
VON
VON
-
12
16
-
28



0.05
0.5

-
-
220
VPeak
ON-Resistance Match
Per ON-resistance Test Condition of SW1, SW2 Magnitude
rON SW1 - rON SW2
ON-State Voltage (Note 2)
Break Switches in ON-State; Iswitch = ILIMIT at
50/60Hz
VON
VSWITCH (ON) = 10V
VSWITCH (ON) = 10V
VSWITCH (ON) = 10V
ISWITCH
ISWITCH
ISWITCH
80
125
-
250
-
mA
mA
mA
Break Switches in ON-state; Ringing Access
Switches OFF; Apply 1000V at 10/1000s
Pulse; Appropriate External Secondary
Protection in Place
ISWITCH
-
1.5
2.0
A
VSWITCH (Both Poles) = 310V
Logic Inputs = GND
VSWITCH (Both Poles) = 320V
Logic Inputs = GND
VSWITCH (Both Poles) = 330V
Logic Inputs = GND
ISWITCH
-
-
1
A
ISWITCH
-
-
1
A
ISWITCH
-
-
1
A
-
5000
-
V/s
DC Current Limit:
-40°C
25°C
85°C
Dynamic Current Limit
(t = <0.5s)
Isolation:
-40°C
25°C
85°C
dV/dt Sensitivity (Note 3)
NOTES:
2. Choice of secondary protection should ensure this rating is not exceeded.
3. Applied voltage is 100VP-P square wave at 100Hz.
3
ISL5571A
TABLE 2. RING RETURN SWITCH - ISL5571A - SW3
PARAMETER
OFF-State Leakage Current:
-40°C
25°C
85°C
DC Current Limit
-40°C
TEST CONDITION
MEASURE
MIN
TYP
MAX
UNIT
S
VSWITCH (DIFFERENTIAL) = -310V to GND
VSWITCH (DIFFERENTIAL) = -60V to +250V
VSWITCH (DIFFERENTIAL) = -320V to GND
VSWITCH (DIFFERENTIAL) = -60V to +260V
VSWITCH (DIFFERENTIAL) = -330V to GND
VSWITCH (DIFFERENTIAL) = -60V to +270V
ISWITCH
-
-
1
A
ISWITCH
-
-
1
A
ISWITCH
-
-
1
A
VSWITCH (ON)
ISWITCH
-
-
350
mA
VSWITCH (ON)
VSWITCH (ON)
ISWITCH
-
200
-
mA
ISWITCH
120
-
-
mA
Dynamic Current Limit
(t = <0.5s)
Break Switches in OFF-State; Ringing Access Switches ON;
Apply 1000V at 10/1000s Pulse; Appropriate External
Secondary Protection in Place
ISWITCH
-
1.5
2.0
A
ON-Resistance
TLINE = 0, 10mA
VON
-
-
100

ON-State Voltage (Note 4)
Ring Return Switch in ON-State; Iswitch = ILIMIT at 50/60Hz
VON
-
-
130
VPeak
VSWITCH (Both Poles) = 310V
Logic Inputs = GND
VSWITCH (Both Poles) = 320V
Logic Inputs = GND
VSWITCH (Both Poles) = 330V
Logic Inputs = GND
ISWITCH
-
-
1
A
ISWITCH
-
-
1
A
ISWITCH
-
-
1
A
-
5000
-
V/s
25°C
85°C
Isolation:
-40°C
25°C
85°C
dV/dt Sensitivity (Note 5)
NOTES:
4. Choice of secondary protection should ensure this rating is not exceeded.
5. Applied voltage is 100VP-P square wave at 100Hz.
TABLE 3. RING ACCESS SWITCH - ISL5571A - SW4
PARAMETER
OFF-State Leakage Current:
-40°C
TEST CONDITION
MEASURE
MIN
TYP
MAX
UNITS
VSWITCH (DIFFERENTIAL) = -245V to +210V
VSWITCH (DIFFERENTIAL) = +245V to -210V
VSWITCH (DIFFERENTIAL) = -255V to +210V
VSWITCH (DIFFERENTIAL) = +255V to -210V
VSWITCH (DIFFERENTIAL) = -270V to +210V
VSWITCH (DIFFERENTIAL) = +270V to -210V
ISWITCH
-
-
1
A
ISWITCH
-
-
1
A
ISWITCH
-
-
1
A
ON-Resistance
ISWITCH (ON) = 70mA, 80mA
VON
-
-
12

ON Voltage
ISWITCH (ON) = 1mA
VON
-
-
3
V
Ring Access Switch Quiescent
Current During Ringing
VCC = 5V, Ring Access Switches On, All Other
Switches Off
IRING QUIESCENT
(Note 6)
-
2.0
-
mA
mA
25°C
85°C
Steady State Current (Note 7)
Surge Current (Note 7)
-
-
150
-
-
2
A
200
-
1000
A
ISWITCH
-
-
1
A
ISWITCH
-
-
1
A
ISWITCH
-
-
1
A
-
5000
-
V/s
Ring Access Switch On, Time Duration = 100s
Release Current
Isolation:
-40°C
25°C
85°C
VSWITCH (Both Poles) = 310V
Logic Inputs = GND
VSWITCH (Both Poles) = 320V
Logic Inputs = GND
VSWITCH (Both Poles) = 330V
Logic Inputs = GND
dV/dt Sensitivity (Note 8)
NOTES:
6. Magnitude of the ring generator current not supplied to the ring load. IRING QUIESCENT= IRING GEN - IRING LOAD.
7. Choice of secondary protector and series current-limit resistor should ensure these ratings are not exceeded.
8. Applied voltage is 100VP-P square wave at 100Hz.
4
ISL5571A
TABLE 4. LOGIC I/O ELECTRICAL CHARACTERISTICS - ISL5571A
PARAMETER
TEST CONDITION
Digital Input Characteristics:
Input Low Voltage
Input High Voltage
Input Leakage Current (High)
Input Leakage Current (Low)
MEASURE
VDD = 5.5V, VBAT = -75V, VLOGIC-IN = 5V
VDD = 5.5V, VBAT = -75V, VLOGIC-IN = 0V
MIN
TYP
MAX
UNITS
2.4
-
-
0.8
1
1
V
V
A
A
MIN
TYP
MAX
UNITS
IDD, IBAT
IDD, IBAT
IDD
-
6.6
8.8
11.0
8.5
11.5
18.2
mW
mW
mW
IDD
IDD
IDD
-
1.2
1.6
2.0
2.0
2.1
3.3
mA
mA
mA
IBAT
IBAT
IBAT
-
1.0
1.0
1.0
10
10
10
A
A
A
115
7
125
14
135
21
°C
°C
ILOGIC-IN
ILOGIC-IN
TABLE 5. LOGIC I/O POWER REQUIREMENTS - ISL5571A
PARAMETER
TEST CONDITION
Power Requirements:
Power Dissipation
VDD = 5.5V, VBAT = -48V,
Idle/Talk State
All OFF-State
Ringing State
VDD = 5.5V,
Idle/Talk State
All OFF-State
Ringing State
VBAT = -48V,
Idle/Talk State
All OFF-State
Ringing State
VDD Current
VBAT Current
Temp. Shutdown Requirements (Note 9)
Shutdown Activation Temperature
Shutdown Circuit Hysteresis
MEASURE
TJ
NOTE:
9. The Temperature Shutdown logic pin (TSD) will be high during normal operation and low during temperature shutdown state.
TABLE 6. ELECTRICAL SPECIFICATION - PROTECTION CIRCUITRY - ISL5571A
PARAMETER
TEST CONDITION
MEASURE
MIN
TYP
MAX
UNITS
Forward Voltage
-
-
3
V
Voltage Drop at Surge Current Apply Dynamic Current Limit of Break Switches Forward Voltage
-
5
-
V
-
-
4
A
-
50
-
mA
110
-
VBAT - 4V
-
VBAT - 2V
V
PARAMETERS RELATED TO DIODES
Voltage Drop at Continuous
Current (50Hz/60Hz)
Apply DC Current Limit of Break Switches
PARAMETERS RELATED TO PROTECTION SCR
Surge Current
Twice Dynamic Current Limit of Break Switches
Gate Trigger Current
-VBAT Current
Hold Current
mA
Gate Trigger Voltage
Trigger Current
Reverse Leakage Current
VBAT
-
-
1.0
A
ON-state Voltage (Note 10)
0.5A, t = 0.5s
2.0A, t = 0.5s
-
-3
-5
-
V
V
NOTES:
10. In some instances, the typical ON-state voltage can range as low as -25V.
TABLE 7. POWER SUPPLY SPECIFICATIONS
SUPPLY
MIN
TYP
MAX
UNITS
VDD
4.5
-
5.5
V
VBAT
-19
-
-72
V
5
ISL5571A
TABLE 8. PIN DESCRIPTIONS - ISL5571A
PIN
NO.
PIN
NAME
PIN
NO.
PIN
NAME
1
FGND
Fault Ground. Internally, this pin is electrically isolated
from DGND.
16
VBAT
Battery Voltage. Used as a reference for
protection circuit. Provides Trigger
current for the protection SCR.
2
TBAT
Connect to TIP on SLIC side.
15
RBAT
Connect to RING on SLIC side.
3
TLINE
Connect to TIP on line or phone side.
14
RLINE
Connect to RING on line or phone side.
4
NC
No Connection.
13
NC
5
NC
No Connection.
12
RRING
Connect to ringing generator.
6
TRING
Connect to Return Ground for Ringing Generator.
11
LATCH
Logic State Latch Control, active-high,
transparent low.
7
VDD
+5V supply.
10
INPUT
Logic Level Input Switch Control.
8
TSD
Temperature Shutdown Pin. Can be used as a logic level
input or output. See Truth Table. As an output, will read
+5V when device is in its operational mode and 0V in the
thermal shutdown mode. In the ISL5571A, the thermal
shutdown mechanism cannot be disabled.
9
DGND
Digital Ground. Internally, this pin is
electrically isolated from FGND.
DESCRIPTION
DESCRIPTION
No Connection.
Pinout
ISL5571A
TOP VIEW
- 48 VDC
TRING
VBAT
6
TIP
TLINE
R1
TBAT
2
D3
SCR
D2
RRING
†
RING RING LINE BREAK
SW2
ACCESS
SW4
RLINE
R2
TLINE EXTERNAL PROTECTOR MAXIMUM
VOLTAGE PRIOR TO SWITCHING TO THE
ON STATE SHOULD NOT EXCEED 130V.
RLINE EXTERNAL PROTECTOR MAXIMUM
VOLTAGE PRIOR TO SWITCHING TO
THE ON STATE SHOULD NOT EXCEED 220V.
12
11
RGEN
LATCH
RBAT
D4
RING
7
CONTROL LOGIC
GND
VDD
10
9
8
INPUT
DGND
TSD
RING
GENERATOR
BATTERY
FIGURE 1. APPLICATION CIRCUIT
6
SLIC
1
15
14
TIP
FGND
EXTERNAL
CROWBAR
PROTECTION †
†
VBAT
3
TIP LINE BREAK
SW1
D1
RING
16
RING
RETURN
SW3
RRLY
+ 5 VDC
ISL5571A
TABLE 9. TRUTH TABLE - ISL5571A
LOGIC INPUTS
SWITCH CONDITION
RING LINE BREAK
SWITCH
RINGING
RETURN
SWITCH
RING ACCESS
SWITCH
LATCH
INPUT
TSD
TIP LINE BREAK
SWITCH
IDLE / TALK
0
0
1 or Floating (Note 11)
ON
ON
OFF
OFF
POWER RINGING
0
1
1 or Floating (Note 11)
OFF
OFF
ON
ON
IDLE / TALK
LATCHED (Note 12)
1
0
1 or Floating (Note 11)
ON
ON
OFF
OFF
POWER RINGING
LATCHED (Note 12)
1
1
1 or Floating (Note 11)
OFF
OFF
ON
ON
All OFF
X
X
0 (Note 13)
OFF
OFF
OFF
OFF
LOGIC STATE
NOTES:
11. Thermal shutdown mechanism is active with TSD floating or equal to 5V.
12. If the LATCH pin is low, the logic state of the device is controlled by the INPUT pin. When the LATCH pin goes high, the current logic state is
latched. As long as the LATCH pin is held high, the device will no longer respond to any changes applied to the INPUT control pin. The state of
the device will be permanently latched until the LATCH pin is taken low.
13. Setting TSD to a logic low overrides the LATCH and INPUT logic pins and forces all switches to turn OFF.
Circuit Operation and Design Information
Introduction
The ISL5571A was designed to be used in subscriber line
card applications. A typical application circuit is shown in
Figure 1. Its main purpose is to momentarily disconnect the
voice circuit (SLIC and CODEC) and connect an external
ring generator to ring the phone. This function has been
traditionally done by electromechanical relays. The
ISL5571A offers the system designer a solid-state switching
solution with distinct advantages over the electromechanical
relay. These advantages are as follows:
• Lower power consumption (20mW vs. 150mW for the
relay)
• Smaller size, surface mounted package
• Bounce-Free switching
• Lower impulse noise, Low EMI
• Longer life
• Provides current limiting, thermal shutdown, and overvoltage protection for the SLIC and CODEC
Their bounce-free operation, long lifetime, small size, and
low power consumption make the solid-state access switch
the preferred choice over electromechanical relays
whenever board area, high reliability, and heat reduction are
primary concerns.
The ISL5571A was designed to be a drop in replacement for
the Lucent ATTL7581AAE LCAS device. The Intersil
ISL5571A offers superior rON matching between the line
break switches for optimal longitudinal balance, higher
temperature operation (enabling continuous operation in
7
short loop, high Ringer Equivalency Number applications)
and with 3V TTL logic controlled inputs.
Basic Functional Description
This section describes the basic operation of the ISL5571A.
From the application circuit shown in Figure 1, the ISL5571A
consists of four switches, the Line Break switches (SW1,
SW2), the Ring Return switch (SW3), and the Ring Access
switch (SW4). The Line Break switches (SW1 and SW2)
open and close in unison to connect and disconnect the
voice / data signal from the phone. The Ring Access switch
and the Ring Return switch (SW3 and SW4) open and close
in unison, to connect and disconnect the external ring
generator to the phone.
The ISL5571A has three possible operating states: the Idle /
Talk state, the Power Ringing state, and the All OFF state. It
also has a built in Logic State Latch. The Logic State Latch
enables the user to latch the logic state of the ISL5571A in
either the Idle / Talk state or the Power Ringing state.
The three control logic pins for the ISL5571A are the INPUT
pin, the TSD pin and the LATCH pin. These logic pins are
controlled by TTL logic levels (0V - 0.8V for logic low and
2.4V - 5.0V for logic high). The combination of the logic
levels applied at these pins determine which of the three
logic states the device will be in and whether the Logic State
Latch is active. The truth table for the ISL5571A is shown in
Table 9. A description of each operating state and the control
logic pins follows:
ISL5571A
Idle / Talk State (LATCH = 0, INPUT = 0, TSD = 1 or
Floating)
In this state the Line Break switches (SW1 and SW2) are
closed (on) and the Ring Return and Ring Access switches
(SW3 and SW4) are open (off). The subscriber line circuit is
either on-hook or off-hook:
1. In the on-hook condition, the SLIC is monitoring the Tip
and Ring lines through the Line Break switches for an offhook condition. This is called the Idle state.
the LATCH pin is taken low the device will again be under
the control of the INPUT pin and the switches will
immediately go to the state specified by the logic level at the
INPUT pin. (Note: The TSD pin overrides the LATCH pin and
the INPUT pin. When the TSD pin is low the ISL5571A goes
to the ALL OFF state regardless of the logic levels applied at
the LATCH pin and the INPUT pin.)
ISL5571A
2. In the off-hook condition, a telephone conversation
between two or more parties is in progress or data is
being transferred between modems. This is called the
Talk state. The SLIC is providing DC power through the
Line Break switches to the telephone handset for
modulation. Modulated AC voice signals or data are
traveling through the Line Break switches SW1 and SW2.
SWITCHES
LOGIC
CONTROL
CIRCUITRY
LOGIC
STATE
LATCH
10 INPUT
8
TSD
Power Ringing State (LATCH = 0, INPUT = 1, TSD = 1
or Floating)
In this state the Line Break switches (SW1 and SW2) are
open (off) and the Ring Return and Ring Access switches
(SW3 and SW4) are closed (on). For ring injected ringing as
shown in Figure 1, a ring generator is connected to the
phone through the Ring Access switch (SW4) and returned
to ground through the Ring Return switch (SW3).
All OFF State (LATCH = X, INPUT = X, TSD = 0)
In this state both the Line Access switches (SW1 and SW2)
and the Ring Return and Ring Access switches (SW3 and
SW4) are open (off). The ISL5571A will enter the All Off
state when the following conditions occur:
11
LATCH
FIGURE 2. BLOCK DIAGRAM OF LOGIC CONTROL
INPUT Pin
The INPUT pin (pin 10) is the main logic input control pin.
Reference Table 9 for logic state table. When the LATCH pin
is low and the TSD pin is high or floating, you can toggle
back and forth between the Idle / Talk state and the Power
Ringing state by changing the logic level at the INPUT pin.
This is the normal operating mode of the device.
NOTE:
1. The TSD pin is used as a control input and is
programmed to logic low.
The TSD pin overrides all other logic pins. If the
TSD pin is low, the device will enter an All OFF
state and will no longer respond to logic
changes at the INPUT pin.
2. The device has enter thermal shutdown due to a fault
condition. (Thermal Shutdown is described in the
Auxiliary Functions and Features section below.)
3. If VBAT rises above -10V or disappears.
While in the All OFF state, communication and power ringing
are inoperable because all the ISL5571A switches are open
(off).
Logic State Latch (LATCH = 1, TSD = 1 or floating,
INPUT = 0 or 1)
A Logic State Latch is Integrated into the ISL5571A, see
Figure 2. If the LATCH control pin is high and the TSD pin is
high or floating, the device will no longer respond to logic
level changes at the INPUT pin. The state of the switches
will be determined by the logic level of the INPUT pin at the
time the LATCH pin transitions from logic low to logic high.
The state of the switches at the time of this transition will be
permanently held as long as the LATCH pin is high. When
8
If the LATCH pin is high, the INPUT pin is no
longer active and the device will no longer
respond to logic changes at the INPUT pin.
Latch Pin
The LATCH pin (pin 11) is the control for the Logic State
Latch. Reference Table 9 for logic state table. When the
LATCH pin is low, the latch is disabled and the state of the
ISL5571A will be determined by the logic level applied at the
other logic inputs.
When the LATCH pin is high, the latch is active and the logic
state of the switches at the time the LATCH pin went high will
be latched. As long as the LATCH pin is held high the
switches will not respond to logic changes at the INPUT
control pin.
ISL5571A
TSD Pin
+I
The TSD pin (pin 8) can be used as a logic level input or
output. Reference Table 9 for logic state table. The TSD pin
overrides all other logic pins.
2/3 rON
As an input, if this pin is driven low, either by external logic
applied to it or by the internal thermal shutdown circuitry, the
ISL5571A device will enter the All OFF state. In the All OFF
state all switches of the ISL5571A are open (off).
As an output, it is capable of driving a TTL input (2.8V at
200A). The TSD pin will read +5V when the device is in
normal operating mode and 0V when the device is in thermal
shutdown. This pin can be monitored on an oscilloscope to
determine if the ISL5571A device has enter thermal
shutdown. (Thermal Shutdown is described in the Auxiliary
Functions and Features section below.)
Connecting the TSD pin to 5V will have no effect on the
performance of the ISL5571A device and will not disable the
thermal shutdown circuitry.
CURRENT
LIMITING
ILIMIT
rON
-1.5
-V
+1.5
rON
+V
2/3 rON
ILIMIT
CURRENT
LIMITING
-I
FIGURE 3. ON STATE V-I GRAPH OF SW1, SW2 AND SW3
Auxiliary Functions and Features
+I
In addition to the ISL5571A main function of momentarily
connecting and disconnecting an external ring generator to
ring the phone, the ISL5571A device also provides surge
and power-cross protection to the SLIC and CODEC. This
fault protection is provided by a combination of currentlimiting circuitry, a thermal shutdown mechanism and an
over-voltage clamping circuit. Another feature the device
offers is a VBAT fault detection circuit. The following
describes each in detail.
T1
T2
-V
+V
T2
Current Limiting
The Line Break switches (SW1 and SW2) and the Ring
Return switch (SW3) are all current-limited. These switches
have a DC current limiting response and a dynamic current
limiting response which were built into the device to provide
protection during lightning and power-cross faults. Each of
these current limiting responses are explained below.
DC CURRENT LIMITING RESPONSE
The ON state V-I Graph for SW1, SW2, and SW3 is shown in
Figure 3. It represents the DC current limiting response of
the switches. The graph shows that over a certain range of
positive and negative voltages, the current and voltage
relationship is linear and behaves according to Ohms law
(V = IR). Note: At around 1.5V an inflection point occurs
decreasing the on resistance by 2/3. The on resistance
specified in the data sheet is measured in the region prior to
the inflection point (between 1.5V).
When current through the switch reaches the current limit of
the switch, the current is clamped and held at a constant
value. The switch then operates as a constant current
source. Increasing the voltage beyond this point will not
change the value of the current.
9
T1
T2 > T1
-I
FIGURE 4. EFFECT OF TEMPERATURE ON DC CURRENT
LIMIT
+I
2A
0
0.5s
TIME
FIGURE 5. DYNAMIC CURRENT LIMIT RESPONSE
ISL5571A
The DC current limiting response has a negative
temperature coefficient. As the temperature of the device
increases the DC current limit of the switch will decrease.
This is illustrated in Figure 4.
Figure 4 shows the V-I curves of a switch at two different die
temperatures, T1 and T2. In this illustration T2 is greater in
temperature than T1. This shows that when a switch is
driven into current limit and held there, the current limit will
decrease over time as the switch temperature increases. If
the power through the switch is great enough, the
temperature of the switch will continue to increase until the
switch goes into thermal shutdown (Thermal Shutdown is
described below).
Dynamic Current Limiting Response
The DC current limit response described above pertains to
DC and AC voltage sources applied across the switches.
The dynamic response is the response of the current limit
circuit to a fast or high dv/dt pulse. The dynamic response
would be seen, for example, during a lightning surge
Figure 5 shows the dynamic response that is observed when
SW1, SW2 or SW3 is surged with a 1000V at 10/1000s
telecom surge pulse. (Note: This surge test is done with the
switch in the on state and with the appropriate external
secondary protection in place.) The dynamic current limit of
SW1, SW2 or SW3 will limit the current through the switch to
less than 2.0A for 0.5s as shown in Figure 5. Once the
switch has turned off, the voltage at the TLine and RLine
terminals will increase to a point where the external
secondary protection device will trigger and crowbar the
voltage at TLine and RLine to a low voltage, protecting the
ISL5571A against damage.
Since the Line Break switches (SW1, SW2) have this
dynamic current limit feature, the internal over-voltage
protection clamping circuit of the ISL5571A device will need
to only protect the SLIC against a 2.0A 0.5s pulse during a
lightning surge.
Thermal Shutdown (TSD)
The ISL5571A has a built in thermal shutdown protection
circuit. The thermal shutdown protection mechanism is
invoked if a fault condition causes the junction temperature
of the die to exceed about 150°C. Once the thermal limit is
exceeded the thermal shutdown circuitry will force the
switches into an All OFF state, regardless of the logic inputs.
While in thermal shutdown the TSD logic pin (pin 11) will be
driven low by the thermal shutdown circuit. (Note: During
normal operation the TSD pin is high.) The thermal
shutdown mechanism was designed to have a thermal
hysteresis of about 12°C. Once in thermal shutdown the
device will begin to cool down, because all the switches are
off and no current flows. When the temperature of the die
cools to about 138°C the ISL5571A will cycle out of thermal
shutdown and the switches will close again. If the fault
10
condition is still present, the temperature of the die will again
increase and this cycle will be repeated.
Over Voltage Protection Clamping Circuit
The ISL5571A contains an over-voltage clamping circuit on
the SLIC side of the Line Break switches, see Figure 1. This
clamping circuit consists of a diode bridge and SCR. During
lightning surges and power-cross fault conditions this circuit
will clamp the voltage at the TBAT and RBAT terminals of the
SLIC to a safe level and will shunt harmful currents to ground
away from the SLIC.
The clamping circuit is externally connected to ground
through the FGND pin (pin 1) of the device. The battery
voltage of the SLIC is connected to the clamping circuit
through the VBAT pin (pin 16) of the device. The operation of
diode bridge and the SCR circuit is described below.
DIODE BRIDGE WITH SCR (ISL5571A)
During a positive lightning surge or during the positive cycle
of a power-cross / induction fault, the voltage at the TBAT
and RBAT terminals of the SLIC will be clamped to a diode
drop above ground. The fault current will flow harmlessly
through diodes D1 and D2 of the diode bridge to ground (see
Figure 1).
During a negative lightning surge or during the negative
cycle of a power-cross / induction fault when the voltage at
the TBAT and RBAT terminals reach 2V to 4V more negative
than the VBAT voltage, the protection SCR will trigger and
turn on. When the SCR turns on and latches, it will crowbar
the voltage at the TBAT and RBAT lines to a low-voltage
state, approximately 3 diode drops below ground. This lowvoltage on state will cause the current resulting from the over
voltage to be safely direct to ground through diodes D3 and
D4 of the diode bridge and the SCR (see Figure 1). Once the
fault current decrease below the protection SCR holding
current (110mA) the SCR will turn off and the SLIC will be
able to return to normal operation.
VBAT Fault Circuit Protection - Loss of Battery
Voltage
The ISL5571A device contains a VBAT fault circuit which
monitors the SLIC battery voltage (VBAT). When this circuit
detects that the VBAT voltage has risen above -10V, it will
cause the ISL5571A to enter the All OFF state. All the
switches will remain off (open) until the circuit detects that
the SLIC battery voltage has dropped below -15V.
Design Considerations
External Protection
Subscriber line card circuits using the ISL5571A require the
use of an external protection circuit on the loop side or
phone side of the device, see Figure 1. This protection is
required to minimize the power stress on the ISL5571A
during overvoltage and overcurrent conditions. When the
proper external protection circuitry is used in conjunction
ISL5571A
with the integrated secondary protection, features offered by
the ISL5571A, the application circuit will pass the AC powercross and lightning immunity tests of the following regulatory
requirements:
• GR 1089-CORE
Ringing state to the Idle / Talk state. There is a period of time
that can be as much as 25ms (1/2 cycle of the 20Hz ring
signal) when both SW2 and SW4 will both be on (closed).
This occurs because SW4 is an SCR and requires a zero
current crossing to turn off.
Protection SRC Latch-Up
• ITU-T K.20
This section will discuss the issues that must be considered
when designing an external protection circuit for use with the
ISL5571A.
The external protection circuitry should be designed to limit
the peak voltages on the TLine and RLine terminals of the
ISL5571A. The most potentially stressful condition concerning
the ISL5571A is low level power-cross when the ISL5571A
switches are closed. Under this condition, the external
protection circuitry limits the voltage and corresponding power
dissipation until the ISL5571A thermal shutdown circuitry
opens the switches.
The external protector chosen for the TLine terminal
must limit at a maximum of 130V thereby limiting the
power stress on the Ring Return switch (SW3).
The protector chosen for the RLine terminal must limit at a
maximum of 220V thereby limiting the power stress on the
Line Break switch (SW2). The 220V break-over voltage of the
protector on RLine is large enough to not interfere with the AC
ring signal during ringing.
Texas Instruments and Teccor Electronics have designed
specific parts to protect solid state line card access switches.
The following protectors are recommended:
Texas Instruments Part Number TISPL758LF3D(TLine
and RLine)
Teccor Electronics Part Number P1200SC (TLine) and
P2000SC (RLine)
Refer to the above company’s data sheets for information on
their parts and reference designs for protection of solid state
line card access switches, see Related Literature section on
Page One.
Break-Before-Make Operation
The ISL5571A device inherently has a Break-before-Make
condition between the following switches:
a. Between the Line Break switch SW1 and the Ring
Return switch SW3 during the transition from the Idle
state to the Power Ringing state.
b. Between the Line Break switch SW2 and the Ring
Access switch SW4 during the transition from the
Idle state to the Power Ringing state.
Make-Before-Break Operation
The ISL5571A device could exhibit a Make-before-Break
condition between the Line Break switch SW2 and the Ring
Access switch SW4 during the transition from the Power
11
In the Make-before-Break condition, when transiting from the
Power Ringing state to the Idle/ Talk state, during the negative
cycle of the ring generator it is possible for enough current to
flow that the protection SCR will turn on. This will result in
shorting the ring generator and the Ring terminal of the SLIC
to ground. When either SW2 or SW4 turns off, the Ring
terminal of the SLIC will remain shorted to ground unless the
output current limit of the SLIC is less than the holding current
(110mA) of the protection SCR. The current limit of most
SLICs are set well below the 110mA minimum holding current
of the ISL5571A protection SCR and therefore should not be a
concern. Another method to prevent latch-up of the protection
SCR would be to strobe the TSD pin of the ISL5571A. as
discussed in Break-Before-Make section.
Ring Access Switch Quiescent Current During
Ringing
The Ring Access switch (SW4) is a silicon control rectifier
type switch (SCR). During power ringing, the Ring Access
switch will draw a nominal 2mA of current from the ring
generator. This current is called IRING QUIESCENT and is
equal to:
IRING QUIESCENT = IRING GEN - IRING LOAD .
System designers need to ensure that this additional current
can be provided by the ring generator.
Glossary of Acronyms
AC = Alternating Current
BIMOS = Bipolar Metal-Oxide Semiconductor
CO = Central Office
CODEC = CODer-DECoder
DC = Direct Current
DLC = Digital Loop Carrier
DAML = Digitally Added Main Line
EMI = Electromagnetic Interference
ESD = Electrostatic Discharge
FITL = Fiber in the Loop
HFC = Hybrid Fiber Coax
ICs = Integrated Circuits
LCAS = Line Card Access Switch
PBX = Private Branch Exchange
REN = Ring Equivalency Number
MOSFET = Metal-Oxide Semiconductor Field-Effect Transistor
SCR = Silicon Control Rectifier
SLIC = Subscriber Line Interface Circuit
SMDs = Surface Mount Devices
SOIC = Small Outline Integrated Circuit
TSD = Thermal ShutDown
TTL = Transistor-Transistor Logic
ISL5571A
Small Outline Plastic Packages (SOIC)
N
INDEX
AREA
0.25(0.010) M
H
M16.3 (JEDEC MS-013-AA ISSUE C)
B M
16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
E
INCHES
-B-
1
2
SYMBOL
3
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
µ
e
A1
B
0.10(0.004)
0.25(0.010) M
C A M
B S
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
MILLIMETERS
MIN
MAX
NOTES
A
0.0926
0.1043
2.35
2.65
-
0.0040
0.0118
0.10
0.30
-
B
0.013
0.0200
0.33
0.51
9
C
0.0091
0.0125
0.23
0.32
-
D
0.3977
0.4133
10.10
10.50
3
E
0.2914
0.2992
7.40
7.60
4
0.050 BSC
1.27 BSC
-
H
0.394
0.419
10.00
10.65
-
h
0.010
0.029
0.25
0.75
5
L
0.016
0.050
0.40
1.27
6
8o
0o
N
NOTES:
MAX
A1
e
C
MIN

16
0o
16
7
8o
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm (0.024
inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
12
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