DATASHEET

®
R
HC-5502B
UC T
R O D C E M EN T
P
E
T
A
OL E
EP L
O B S N D ED R B
ME
504
Data
COMSheetHC5
E
August 2003
FN2884.7
EIA/ITU PABX SLIC with 30mA Loop Feed
Features
The Intersil SLIC incorporates many of the BORSHT
functions on a single IC chip. This includes DC battery feed,
a ring relay driver, supervisory and hybrid functions. This
device is designed to maintain transmission performance in
the presence of externally induced longitudinal currents.
Using the unique Intersil dielectric isolation process, the
SLIC can operate directly with a wide range of station battery
voltages.
• Capable of 12V or 5V (VB+) Operation
The SLIC also provides selective denial of power. If the PBX
system becomes overloaded during an emergency, the SLIC
will provide system protection by denying power to selected
subscriber loops.
The Intersil SLIC is ideally suited for the design of new digital
PBX systems, by eliminating bulky hybrid transformers.
Part Number Information
PART NUMBER
TEMP. RANGE
(oC)
• Monolithic Integrated Device
• DI High Voltage Process
• Compatible With Worldwide PBX Performance
Requirements
• Controlled Supply of Battery Feed Current for Short Loops
(30mA)
• Internal Ring Relay Driver
• Low Power Consumption During Standby
• Switch Hook, Ground Key and Ring Trip Detection
Functions
• Selective Denial of Power to Subscriber Loops
Applications
PACKAGE
PKG. DWG. #
• Solid State Line Interface Circuit for Analog and Digital
PBX Systems
HC3-5502B-5
0 to 75
24 Ld PDIP
E24.6
• Direct Inward Dial (DID) Trunks
HC4P5502B-5
0 to 75
28 Ld PLCC
N28.45
• Voice Messaging PBXs
• Related Literature
- AN549, The HC-5502S/4X Telephone Subscriber Line
Interface Circuits (SLIC)
- AN571, Using Ring Sync with HC-5502A and HC-5504
SLICs
Pinouts
22 C4
C1*
4
21 RX
C3
5
2
C4
3
3
AG
VB+
4
N/C
23 AG
TX
24 TX
2
TIP
1
RING
TIP
RING
HC-5502B (PLCC)
TOP VIEW
VB+
HC-5502B (PDIP)
TOP VIEW
1
28
27
26
C1†
5
25 RX
20 +IN
C3
6
24 +IN
7
23 -IN
DG
6
19 -IN
DG
N/C
8
22 N/C
RS
9
21 OUT
RF 10
15 PD
VB- 11
14 GKD
BG 12
13 SHD
1
RD 10
20 C2
TF 11
19 RC
12
13
14 15
16
17
18
PD
16 RC
SHD
9
GKD
TF
N/C
17 C2
BG
18 OUT
8
VB-
7
RF
RS
RD
† OPTIONAL
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
HC-5502B
Absolute Maximum Ratings (Note 1)
Thermal Information
Supply Voltage
(VB-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -60 to 0.5V
(VB+) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 15V
(VB+ - VB-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75V
Relay Drive Voltage (VRD). . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 15V
Thermal Resistance (Typical, Note 2)
Operating Conditions
Relay Driver Voltage (VRD) . . . . . . . . . . . . . . . . . . . . . . . . 5V to 12V
Positive Supply Voltage (VB+) . . . 4.75V to 5.25V or 10.8V to 13.2V
Negative Supply Voltage (VB-) . . . . . . . . . . . . . . . . . . . -42V to -58V
High Level Logic Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 2.4V
Low Level Logic Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6V
Loop Resistance (RL) . . . . . . . . . . . . . . . . . . . . . . . . . 200 to 1200Ω
Operating Temperature Range
HC-5502B-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
65
PLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
65
Maximum Junction Temperature (Hermetic Package) . . . . . .175oC
Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(PLCC - Lead Tips Only)
Die Characteristics
Transistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Diode Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Die Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . .137 mils x 102 mils
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VBProcess . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bipolar-DI
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Absolute maximum ratings are limiting values, applied individually, beyond which the serviceability of the circuit may be impaired.
Functional operability under any of these conditions is not necessarily implied.
2. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
Unless Otherwise Specified, VB- = -48V, VB+ = 12V and 5V, AG = BG = DG = 0V, Typical Parameters
TA = 25oC. Min-Max Parameters are Over Operating Temperature Range
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
On Hook Power Dissipation
ILONG = 0, VB+ = 12V (Note 3)
-
135
235
mW
Off Hook Power Dissipation
RL = 600Ω, ILONG = 0, VB+ = 12V (Note 3)
-
450
690
mW
Off Hook IB+
RL = 600Ω, ILONG = 0, TA = -40oC (Note 3)
-
-
6.0
mA
Off Hook IB+
RL = 600Ω, ILONG = 0, TA = 25oC (Note 3)
-
-
5.3
mA
Off Hook IB-
RL = 600Ω, ILONG = 0 (Note 3)
-
-
39
mA
Off Hook Loop Current
RL = 1200Ω, ILONG = 0 (Note 3)
-
21
-
mA
Off Hook Loop Current
RL = 1200Ω, VB- = -42V, ILONG = 0, TA = 25oC
(Note 3)
17.5
-
-
mA
Off Hook Loop Current
RL = 200Ω, ILONG = 0 (Note 3)
25.5
30
34.5
mA
TIP to Ground
-
14
-
mA
RING to Ground
-
47
-
mA
TIP to RING
-
30
-
mA
TIP and RING to Ground
-
47
-
mA
Fault Currents
Ring Relay Drive VOL
IOL = 62mA
-
0.2
0.5
V
Ring Relay Driver Off Leakage
VRD = 12V, RC = 1 = HIGH, TA = 25oC
-
-
100
µA
Ring Trip Detection Period
RL = 600Ω, TA = 25oC
-
2
3
Ring Cycles
Switch Hook Detection Threshold
SHD = VOL
10
-
-
mA
SHD = VOH
-
-
5
mA
2
HC-5502B
Electrical Specifications
Unless Otherwise Specified, VB- = -48V, VB+ = 12V and 5V, AG = BG = DG = 0V, Typical Parameters
TA = 25oC. Min-Max Parameters are Over Operating Temperature Range (Continued)
PARAMETER
TEST CONDITIONS
Ground Key Detection Threshold
Loop Current During Power Denial
MIN
TYP
MAX
UNITS
GKD = VOL
20
-
-
mA
GKD = VOH
-
-
10
mA
RL = 200Ω
-
±2
-
mA
0
-
5
ms
Dial Pulse Distortion
Receive Input Impedance
(Note 4)
-
110
-
kΩ
Transmit Output Impedance
(Note 4)
-
10
20
Ω
2-Wire Return Loss
Referenced to 600Ω +2.16µF (Note 4)
SRL LO
-
15.5
-
dB
ERL
-
24
-
dB
SRL HI
-
31
-
dB
58
65
-
dB
2-Wire On Hook
60
63
-
dB
4-Wire Off Hook
50
58
-
dB
R.E.A. Method, (Note 4)
RL = 600Ω,
0oC ≤ TA ≤ 75oC
-
-
23
dBrnC
-
-
-67
dBm0p
Insertion Loss
2-Wire to 4-Wire, 4-Wire to 2-Wire
At 1kHz, 0dBm Input Level, Referenced 600Ω
-
±0.05
±0.2
dB
Frequency Response
200 - 3400Hz Referenced to Absolute
Loss at 1kHz and 0dBm Signal Level (Note 4)
-
±0.02
±0.05
dB
Idle Channel Noise
2-Wire to 4-Wire, 4-Wire to 2-Wire
(Note 4)
-
1
5
dBrnC
-
-89
-85
dBm0p
-
-
2
µs
Longitudinal Balance
1VRMS 200Hz - 3400Hz, (Note 4)
IEEE Method
0oC ≤ TA ≤ 75oC
2-Wire Off Hook
Low Frequency Longitudinal Balance
Absolute Delay
2-Wire to 4-Wire, 4-Wire to 2-Wire
(Note 4)
Trans Hybrid Loss
Balance Network Set Up for 600Ω
Termination at 1kHz
36
40
-
dB
Overload Level
2-Wire to 4-Wire, 4-Wire to 2-Wire
VB+ = 5V
1.5
-
-
VPEAK
VB+ = 12V
1.75
-
-
VPEAK
Level Linearity
At 1kHz, (Note 4) Referenced to 0dBm Level
2-Wire to 4-Wire, 4-Wire to 2-Wire
+3 to -40dBm
-
-
±0.05
dB
-40 to -50dBm
-
-
±0.1
dB
-50 to -55dBm
-
-
±0.3
dB
3
HC-5502B
Electrical Specifications
Unless Otherwise Specified, VB- = -48V, VB+ = 12V and 5V, AG = BG = DG = 0V, Typical Parameters
TA = 25oC. Min-Max Parameters are Over Operating Temperature Range (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
15
-
-
dB
VB+ to Transmit
15
-
-
dB
VB- to 2-Wire
15
-
-
dB
VB- to Transmit
15
-
-
dB
30
-
-
dB
30
-
-
dB
VB- to 2-Wire
30
-
-
dB
VB- to Transmit
30
-
-
dB
-
-
±100
µA
Logic ‘0’ VIL
-
-
0.8
V
Logic ‘1’ VIH
2.0
-
5.5
V
-
0.1
0.5
V
Power Supply Rejection Ratio
30 - 60Hz,
RL = 600Ω,
(Note 4)
VB+ to 2-Wire
VB+ to 2-Wire
200 - 16kHz,
RL = 600Ω
VB+ to Transmit
Logic Input Current (RS, RC, PD)
0V ≤ VIN ≤ 5V
Logic Inputs
Logic Outputs
Logic ‘0’ VOL
ILOAD 800µA, VB+ = 12V, 5V
Logic ‘1’ VOH
ILOAD 80µA, VB+ = 12V
2.7
5.0
5.5
V
ILOAD 40µA, VB+ = 5V
2.7
-
5.0
V
Uncommitted Op Amp Specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Input Offset Voltage
-
±5
-
mV
Input Offset Current
-
±10
-
nA
Input Bias Current
-
20
-
nA
Differential Input Resistance
(Note 4)
-
1
-
MΩ
Output Voltage Swing
RL = 10kΩ, VB+ = 12V
-
±6.2
±6.6
VPEAK
RL = 10kΩ, VB+ = 5V
-
±3
-
VPEAK
Output Resistance
AVCL = 1 (Note 4)
-
10
-
Ω
Small Signal GBW
(Note 4)
-
1
-
MHz
NOTES:
3. ILONG = Longitudinal Current.
4. These parameters are controlled by design or process parameters and are not directly tested. These parameters are characterized upon initial
design release, upon design changes which would affect these characteristics, and at intervals to assure product quality and specification
compliance.
4
HC-5502B
Pin Descriptions
28 PIN PLCC
24 PIN DIP
SYMBOL
DESCRIPTION
2
1
TIP
An analog input connected to the TIP (more positive) side of the subscriber loop through a 150Ω feed
resistor and a ring relay contact. Functions with the Ring terminal to receive voice signals from the
telephone and for loop monitoring process.
3
2
RING
An analog input connected to the RING (more negative) side of the subscriber loop through a 150Ω
feed resistor and a ring relay contact. Functions with the Tip terminal to receive voice signals from
the telephone and for loop monitoring purposes.
4
3
VB+
5
4
C1
Capacitor #1 - Optional Capacitor used to improve power supply rejection. This pin should be left open if
unused.
6
5
C3
Capacitor #3 - An external capacitor to be connected between this terminal and analog ground.
Required for proper operation of the loop current limiting function, and for filtering VB- supply. Typical
value is 0.3µF, 30V.
7
6
DG
(Note 5)
Digital Ground - To be connected to zero potential and serves as a reference for all digital inputs and
outputs on the SLIC.
9
7
RS
Ring Synchronization Input - A TTL - compatible clock input. The clock should be arranged such that
a positive transition occurs on the negative going zero crossing of the ring voltage source, ensuring
that the ring relay is activated and deactivated when the instantaneous ring voltage is near zero. If
synchronization is not required, tie to 5V.
10
8
RD
Relay Driver - A low active open collector logic output. When enabled, the external ring relay is
energized.
11
9
TF
Tip Feed - A low impedance analog output connected to the TIP terminal through a 150Ω feed
resistor. Functions with the RF terminal to provide loop current, feed voice signals to the telephone
set, and sink longitudinal current.
12
10
RF
Ring Feed - A low impedance analog output connected to the RING terminal through a 150Ω feed
resistor. Functions with the TF terminal to provide loop current, feed voice signal to the telephone
set, and sink longitudinal current.
13
11
VB-
Negative Voltage Source - Most negative supply. VB- is typically -48V with an operational range of 42V to -58V. Frequently referred to as “battery”.
14
12
BG
(Note 1)
Battery Ground - To be connected to zero potential. All loop current and some quiescent current
flows into this ground terminal.
16
13
SHD
Switch Hook Detection - A low active LS TTL - compatible logic output. This output is enabled for
loop currents exceeding 10mA and disabled for loop currents less than 5mA.
17
14
GKD
Ground Key Detection - A low active LS TTL - compatible logic output. This output is enabled if the
DC current into the ring lead exceeds the DC current out of the tip lead by more than 20mA, and
disabled if this current difference is less than 10mA.
18
15
PD
Power Denial - A low active TTL - Compatible logic input. When enabled the switch hook detect
(SHD) and ground key detect (GKD) are not necessarily valid, and the relay driver (RD) output is
disabled.
19
16
RC
Ring Command - A low active TTL - Compatible logic input. When enabled, the relay driver (RD)
output goes low on the next rising edge of the ring sync (RS) input, as long as the SLIC is not in the
power denial state (PD = 0) or the subscriber is not already off- hook (SHD = 0).
20
17
C2
Capacitor #2 - An external capacitor to be connected between this terminal and digital ground.
Prevents false ground key indications from occurring during ring trip detection. Typical value is
0.15µF, 10V. This capacitor is not used if ground key function is not required.
21
18
OUT
23
19
-IN
The inverting analog input of the spare operational amplifier.
24
20
+IN
The non-inverting analog input of the spare operational amplifier.
5
Positive Voltage Source - Most positive supply. VB+ is typically 12V or 5V.
The analog output of the spare operational amplifier.
HC-5502B
Pin Descriptions
(Continued)
28 PIN PLCC
24 PIN DIP
SYMBOL
DESCRIPTION
25
21
RX
Receive Input, 4-Wire Side - A high impedance analog input which is internally biased. Capacitive
coupling to this input is required. AC signals appearing at this input differentially drive the Tip feed
and Ring feed amplifiers, which in turn drive tip and ring through 300Ω of feed resistance on each
side of the line.
26
22
C4
Capacitor #4 - An external capacitor to be connected between this terminal and analog ground. This
capacitor prevents false ground key indication and false ring trip detection from occurring when
longitudinal currents are induced onto the subscriber loop from nearby power lines and other noise
sources. This capacitor is also required for the proper operation of ring trip detection. Typical value
is 0.5µF to 1.0µF, 20V. This capacitor should be nonpolarized.
27
23
AG
(Note 5)
Analog Ground - To be connected to zero potential and serves as a reference for the transmit output
(TX) and receive input (RX) terminals.
28
24
TX
Transmit Output, 4-Wire Side - A low impedance analog output which represents the differential
voltage across Tip and Ring. Transhybrid balancing must be performed (using the SLIC
microcircuit’s spare op amp) beyond this output to completely implement two to four wire conversion.
This output is unbalanced and referenced to analog ground. Since the DC level of this output varies
with loop current, capacitive coupling to the next stage is essential.
NC
No internal connection.
1, 8, 5, 22
NOTE:
5. All grounds (AG, BG, and DG) must be applied before VB+ or VB-. Failure to do so may result in premature failure of the part. If a user wishes
to run separate grounds off a line card, the AG must be applied first.
Functional Diagram
RING
VOLTAGE
RING SYNC
RING COMMAND
RC
RD
RING
CONTROL
SHD SWITCH HOOK
DETECTION
LOOP
MONITORING
GKD GROUND KEY
DETECTION
TIP
RING
RELAY
TIP
RING
TRIP
RS
DIFF
AMP
150Ω
+
TX
150Ω
TRANSMIT
OUTPUT
TF
2 WIRE
LOOP
V BBATTERY
FEED
SECONDARY
PROTECTION
OUT
+1
BG
VB-
RF
150Ω
LOOP
CURRENT
LIMITER
LINE
DRIVERS
RING
RING
-1
150Ω
POWER DENIAL
PD
SLIC MICROCIRCUIT
6
+IN
OP
AMP
+
-IN
RX RECEIVE
INPUT
HC-5502B
Schematic Diagram
HC-5502B
Pin Numbers for DIP Package
21
22
RCV
1
A-400
TIP FEED
AMP
TF
C4
12
BAT
GND
VBAT
23
ANA
GND
6
DIG
VB+ GND
C1
+
-
OUT
VB+
-
VB1
VB2
VB3
VB4
VB5
-5V
+
A-500
OP AMP
VBAT
RING TRIP
DETECTOR
R7
VB+
VB+
QD3
QD36
R10
A-200
LONG’L
I/V AMP
VBAT
+5V
GK
+
IB6
R16
R15
-
VB3
VBAT
VB+
VBAT
+
R6
IIL
LOGIC
INTERFACE
QD27
R14
R18
SHD 13
SH
LOOP CURRENT
LIMITING
IB2
THERMAL
LIMITING
VB5
RFC
VB5
VBAT
R13
VBAT
RC
16
PD
15
QD28
R19
VBAT
C3
TX
RS
RD
5
24
7
8
7
17
VB1
+
IB5
C2
IB9
VB2
R21
-
GKD 14
+
SWITCH HOOK
DETECTOR
VBAT/2 REFERENCE
A-300
RING FEED
AMP
GND SHORTS
CURRENT
LIMITING
IB1
A-100
TRANSV’L
I/VAMP
R2
VBAT
IB8
VBAT
VB+
R1
VB4
R5
R3
R4
-5V IB10 VB+
R20
IB7
R11
VBAT
V B+
VBAT
VB+
18
IB1 IB2 IB3 IB4 IB5 IB6 IB7 IB8 VBAT IB9 IB10 IB11
1 TIP
10 RF
19
IB3
R12
2 RING
20
VB2
IB4
R9
4
-
VBAT
R8
3
VOLTAGE AND CURRENT
BIAS NETWORK
R17
+
VB+
11
HC-5502B
Logic Diagram
HC-5502B LOGIC GATE SCHEMATIC
C2
GK
1
2
LOGIC BIAS
DELAY
8
7
9
5
4
SH
6
3
12
16
10
13
11
RELAY
DRIVER
14
15
15
TTL
TO
STTL
TTL
TO
STTL
TO
R21
TTL
TO
STTL
STTL
TO
TTL
C
STTL
TO
TTL
B
A
A
B
RS
RC
PD
RD
C
SHD
GKD
SCHOTTKY LOGIC
Overvoltage Protection and Longitudinal
Current Protection
TABLE 1.
PERFORMANCE
(MAX)
UNITS
10µs Rise/
±1000 (Plastic)
VPEAK
1000µs Fall
±500 (Ceramic)
VPEAK
10µs Rise/
±1000 (Plastic)
VPEAK
1000µs Fall
±500 (Ceramic)
VPEAK
T/GND
10µs Rise/
±1000 (Plastic)
VPEAK
R/GND
1000µs Fall
±500 (Ceramic)
VPEAK
T/GND
11 Cycles
700 (Plastic)
VRMS
R/GND
Limited to
10ARMS
350 (Ceramic)
VRMS
PARAMETER
The SLIC device, in conjunction with an external protection
bridge, will withstand high voltage lightning surges and
power line crosses.
Longitudinal
Surge
High voltage surge conditions are as specified in Table 1.
Metallic Surge
The SLIC will withstand longitudinal currents up to a
maximum or 30mARMS, 15mARMS per leg, without any
performance degradation.
TEST
CONDITION
50/60Hz Current
8
HC-5502B
Applications Diagram
SYSTEM CONTROLLER
Z1
15
12V
PTC
RING GENERATOR
150VPEAK (MAX)
13
14
7
16
POWER SWITCH GROUND RING RING
SYNC CMD
DENIAL HOOK
KEY
8
DETECT DETECT
RD
RECEIVE
RING
RELAY
BALANCE NETWORK
C5
21
C6
24
C7
TRANSMIT
RB1
TIP
SLIC
HC-5502B
TIP
RB2
CS
RS
1
20
19
-IN
OP AMP
9
R1
+IN
PCM SWITCHING
FILTER/ NETWORK
CODEC
ZB
18
R2
OUT
TIP FEED
R3
VBSUBSCRIBER
LOOP
10
RING FEED
C1
PRIMARY
PROTECTION
C2
RB4
C3
2
RING
RB3
C4
4
17
5
22
RING
NEG.
BATT.
BATT.
GND.
DIG.
GND.
ANA.
GND.
POS.
SUPP.
11
12
6
23
3
C8
-48V
C4
C3
C2
C1
C9
VB+
FIGURE 1. TYPICAL LINE CIRCUIT APPLICATION WITH THE MONOLITHIC SLIC
Typical Component Values
C1 = 0.5µF (Note 6).
R1 = R2 = R3 = 100kΩ (0.1% Match Required, 1% absolute
value), ZB = 0 for 600Ω Terminations (Note 7).
C2 = 0.15µF, 10V.
RB1 = RB2 = RB3 = RB4 = 150Ω (0.1% Match Required, 1%
absolute value).
C3 = 0.3µF, 30V.
C4 = 0.5µF to 1.0µF, 10%, 20V (Should be nonpolarized).
C5 = 0.5µF, 20V.
C6 = C7 = 0.5µF (10% Match Required) (Note 7), 20V.
C8 = 0.01µF, 100V.
RS = 1kΩ, CS = 0.1µF, 200V typically, depending on VRING
and line length.
Z1 = 150V to 200V transient protection. PTC used as ring
generator ballast.
C9 = 0.01µF, 20V, ±20%.
NOTES:
6. C1 is an optional capacitor used to improve VB+ supply rejection. This pin must be left open if unused.
7. To obtain the specified transhybrid loss it is necessary for the three legs of the balance network, C6-R1 and R2 and C7-ZB-R3, to match in
impedance to within 0.3%. Thus, if C6 and C7 are 1µF each, a 20% match is adequate. It should be noted that the transmit output to C6 sees
a -22V step when the loop is closed. Too large a value for C6 may produce an excessively long transient at the op amp output to the PCM
Filter/CODEC.
A 0.5µF and 100kΩ gives a time constant of 50ms. The uncommitted op amp output is internally clamped to stay within ±6.6V and is current
limited.
8. Secondary protection diode bridge recommended is a 2A, 200V type.
9. All grounds (AG, BG, and DG) must be applied before VB+ or VB-. Failure to do so may result in premature failure of the part. If a user wishes
to run separate grounds off a line card, the AG must be applied first.
10. Pin numbers given for DIP package.
9
HC-5502B
Dual-In-Line Plastic Packages (PDIP)
E24.6 (JEDEC MS-011-AA ISSUE B)
N
24 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
1 2 3
INCHES
N/2
SYMBOL
-B-
-C-
A2
SEATING
PLANE
e
B1
D1
A1
eC
B
0.010 (0.25) M
C A B S
0.250
-
-
0.39
A2
0.125
0.195
3.18
4.95
-
B
0.014
0.022
0.356
0.558
-
C
L
B1
0.030
0.070
0.77
1.77
8
eA
C
0.008
0.015
0.204
0.381
-
D
1.150
1.290
D1
0.005
-
C
eB
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and eA are measured with the leads constrained to be perpendicular to datum -C- .
7. eB and eC are measured at the lead tips with the leads unconstrained.
eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
6.35
NOTES
-
NOTES:
10
MAX
0.015
A
L
D1
MIN
A
E
BASE
PLANE
MAX
A1
-AD
MILLIMETERS
MIN
29.3
-
4
4
32.7
5
-
5
0.13
E
0.600
0.625
15.24
15.87
6
E1
0.485
0.580
12.32
14.73
5
e
0.100 BSC
2.54 BSC
-
eA
0.600 BSC
15.24 BSC
6
eB
-
0.700
-
17.78
7
L
0.115
0.200
2.93
5.08
4
N
24
24
9
Rev. 0 12/93
HC-5502B
Plastic Leaded Chip Carrier Packages (PLCC)
0.042 (1.07)
0.048 (1.22)
PIN (1) IDENTIFIER
N28.45 (JEDEC MS-018AB ISSUE A)
0.042 (1.07)
0.056 (1.42)
0.004 (0.10)
C
0.025 (0.64)
R
0.045 (1.14)
0.050 (1.27) TP
C
L
D2/E2
C
L
E1 E
D2/E2
VIEW “A”
0.020 (0.51)
MIN
A1
A
D1
D
28 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.165
0.180
4.20
4.57
-
A1
0.090
0.120
2.29
3.04
-
D
0.485
0.495
12.32
12.57
-
D1
0.450
0.456
11.43
11.58
3
D2
0.191
0.219
4.86
5.56
4, 5
E
0.485
0.495
12.32
12.57
-
E1
0.450
0.456
11.43
11.58
3
E2
0.191
0.219
4.86
5.56
4, 5
N
28
28
6
Rev. 2 11/97
SEATING
-C- PLANE
0.020 (0.51) MAX
3 PLCS
0.026 (0.66)
0.032 (0.81)
0.013 (0.33)
0.021 (0.53)
0.025 (0.64)
MIN
0.045 (1.14)
MIN
VIEW “A” TYP.
NOTES:
1. Controlling dimension: INCH. Converted millimeter dimensions are
not necessarily exact.
2. Dimensions and tolerancing per ANSI Y14.5M-1982.
3. Dimensions D1 and E1 do not include mold protrusions. Allowable
mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1
and E1 include mold mismatch and are measured at the extreme
material condition at the body parting line.
4. To be measured at seating plane -C- contact point.
5. Centerline to be determined where center leads exit plastic body.
6. “N” is the number of terminal positions.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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11
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