DATASHEET

Fixed Gain Dual Port Class-G Differential xDSL Line
Driver
ISL1561
Features
The ISL1561 is a fixed gain dual port class-G differential
amplifier designed for driving full rate ADSL2+ and VDSL2
signals at very low power dissipation. The driver runs on a
single +14V power supply and internally generates higher
supply voltages when needed to enable power efficient
operation for high peak-to-average ratio (PAR) ADSL2+ and
VDSL2 signals.
• Internal fixed gain of 11.6V/V to transformer (see Figure 3)
In ADSL2+ mode of operation with full 19.8dBm transmit
signal power across 100Ω line load, each port consumes only
520mW of power, while with 19.5dBm VDSL2 8b profile a port
consumes 610mW of power. In VDSL2 17a mode of operation
with 14.5dBm transmit power, a port will consume 411mW of
power. These typical power consumption figures account for
receiver hybrid loading effects and transformer losses.
The ISL1561 provides two ports of wideband, current feedback
amplifiers optimized for low power consumption in xDSL
systems. The drivers achieve an average upstream missing
band power ratio (MBPR) distortion of better than -64dBc
under 19.8dBm transmit signal power into 100Ω load. A three
pin serial interface is used to program an 8-bit internal register
to set each port’s supply current with 0.5mA step size. This
flexibility allows the DSP to optimize each port separately
during modem training.
• 360mA output drive capability
• 41.8VP-P differential output drive into 100Ω in class G mode
• VDSL2 8b profile MTPR of -64dBc
• VDSL2 17a profile MTPR of -60dBc
• ADSL2+, VDSL2 8b and 17a power consumption of 520mW,
610mW and 411mW respectively
• 8-bit programmable register to set supply current on each
port
• 3 pin serial port interface
Applications
• Dual port ADSL2+ and VDSL2 DSLAM
Alternate Part
• ISL1591 Class AB VDSL Driver
The device is supplied in a thermally-enhanced small footprint
(4mmx4mm) 24 lead QFN package. The ISL1561 is specified
for operation over the full -40°C to +85°C industrial
temperature range and is Pb-free RoHS compliant.
+14V
900
SCLK
CS
CPP
SERIAL
BIAS
INTERFACE CURRENT
SETTING
CPSW
POWER MANAGEMENT
CMM
CMSW
BOOST
SWITCH SIGNAL
BOTH PORTS
SUPPLY
RAILS OF
LINE DRIVERS
AFE
INP
ANALOG
INPUT
CLASS
AB
DRIVER
OUTPUT OF
DRIVER
1 OF 2
PORTS
FIGURE 1. BLOCK DIAGRAM
February 26, 2013
FN7941.1
1
OUT
8b CLASS AB
800
POWER CONSUMPTION (mW)
SDATA
700
17a CLASS AB
600
500
400
8b CLASS G
300
200
17a CLASS G
100
0
2
4
6
8
10
12
14
Tx POWER (dBm)
16
18
20
FIGURE 2. CLASS G+ vs CLASS AB DRIVER TOTAL POWER
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL1561
Pin Configuration
19 FBB
20 OUTB
21 OUTA
22 FBA
23 SDATA
24 BOOST
ISL1561
(24 LD QFN)
TOP VIEW
INPA 1
18 VSP
INPB 2
17 CPSW
VCMAB 3
16 CPP
THERMAL
PAD
VCMCD 4
15 CMM
FBC 12
OUTC 11
OUTD 10
13 GND
FBD 9
INPD 6
SCLK 8
14 CMSW
CS 7
INPC 5
THERMAL PAD CONNECTS TO GROUND
Pin Descriptions
ISL1561
(24 Ld QFN)
PIN
NAME
1
INPA
Amplifier A non-inverting input
2
INPB
Amplifier B non-inverting input
3
VCMAB
4
VCMCD
5
INPC
Amplifier C non-inverting input
6
INPD
Amplifier D non-inverting input
7
CS
8
SCLK
Serial clock input
9
FBD
Feedback pin for amplifier D
10
OUTD
Amplifier D output
11
OUTC
Amplifier C output
FUNCTION
Input common mode bias for port AB
Input common mode bias for port CD
Chip select, low enables data input to logic
12
FBC
Feedback pin for amplifier C
13
GND
Ground
14
CMSW
15
CMM
Internal negative supply
16
CPP
Internal positive supply
17
CPSW
Internal negative boost supply
Internal positive boost supply
18
VSP
Positive supply voltage
19
FBB
Feedback pin for amplifier B
20
OUTB
Amplifier B output
21
OUTA
Amplifier A output
22
FBA
Feedback pin for amplifier A
23
SDATA
Serial data write
24
BOOST
Class G control input
2
FN7941.1
February 26, 2013
ISL1561
VSP
+
1µF
CPP
CPSW
POWER
CONTROL
INP
+
0.1µF
3.5kΩ
OUTPUT
POSITIVE
SUPPLY
¼
ISL1561
OUT
5.1Ω
+VSP
AFE VCM
Rc
100kΩ
0.1µF
1:1.4
Rf
1.33kΩ
Rc
100kΩ
Rp
1.78kΩ
Rg
733Ω
Rp
1.78kΩ
FB
100Ω
LINE
FB
Rf
1.33kΩ
¼
ISL1561
3.5kΩ
INP
OUT
5.1Ω
OUTPUT
NEGATIVE
SUPPLY
+
0.1µF
ISP PORT
CONTROL
GND
POWER
CONTROL
CMM
+
ISP
ADJUST
LOGIC
SPI
CLASS G
CONTROL
BOOST
CONTROL
CMSW
1µF
TYPICAL DIFFERENTIAL I/O LINE DRIVER (1 OF 2 PORTS)
FIGURE 3. CONNECTION DIAGRAM
Ordering Information
PART NUMBER
(Notes 2, 3)
PART
MARKING
OPERATING AMBIENT
TEMP RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL1561IRZ
15 61IRZ
-40 to +85
24 Ld QFN
L24.4x4H
ISL1561IRZ-T13 (Note 1)
15 61IRZ
-40 to +85
24 Ld QFN
L24.4x4H
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL1561. For more information on MSL please see tech brief TB363.
3
FN7941.1
February 26, 2013
ISL1561
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
VS+ Voltage to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +15V
Driver VIN+ Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .GND to VS+
SPI and Boost Pin Voltage to GND . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V
VCM Voltage to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .GND to VS+
Current into any Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8mA
Continuous Output Current for Long Term Reliability. . . . . . . . . . . . . . . . .50mA
ESD Rating
Human Body Model (Tested per JESD22-A114F). . . . . . . . . . . . . . . . . . 3kV
Machine Model (Tested per JESD22-A115C) . . . . . . . . . . . . . . . . . . 300V
Charge Device Model (Tested per JESD22-C101E). . . . . . . . . . . . . .1.5kV
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
24 Ld QFN Package (Notes 4, 5)
44
5
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Performance Curve
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-40°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +150°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
VSP = +14V, RL-DIFF = 51Ω differential (emulating transformer input load), Refer to Figure 3, TA = +25°C. Ports
tested separately unless otherwise indicated.
PARAMETER
DESCRIPTION
CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
AC PERFORMANCE
AV
BW
Gain Flatness
-3dB Bandwidth
Small Signal Gain Flatness
Gain Across the Load, RB = 5.1Ω
11.6
V/V
IS = 14mA/port, VO < 2VPP-DIFF
110
MHz
IS = 10mA/port, VO = 5VPP-DIFF
70
MHz
IS = 14mA/port, 17.6MHz
0.3
dB
IS = 14mA/port, 30MHz
0.9
dB
1000
V/µs
SR
Slew Rate
VOUT = 16VP-P-DIFF (20% to 80%)
200kHz Harmonic
Distortion
2nd Harmonic
10mA/port, VOUT = 10VP-P-DIFF
-95
dBc
3rd Harmonic
10mA/port, VOUT = 10VP-P-DIFF
-83
dBc
THD
10mA/port, VOUT = 10VP-P-DIFF
-83
dBc
2nd Harmonic
10mA/port, VOUT = 10VP-P-DIFF
-80
dBc
3rd Harmonic
10mA/port, VOUT = 10VP-P-DIFF
-75
dBc
THD
10mA/port, VOUT = 10VP-P-DIFF
-74
dBc
MBPR
Average Missing-Band Power Ratio
26kHz to 8MHz, 5kHz Tone Spacing,
PLINE = 19.5dBm, VDSL2+ 8b, US1
-64
dBc
eO
Output Voltage Noise
f = 1MHz, differential each port
110
nV/√ Hz
eO-CM
Common Mode Output Noise at each
Port Pair
f = 1MHz
190
nV/√ Hz
VHIGH
Input High Voltage
SCLK, SDATA, CS, BOOST inputs
VLOW
Input Low Voltage
SCLK, SDATA, CS, BOOST inputs
IHIGH
Input High Current for Pull-up Pins CS,
BOOST
VIN = 3.3V
-28
IHIGH
Input High Current for Pull-down Pins
SCLK, SDATA
VIN = 3.3V
40
4MHz Harmonic
Distortion
560
CONTROL FEATURES
4
2.3
V
0.8
V
-23
-18
µA
50
60
µA
FN7941.1
February 26, 2013
ISL1561
Electrical Specifications
VSP = +14V, RL-DIFF = 51Ω differential (emulating transformer input load), Refer to Figure 3, TA = +25°C. Ports
tested separately unless otherwise indicated.(Continued)
PARAMETER
DESCRIPTION
CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
ILOW
Input Low Current for Pull-up Pins CS,
BOOST
VIN = 0V
-88
-73
-58
µA
ILOW
Input Low Current for Pull-down Pins
SCLK, SDATA
VIN = 0V
-0.2
0
+0.2
µA
+10
+14
+14.7
V
SUPPLY CHARACTERISTICS
VS
Operating Supply Voltage
VCPP
Voltage on the CPP Pin
BOOST = 0V (Class AB)
7
V
VCPSW
Maximum Voltage on the CPSW Pin
BOOST = 0V (Class AB)
14
V
VCMM
Voltage on the CMM Pin
BOOST = 0V (Class AB)
7
V
VCMSW
Minimum Voltage on the CMSW Pin
BOOST = 0V (Class AB)
0
V
ISP
Positive Supply Current per Port
All outputs at 0V, BOOST = 0V, SDATA = 8’h7F
for Registers 3 and 7
17.5
19.5
21.5
mA
All outputs at 0V, BOOST = 0V, SDATA = 8’h1C
for Registers 3 and 7
9.8
10.3
10.8
mA
All outputs at 0V, BOOST = 0V, SDATA = 8’h0F
for Registers 3 and 7
6.8
7.2
7.6
mA
All outputs at 0V, BOOST = 0V, SDATA = 8’h80
for Registers 3 and 7
2.0
2.5
3.0
mA
11.9
12.4
ISP (Power-down)
Supply Current per Port
OUTPUT CHARACTERISTICS
VOUT
Loaded Output Swing High
(Single-ended to GND)
RL = 51Ω, Class AB (see Figure 3)
Loaded Output Swing High
(Single-ended to GND)
RL = 51Ω, Class AB (see Figure 3)
IOL
Linear Output Current
RL = 10Ω, f = 100kHz, THD = -60dBc (5Ω
differential)
VOS-DM
Differential Output Offset Voltage
SDATA = 8’h1C
-125
VOS-CM
Common Mode Output Offset Voltage
SDATA = 8’h1C (Offset from input VCM)
1.6
V
2.1
±360
18
V
mA
+125
mV
6.85
7.09
mV
+4.5
+9.5
V
INPUT CHARACTERISTICS
CMIR
Common Mode Input Range at each of
the 4 Non-inverting Input Pins
Class AB
CMRR
DC Common Mode Rejections for each
Port. VCM = +4.5V to +9.5V
VCM to Differential Mode Output (Input
Referred) ISP = 10mA/port
66
dB
VCM to Common Mode Output (Output
Referred) ISP = 10mA/port
40
dB
DC Power Supply Rejections for each
Port to Differential Output (Input
Referred)
+VS = +7V to +14V, GND = 0V, ISP = 10mA/port
74
dB
DC Power Supply Rejections for each
Port to Common Mode Output (Output
Referred)
+VS = +7V to +14V, GND = 0V, ISP = 10mA/port
55
dB
Input Resistance
Differential
PSRR
RIN
5.0
6.0
7.1
kΩ
0.1
10
MHz
DIGITAL
fCLK
Clock Frequency
NOTE:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
5
FN7941.1
February 26, 2013
ISL1561
Typical Performance Curves
TA = +25°C, Unless otherwise noted.
VCC = +14V, Rb = 5.1Ω, Gain at the Load = 11.6V/V (Differential), RLOAD = 51Ω,
9
9
VO = 0.5VP-P
10mA/PORT
8mA/PORT
14mA/PORT
10mA/PORT
3
12mA/PORT
0
-3
3
0
-9
1M
10M
100M
FREQUENCY (Hz)
VO = 10VP-P
-9
1M
1G
10M
100M
FREQUENCY (Hz)
1G
FIGURE 5. LARGE SIGNAL FREQUENCY RESPONSE
FIGURE 4. SMALL SIGNAL FREQUENCY RESPONSE vs BIAS CURRENT
9
9
10mA/PORT
6
VO = 0.5VP-P
6
CL = 5.6pF
CL = 39pF
8mA/PORT
3
3
GAIN (dB)
NORMALIZED GAIN (dB)
VO = 5VP-P
-3
-6
-6
VO = 1VP-P
VO = 2VP-P
6
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
6
CL = 15pF
CL = 27pF
0
14mA/PORT
0
-3
-3
-6
10mA/PORT
12mA/PORT
-6
1M
10M
100M
FREQUENCY (Hz)
-9
100k
1G
FIGURE 6. SMALL SIGNAL FREQUENCY RESPONSE vs CLOAD
1M
10M
FREQUENCY (Hz)
100M
FIGURE 7. COMMON MODE SMALL SIGNAL RESPONSE vs BIAS
CURRENT
700
700
-50
MBPR (dBc)
8MHz PROFILE (10mA/PORT)
500
17MHz (12mA/PORT)
400
300
200
600
-55
600
ADSL2 SMARTG (8mA/PORT)
8
10
12
14
16
18
LINE POWER (dBm)
FIGURE 8. POWER CONSUMPTION vs LINE POWER
6
500
-60
Pd (mW)
400
-65
300
MBPR (dBc)
-70
200
-75
20
-80
10
100
11
12
13
14
15
16
17
18
19
POWER CONSUMPTION (mW)
POWER CONSUMPTION (mW)
CF = 6.56V/V
0
20
LINE POWER (dBm)
FIGURE 9. VDSL2+ 8b Avg. MBPR US1 vs LINE POWER
FN7941.1
February 26, 2013
ISL1561
Typical Performance Curves
TA = +25°C, Unless otherwise noted. (Continued)
VCC = +14V, Rb = 5.1Ω, Gain at the Load = 11.6V/V (Differential), RLOAD = 51Ω,
-40
-40
10mA/PORT
VO = 2VP-P
-50
HARMONIC DISTORTION (dBc)
HARMONIC DISTORTION (dBc)
-30
3RD HD
-60
-70
-80
-90
2ND HD
-100
100k
1M
fc = 4MHz
VO = 2VP-P
-50
-60
3RD HD
-70
-80
-90
2ND HD
-100
8
10M
10
12
14
16
BIAS CURRENT(mA)
FREQUENCY (Hz)
-50
10mA/PORT
fc = 4MHz
VO = 2VP-P
-65
HARMONIC DISTORTION (dBc)
HARMONIC DISTORTION (dBc)
-60
3RD HD
-70
-75
-80
-85
-90
25
10mA/PORT
fc = 4MHz
-55
-60
-65
3RD HD
-70
-75
-80
-85
2ND HD
2ND HD
50
75
100
-90
125
1
RLOAD (Ω)
3
5
7
9
11
13
DIFFERENTIAL OUTPUT VOLTAGE (VP-P)
15
FIGURE 13. HARMONIC DISTORTION vs OUTPUT AMPLITUDE
FIGURE 12. HARMONIC vs RLOAD
1000
nV/√Hz
1000
nV/√Hz
20
FIGURE 11. HARMONIC DISTORTION vs BIAS CURRENT
FIGURE 10. HARMONIC DISTORTION vs FREQUENCY
100
10
18
1k
10k
100k
1M
FREQUENCY (Hz)
10M
FIGURE 14. DIFFERENTIAL OUTPUT VOLTAGE NOISE
7
100M
100
10
10k
100k
1M
FREQUENCY (Hz)
10M
100M
FIGURE 15. COMMON MODE OUTPUT VOLTAGE NOISE
FN7941.1
February 26, 2013
ISL1561
Typical Performance Curves
TA = +25°C, Unless otherwise noted. (Continued)
VCC = +14V, Rb = 5.1Ω, Gain at the Load = 11.6V/V (Differential), RLOAD = 51Ω,
-60
-20
10mA/PORT
10mA/PORT
-30
-70
-80
-60
GAIN (dB)
CHANNEL AB -> CD
-50
CHANNEL CD -> AB
-70
-90
-100
-80
-110
-90
-100
100k
1M
10M
FREQUENCY (Hz)
-120
100k
100M
1M
FIGURE 16. CHANNEL-TO-CHANNEL CROSSTALK
10M
FREQUENCY (Hz)
100M
FIGURE 17. OFF-ISOLATION
SDATA
SDATA
OUTA
OUTA
tEN = 600ns
tDIS = 1.6µs
FIGURE 19. DISABLE RESPONSE
FIGURE 18. ENABLE RESPONSE
25
20
Iq/PORT (mA)
GAIN (dB)
-40
15
10
5
0
0
20
40
60
80
100
120
140
Iq CODE
FIGURE 20. QUIESCENT CURRENT PER PORT vs CODES
8
FN7941.1
February 26, 2013
ISL1561
Typical Performance Curves
TA = +25°C, Unless otherwise noted. (Continued)
VCC = +14V, Rb = 5.1Ω, Gain at the Load = 11.6V/V (Differential), RLOAD = 51Ω,
11.70
45
11.65
Iq = ‘7F’
35
GAIN AT LOAD (V/V)
TOTAL Iq FOR 2 PORTS (mA)
40
30
25
20
Iq = ‘1C’
15
10
11.60
GAIN
11.55
11.50
11.45
5
0
-40
-20
0
20
40
TEMPERATURE (°C)
60
11.40
-40
80
FIGURE 21. QUIESCENT CURRENT vs TEMPERATURE
0
20
40
TEMPERATURE (°C)
1100
-60
1080
-62
-68
HD (dBc)
1000
980
-70
-72
960
-74
940
-76
920
-78
-20
0
20
3RD HD
-66
1020
900
-40
40
60
-80
-40
80
2ND HD
-20
0
20
40
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 24. 4MHz HARMONIC DISTORTION vs TEMPERATURE
FIGURE 23. SLEW RATE vs TEMPERATURE
8
14
12
7
HIGH SWING
CM
6
10
Vos (mV)
OUTPUT SWING (V)
80
10VP-P
-64
SR
1040
60
FIGURE 22. GAIN AT LOAD vs TEMPERATURE
1060
SLEW RATE (V/µs)
-20
8
6
4
5
4
3
DM
2
LOW SWING
2
0
-40
-20
0
20
1
40
60
TEMPERATURE (°C)
FIGURE 25. OUTPUT SWING vs TEMPERATURE
9
80
0
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
FIGURE 26. OUTPUT OFFSET CM AND DM vs TEMPERATURE
FN7941.1
February 26, 2013
ISL1561
General Description
Digital Interface
The ISL1561 is a class G amplifier designed to reduce power
consumption in ADSL2+ and VDSL2 applications compared to
class AB. With the high PAR used for xDSL signals, a supply
voltage of +14V can be used for the majority of the small
amplitude cycles while boosting to a supply voltage of +28V can
be used for the few high amplitude cycles.
A 12-bit serial port interface is used to program ISL1561. The
first bit defines the write (1’b1) and read (1’b0) operation to the
register. The following 3-bit calls the registers. The last 8-bit
programs the registers. Default start-up for ISL1561 is in disable
mode with boost and CS pins having internal pull ups and SCLK
and SDATA pins having internal pull downs. ISL1561 can only be
programmed through the SPI when CS is set low.
Register Listing
ADDRESS
FUNCTION
BIT
3’h3
Setting of quiescent current of port AB
[7]
[6:0]
3’h7
Setting of quiescent current of port CD
[7]
[6:0]
0
1
2
DESCRIPTION
Boost disable
Program quiescent current of port AB.
Boost disable
Program quiescent current of port CD.
3
SCLK
Z-HI
W/R
SDATA
ADDR[0:2]
D[0] D[1] D[2]
CS
D[3] D[4]
D[5]
D[6] D[7]
Z-HI
CURRENT SETTING VALUE
FIGURE 27. 12 BITS SERIAL ADDRESSING DIAGRAM
tHC
CS
tSC
t
tSC
tr
tf
SCLK
tSD
tHD
BN
SDATA
LSB
B(N-1)
tw
B(N-2)
LOAD LSB FIRST, MSB LAST
B1
B0
MSB
t
FIGURE 28. 12 BITS SERIAL ADDRESSING DIAGRAM
10
FN7941.1
February 26, 2013
ISL1561
TABLE 1. SERIAL TIMING DIAGRAM
PARAMETER
RECOMMENDED OPERATING RANGE
DESCRIPTION
t
≥100ns
Clock Period
tr/tf
0.05*t
Clock Rise/Clock Fall
tHC
≥7ns
Data Hold Time
tSD
≥10ns
Data Setup Time
tHC
≥2.8ns
CS Hold Time
tSC
≥0.5ns
CS Setup Time
tW
0.50*t
Clock Pulse Width
Boost Control
Table 2 summarizes the logic of register MSB on boost operations followed by Figure 29 with the recommended look ahead timing for
the boost signal.
TABLE 2. REGISTER MSB ON BOOST OPERATION
Reg3 8’h[7]
Reg7 8’h[7]
BOOST PIN
BOOST OPERATION
0
X
1
1
X
0
1
1
1
1
X
0
X
X
0
0
NOTE: X = do not care
SIGNAL
td
BOOST
FIGURE 29. SERIAL TIMING DIAGRAM
TABLE 3. EXTERNAL BOOST SIGNAL TIMING PARAMETERS
PARAMETER
RECOMMENDED OPERATING RANGE
DESCRIPTION
td
100ns
Look ahead boost
11
FN7941.1
February 26, 2013
ISL1561
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
January 24, 2013
FN7941.1
November 21, 2012
October 5, 2012
CHANGE
Changed MIN/MAX specs for “Differential Output Offset Voltage” on page 5 from -75/75mV to -125/125mV.
Added resistor values to Figure 3 on page 3.
Edited table heading for columns 1 and 2 in Table 2 on page 11.
FN7941.0
Initial Release.
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12
FN7941.1
February 26, 2013
ISL1561
Package Outline Drawing
L24.4x4H
24 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 09/11
2.50
4.00
20X 0.50
A
B
6
PIN 1
INDEX AREA
18
4.00
(4X)
6
24
19
PIN #1 INDEX AREA
1
Exp. DAP
2.50 ±0.05 Sq.
2.50
6
13
0.15
0.10 M C A B
24X 0.25 +0.07 4
-0.05
TOP VIEW
7
12
24X 0.40 ±0.10
0.25 min (4 sides)
BOTTOM VIEW
SEE DETAIL "X"
C
0.10 C
0.90 ±0.10
0 . 2 REF
5
C
SEATING PLANE
0.08 C
0 . 00 MIN.
0 . 05 MAX.
SIDE VIEW
DETAIL "X"
( 3.80 )
( 2.50)
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSEY14.5m-1994.
( 20X 0.50)
( 3.80 )
( 2.50 )
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
(24X .25)
6.
( 24 X 0.60)
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Compliant to JEDEC MO-220 VGGD-8
TYPICAL RECOMMENDED LAND PATTERN
13
FN7941.1
February 26, 2013
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