an1798

Application Note 1798
Author: Raymond Ho
ISL1561 Application Note
Introduction
Power Sequencing and Reset
The ISL1561 is a fixed gain dual port class-G differential
amplifier design for driving ADSL2+ and VDSL2 at reduced
power consumption, compared to class AB amplifiers. The line
driver operates on a single +12V to +14V supply and will
generate a higher supply voltage when boosting is detected.
The quiescent current can be programmed with a 12-bit
command through the 3 pin serial port interface (SPI).
The SPI pins can be left floating or pulled low before applying
the power supply. An internal 5V VDD is generated for the
digital interface. The SPI and BOOST pins are internally biased
as follows:
• CS Pin: internal pull-up to VDD
• SDATA Pin: internal pull-down to GND
Highlights
The ISL1561 is Intersil’s most efficient dual port line driver for
ADSL2+ and VDSL2 applications operating on a +14V supply.
A new feature supported on the ISL1561 is programming of
the quiescent current through SPI. Given a targeted MTPR
performance, quiescent current can be adjusted accordingly to
reduce power (500µA steps). When transmitting 8b VDSL2,
power consumption can be 25% less compared to class AB
operation (refer to page 1 in the datasheet). The ISL1561 is
very “robust” in handling transients; passing ITU-T K.20
standard tests.
Power Consumption
Figure 1 shows the power consumption comparison for 8b and
17a VDSL2 profiles. For 8b 19.5dBm, the ISL1561 only
consumes 600mW while achieving missing band power ratio
(MBPR) of -64dBc, and for 17a 14.5dBm, the ISL1561
consumes 400mW while achieving MBPR of -60dBc.
900
8b CLASS AB
800
POWER CONSUMPTION (mW)
• BOOST Pin: internal pull-up to VDD
700
17a CLASS AB
600
• SCLK Pin: internal pull-down to GND
The serial interface counter will reset while a clock cycle is
received with CS high. When CS is driven high, SCLK pulse will
reset the serial counter on the falling edge of SCLK.
Evaluation Software
The GUI software is available to program the ISL1561
evaluation board. Running “ISL1561_Installer_V1.0.exe” will
install the needed drivers for the program.
The program files will be installed in:
“C:\Program Files\Intersil\ISL1561” and the file to run is
“ISL1561.exe”.
NOTE: When running the program, be sure the micro-controller is
connected to the computer’s USB port.
Figure 2 shows that the ISL1561 starts up in disable mode.
Clicking “Read All” will have both registers display “80”. The
two register boxes allow users to write and read. For example,
when a user clicks in the box and types “0F”, the program also
puts back in the same box the read register value, which is
also “0F”. If a different value is displayed, the register is not
programmed correctly.
500
400
8b CLASS G
300
200
17a CLASS G
100
0
2
4
6
8
10
12
14
Tx POWER (dBm)
16
18
20
FIGURE 1. CLASS AB vs CLASS G POWER CONSUMPTION
SPI Control
The ISL1561 supply current can be programmed separately for
each port with the USB micro-controller integrated on the
evaluation board. The micro-controller uses four logic signals
(SCLK, SDI, SDO and CS) to communicate with the ISL1561’s
three pin SPI: (SCLK, SDATA and CS). Since SDATA for the
ISL1561 is used for both data in and out, a series 10kΩ is
placed between SDI and SDO. Therefore, SDI must be
connected directly to SDATA in order for the micro-controller to
read the registers in the ISL1561.
December 5, 2012
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1
FIGURE 2. WINDOW GUI
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Copyright Intersil Americas Inc. 2012. All Rights Reserved.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
OUT_A
C1AB/BOOST
C0AB/SDATA
T1
3
1
1
3
8
2
C0AB/SDATA
SHORT TRACE TO FBA
S2
DSL03-024SC6
Protection Network
R31
SDATA
49.9
R20
R21
5.1
5.1
49.9
2
C5
4
C4
CS
R4
19
20
21
FBB
VOUTA
VOUTB
VOUTC
C8
0.1µF
2.2µF
R32
17
16
C9
C19
2.2µF
1.0µF
CPSW
0.0
15
14
C10
C20
2.2µF
1.0µF
R33
CMSW
13
FBC
GND
12
11
+14V
IND
SCLK
C7
0.0
VOUTD
0.1µF
49.9
8
VIND+
CMSW
10
VINC+
6
C3
CMM
C0CD/SCLK
5
INC
R3
OUT_B
C9, C10, C19 and C20 placed close to pins
VCMCD
C1CD/CS
0.1µF
R28
10k
22
23
24
CPP
18
ISL1561IRZ
C6
SDATA
R29
0
+VS
VCMAB
7
PC0/RXD0
PC1/TXD0
PC2/INT0
PC3/INT1
PC4/T0
PC5/T1
PC6/WR
PC7/RD
3
0.1µF
TP3
CS
4
+14V
CPSW
FBD
PB0/T2
PB1/T2EX
PB2/RXD2
PB3/TXD2
PB4/INT4
PB5/INT5
PB6/INT6
PB7/T2OUT
TP2
SCLK
R34
100
RJ2
OPEN
0.1µF
CS
49.9
RJ3
OPEN
C1CD/CS
SHORT TRACE TO FBC
R36
OUT_C
SCLK
49.9
C0CD/SCLK
R37
R23
R22
5.1
5.1
8
2
2
USB PORT
SHORT TRACE TO FBD
S4
S3
1
3
1
3
49.9
+3.3V
+14V
D2
10k
D1
C17 +
BAT42
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GND
TP20
GND
C1CD/CS
C0CD/SCLK
3.3V
TP21
GND
4.7µf
TP22 TP23
SGND SGND
SGND
FIGURE 3. EVALUATION BOARD SCHEMATIC
1
6
3
7
2
C23
100nF
5
+3.3V
RV
+14V
DSL03-024SC6
Protection Network
T2
C24
R35
33nF
100
4
1:1.4
OUT_D
Application Note 1798
VINB+
9
1
VINA+
FBA
1
0.1µF
C1AB/BOOST
49.9
J1
TP1
SDATA
C22
33nF
1:1.4
U1
C0AB/SDATA
2
0.1µF
C2
SDA
SCL
2
OPEN
49.9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
7
RJ1
R30
C1
R2
3
SHORT TRACE TO FBB
INA
INB
6
5
BOOSTAB
R1
C21
100nF
2
S1
1
+3.3V
Application Note 1798
Programming Quiescent Current
Table 1 is the representation of quiescent current given the
values entered in the register boxes. The register boxes in the GUI
accept hexadecimal. A complete Iq vs. Reg Values is shown in
Figure 20 of the ISL1561 datasheet. Entering “0F” in the box will
change the quiescent current to 7.2mA for that port. To change to
a different value, users can click in the box to highlight the
previous value and enter a new value.
TABLE 1. REGISTER VALUES vs Iq
VALUES IN PORTAB OR
PORTCD BOX (8’h)
Iq PER PORT
(mA)
80
2.5
0F
7.2
1C
10.3
7F
19.5
When the previous value is highlighted, users can also use the up
and down arrow keys on the keyboard to change the value. If
current value is “0F”, pressing the arrow key down will change
the value to “0E” and pressing the key up will change the value to
“10”. Each step changes quiescent current by 500µA for the
selected port.
The range of quiescent current for each port with the most
significant bit (MSB) low is 8’h00 to 8’h7F and with MSB high is
8’h80 to 8h’FF. To change the quiescent current to 10.3mA/port,
entering “1C” is the same as entering “9C” in the registers. The
latter sets the MSB high. Be careful when setting the MSB high
for both ports because this will over-ride boost operation as
discussed in “Boost Signal and Operation” on page 4.
When verifying reading and writing to the registers on an
oscilloscope, note the least significant bit (LSB) is loaded first
and the MSB is loaded last. The scope will display a “F0” instead
of a “0F” because the micro-controller reads MSB first. Bit
swapping was implemented on the software to load LSB first.
Figure 4 is a scope capture of SDATA in yellow, SCLK in red and
CS in blue. From left to right, SDATA shows the first bit is low,
which defines read. The next 3 bits, 110, defines reg3 as being
read. The following 8 bits, 11110000, defines reg3 has the value
of “F0”. Reading and writing to the register only occurs when CS,
is held low. Figure 5 illustrates the 12-bit command to program
the quiescent current of each port in the ISL1561.
FIGURE 4. SDATA = “FO” IN PORTAB (REG3)
0
1
2
3
SCLK
Z-HI
W/R
SDATA
CS
ADDR[0:2]
D[0] D[1] D[2]
D[3] D[4]
D[5]
D[6] D[7]
Z-HI
CURRENT SETTING VALUE
FIGURE 5. 12-BIT COMMAND FOR SDATA
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Application Note 1798
Table 2 outlines the first 4-bit to read and write to reg3 and reg7.
Combining Table 1 and 2 gives the 12-bit command line. The
following are examples of commands:
1. After start-up, users want to read reg3. Default reg3 value is
8’h08. [011000000001]
2. Users want to change the quiescent current in reg3(PortAB) to
10.3mA. This is the same as writing the value of 8’hC1 in
reg3. [111000111000]
3. Users want to change the quiescent current in reg7(PortCD) to
10.3mA. [111100111000]
4. Users want to disable reg3. [111000000001]
TABLE 2. 4-BIT COMMAND TO READ AND WRITE TO REGISTERS
excess power dissipation by putting the driver in permanent
boost mode. In order to satisfy the firmware in detecting the
ISL1561 at start-up with boost pin pulled high, boost operation
had to be over-ridden and turned off. Having the MSB high for
both reg3 and reg7 will over-ride boost operations. By default,
the ISL1561 turns boost operation off with reg3 and reg7 having
values of 8’h08 to over-ride boosting and resolve any undesirable
power-up states. Table 3 shows boost operation is turned off
when MSB for both registers is high, even with the presence of a
boost signal.
TABLE 3. REGISTER MSB ON BOOST OPERATION
REG3
8’h[7]
REG7
8’h[7]
BOOST
PIN
BOOST
OPERATION
REGISTERS
READ
WRITE
0
X
1
1
REG3(PORTAB)
0110
1110
X
0
1
1
REG7(PORTCD)
0111
1111
1
1
X
0
X
X
0
0
Boost Signal and Operation
NOTE: X = do not care
The boost pin has an internal pull-up to help detect the presence
of the ISL1561 in Broadcom’s reference design. Do not place an
external resistor to ground on the boost pin since this will conflict
with Broadcom’s firmware to detect the ISL1561 as the line
driver. Putting the ISL1561 in boost mode with the boost pin high
at power up is not recommended because this can result in
Figure 6 shows normal boost operation with the boost signal in
red, voltage on the CPSW pin in blue, and the output signal in
green. The port has the value of 8’hC1 representing the MSB low.
NOTE: Figure 6 also shows the look-ahead boost timing is 100ns, as
recommended in Figure 29 of the datasheet.
FIGURE 6. BOOST OPERATIONS
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Application Note 1798
FIGURE 7. OVER-RIDING BOOST OPERATIONS
FIGURE 8. BOOST SIGNAL (GREEN), OUTA (BLUE), OUTB (PINK), DIFFOUTAB (YELLOW)
Figure 7 shows over-riding of boost operation. Both ports are
programmed to a value of 8’hC9 (MSB high). Even with a boost
signal present, the supply voltage is not boosted because
boosting is disabled when MSB is high for both ports. With
boosting disable, the output signal is clipped because the output
is being over driven hitting the supply headroom.
Figure 8 shows scope captures of the output waveform with the
supply voltage being boosted. A noticeable ringing at each of the
output happens during the rising edge of each boost. The ringing
is common mode and does not affect differential performance
as the bottom curve shows no ringing in the differential the
output.
Board Design Recommendation
It is recommended to operate ISL1561 with less than 45pF of
common mode parasitic on any of the four outputs. To minimize
parasitic capacitance in the ISL1561 design, consider laying out
5
short output traces, and selecting low capacitance protection
devices, and line transformers with low interwinding capacitance
in the signal path.
Close placement of the boost capacitors to the boost pins is
necessary to minimize parasitic inductance in the boost supply
path. On the ISL1561 evaluation board, 1µF and 2.2µF
capacitors are used instead of one in order to place the smaller
footprint 1µF capacitor close to the boost pins. An increase in
ringing at the outputs caused by the rising edge of each boost
event is observed if the boost capacitors are moved away from
the package pins. Adding 5Ω in series with the boost capacitors
will help reduce this common mode ringing.
The supply decoupling capacitors are also placed close to the
supply pins to minimize parasitic inductance in the supply path.
High frequency load currents are typically pulled through these
capacitors so close placement of 0.1µF capacitors on the supply
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December 5, 2012
Application Note 1798
pin will improve dynamic performance. The higher 2.2µF value
capacitors can be placed further from the supply pins as it
provides low frequency decoupling.
The thermal pad for the ISL1561 should be connected to ground.
For good thermal control, running vias to a bottom pad helps
dissipate heat away from the package.
Lightning Surge Robustness
The ISL1561 is very robust to lightning transients at the output.
Intersil recommends using a tertiary protection device,
TISP4C035L1N, along with a line protection device, 420V GDT
(both from Bourns), to pass 10/700µs, 4kV surges and 600Vrms
power induction tests. An alternate tertiary protection device,
ST’s DSL03-024SC6, also is shown to pass k20e tests.
INTERSIL’S EVAL BOARD
1:1.4
5.1Ω
TIP
LINE
DRIVER
5.1Ω
PROTECTION
DEVICE
RING
FIGURE 9. CIRCUIT PROTECTION CONFIGURATION
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is
cautioned to verify that the Application Note or Technical Brief is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
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