DATASHEET

CT
O D U EM EN T
R
P
TE
AC
O LE
E PL
O B S N D ED R B
5504
MME
ECO SheetHC
RData
®
ITU Low Cost, PABX SLIC With 40mA
Loop Feed
The Intersil SLIC is ideally suited for the design of new digital
PBX systems by eliminating bulky hybrid transformers.
Part Number Information
HC4P5504B1-5
0 to 75
PACKAGE
28 Ld PLCC
PKG. DWG.
#
N28.45
• Capable of 5V or 12V (VB+) Operation
• Monolithic Integrated Device
• DI High Voltage Process
• Compatible With Worldwide PBX Performance
Requirements
• Controlled Supply of Battery Feed Current for Short Loops
(41mA)
• Internal Ring Relay Driver
• Allows Interfacing With Negative Superimposed Ringing
Systems
• Low Power Consumption During Standby
• Switch Hook Ground Key and Ring Trip Detection
Functions
• Selective Denial of Power to Subscriber Loops
Applications
• Solid State Line Interface Circuit for Analog and Digital
PBX Systems
Pinout
• Direct Inward Dial (DID) Trunks
HC-5504B1 (PLCC)
TOP VIEW
RFS
RING
TIP
N/C
TX
AG
C4
• Voice Messaging PBXs
4
3
2
1
28
27
26
VB+
5
25 RX
C3
6
24 +IN
DG
7
23 -IN
N/C
8
22 N/C
RS
9
21 OUT
RD 10
20 C2
TF
19 RC
12
13
14
15
16
17
18
RF
VB-
BG
N/C
SHD
GKD
PD
11
1
FN4125.4
• Low Cost Version of the HC-5504B
The SLIC also provides selective denial of power. If the PBX
system becomes overloaded during an emergency, the SLIC
will provide system protection by denying power to selected
subscriber loops.
PART NUMBER
August 2003
Features
The Intersil SLIC incorporates many of the BORSHT
functions on a single IC chip. This includes DC battery feed,
a ring relay driver, supervisory and hybrid functions. This
device is designed to maintain transmission performance in
the presence of externally induced longitudinal currents.
Using the unique Intersil dielectric isolation process, the
SLIC can operate directly with a wide range of station battery
voltages.
TEMP.
RANGE (oC)
HC-5504B1
• Related Literature
- AN549, The HC-5502S/4X Telephone Subscriber Line
Interface Circuits (SLIC)
- AN571, Using Ring Sync with HC-5502A and HC-5504
SLICs
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HC-5504B1
Absolute Maximum Ratings (Note 1)
Thermal Information
Maximum Continuous Supply Voltages
(VB-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -60 to 0.5V
(VB+) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 15V
(VB+ - VB-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75V
Relay Drive Voltage (VRD). . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 15V
Thermal Resistance (Typical, Note 2)
θJA (oC/W)
28 Lead PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
65
Maximum Junction Temperature Plastic . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(PLCC - Lead Tips Only)
Operating Conditions
Operating Temperature Range
HC-5504B1-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC
Relay Driver Voltage (VRD) . . . . . . . . . . . . . . . . . . . . . . . . 5V to 12V
Positive Supply Voltage (VB+) . . . 4.75V to 5.25V or 10.8V to 13.2V
Negative Supply Voltage (VB-) . . . . . . . . . . . . . . . . . . . -42V to -58V
High Level Logic Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 2.4V
Low Level Logic Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6V
Loop Resistance (RL) . . . . . . . . . . . . . . . . . . . . . . . .200Ω to 1200Ω
Die Characteristics
Transistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Diode Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Die Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 x 102
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connected
Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bipolar-DI
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Absolute maximum ratings are limiting values, applied individually, beyond which the serviceability of the circuit may be impaired. Functional
operability under any of these conditions is not necessarily implied.
2. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
Unless Otherwise Specified, VB- = -48V, VB+ = 12V and 5V, AG = BG = DG = 0V, Typical Parameters
TA = 25oC. Min-Max Parameters are Over Operating Temperature Range
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
On Hook Power Dissipation
ILONG = 0 (Note 2), VB+ = 12V
-
170
235
mW
Off Hook Power Dissipation
RL = 600Ω , ILONG = 0 (Note 3), VB+ = 12V
-
425
550
mW
Off Hook IB+
RL = 600Ω , ILONG = 0 (Note 3), TA = 25oC
-
-
5.3
mA
Off Hook IB-
RL = 600Ω, ILONG = 0 (Note 3)
-
35
41
mA
Off Hook Loop Current
RL = 1200Ω , ILONG = 0 (Note 3)
-
21
-
mA
Off Hook Loop Current
RL = 1200Ω , VB- = -42V, ILONG = 0 (Note 3)
TA = 25oC
17.5
-
-
mA
Off Hook Loop Current
RL = 200Ω , ILONG = 0 (Note 3)
36
41
48
mA
TIP to Ground
-
14
-
mA
RING to Ground
-
55
-
mA
TIP to RING
-
41
-
mA
TIP and RING to Ground
-
55
-
mA
Fault Currents
Ring Relay Drive VOL
IOL = 62mA
-
0.2
0.5
V
Ring Relay Driver Off Leakage
VRD = 12V, RC = 1 = HIGH, TA = 25oC
-
-
100
µA
Ring Trip Detection Period
RL = 600Ω
-
2
3
Ring
Cycles
Switch Hook Detection Threshold
SHD = VOL
10
-
-
mA
SHD = VOH
-
-
5
mA
GKD = VOL
20
-
-
mA
GKD = VOH
-
-
10
mA
RL = 200Ω
-
±2
-
mA
0
-
5
ms
Ground Key Detection Threshold
Loop Current During Power Denial
Dial Pulse Distortion
2
HC-5504B1
Electrical Specifications
Unless Otherwise Specified, VB- = -48V, VB+ = 12V and 5V, AG = BG = DG = 0V, Typical Parameters
TA = 25oC. Min-Max Parameters are Over Operating Temperature Range (Continued)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Receive Input Impedance
(Note 4)
-
110
-
kΩ
Transmit Output Impedance
(Note 4)
-
10
20
Ω
2-Wire Return Loss
(Referenced to 600Ω + 2.16µF), (Note 4)
SRL LO
-
15.5
-
dB
ERL
-
24
-
dB
SRL HI
-
31
-
dB
53
58
-
dB
2-Wire On Hook
53
58
-
dB
4-Wire Off Hook
50
58
-
dB
-
-
23
dBrnC
-
-
-67
dBm0p
-
±0.05
±0.2
dB
-
±0.02
±0.05
dB
-
1
5
dBrnC
-
-89
-85
dBm0p
-
-
2
ms
Longitudinal Balance
1VRMS 200Hz - 3400Hz, (Note 4) IEEE Method
0oC ≤ TA ≤ 75oC
2-Wire Off Hook
Low Frequency Longitudinal Balance
Insertion Loss
R.E.A. Method, (Note 4), RL = 600Ω
0oC ≤ TA ≤ 75oC
At 1kHz, 0dBm Input Level, Referenced 600Ω
2-Wire to 4-Wire, 4-Wire to 2-Wire
Frequency Response
200 - 3400Hz Referenced to Absolute Loss at 1kHz
and 0dBm Signal Level (Note 4)
Idle Channel Noise
(Note 4)
2-Wire to 4-Wire, 4-Wire to 2-Wire
Absolute Delay
(Note 4)
2-Wire to 4-Wire, 4-Wire to 2-Wire
Trans Hybrid Loss
Balance Network Set Up for 600Ω Termination at
1kHz
30
40
-
dB
Overload Level
VB+ = +5V
1.5
-
-
VPEAK
VB+ = 12V
1.75
-
-
VPEAK
+3 to -40dBm
-
-
±0.05
dB
-40 to -50dBm
-
-
±0.1
dB
-50 to -55dBm
-
-
±0.3
dB
15
-
-
dB
VB+ to Transmit
15
-
-
dB
VB- to 2-Wire
15
-
-
dB
VB- to Transmit
15
-
-
dB
30
-
-
dB
VB+ to Transmit
30
-
-
dB
VB- to 2-Wire
30
-
-
dB
VB- to Transmit
30
-
-
dB
-
-
±100
µA
2-Wire to 4-Wire, 4-Wire to 2-Wire
Level Linearity
At 1kHz, (Note 4) Referenced to 0dBm Level
2-Wire to 4-Wire, 4-Wire to 2-Wire
Power Supply Rejection Ratio
(Note 4)
VB+ to 2-Wire
30 - 60Hz, RL = 600Ω
VB+ to 2-Wire
200 - 16kHz, RL = 600Ω
Logic Input Current (RS, RC, PD)
3
0V ≤ VIN ≤ 5V
HC-5504B1
Electrical Specifications
Unless Otherwise Specified, VB- = -48V, VB+ = 12V and 5V, AG = BG = DG = 0V, Typical Parameters
TA = 25oC. Min-Max Parameters are Over Operating Temperature Range (Continued)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Logic ‘0’ VIL
-
-
0.8
V
Logic ‘1’ VIH
2.0
-
5.5
V
-
0.1
0.5
V
Logic Inputs
Logic Outputs
Logic ‘0’ VOL
ILOAD 800µA, VB+ = 12V, 5V
Logic ‘1’ VOH
ILOAD 80µA, VB+ = 12V
2.7
5.0
5.5
V
ILOAD 40µA, VB+ = 5V
2.7
-
5.0
V
Uncommitted Op Amp Specifications
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Input Offset Voltage
-
±5
-
mV
Input Offset Current
-
±10
-
nA
Input Bias Current
-
20
-
nA
Differential Input Resistance
(Note 4)
-
1
-
MΩ
Output Voltage Swing
RL = 10K, VB+ = 12V
-
±6.2
±6.6
VPEAK
RL = 10K, VB+ = 5V
-
±3
-
VPEAK
Output Resistance
AVCL = 1 (Note 4)
-
10
-
Ω
Small Signal GBW
(Note 4)
-
1
-
MHz
NOTES:
3. ILONG = Longitudinal Current.
4. These parameters are controlled by design or process parameters and are not directly tested. These parameters are characterized upon initial
design release, upon design changes which would affect these characteristics, and at intervals to assure product quality and specification
compliance.
4
HC-5504B1
Pin Descriptions
28 PIN
PLCC
SYMBOL
DESCRIPTION
2
TIP
An analog input connected to the TIP (more positive) side of the subscriber loop through a 150Ω feed resistor and a ring
relay contact. Functions with the Ring terminal to receive voice signals from the telephone and for loop monitoring
purposes.
3
RING
An analog input connected to the RING (more negative) side of the subscriber loop through a 150Ω feed resistor and a
ring relay contact. Functions with the Tip terminal to receive voice signals from the telephone and for loop monitoring
purposes.
4
RFS
Senses ring side of loop for ground key and ring trip detection. During ringing, the ring signal is inserted into the line at
this node and RF is isolated from RFS via a relay.
5
VB+
Positive Voltage Source - Most positive supply. VB+ is typically 12V or 5V.
6
C3
Capacitor #3 - An external capacitor to be connected between this terminal and analog ground. Required for proper
operation of the loop current limiting function, and for filtering VB-. Typical value is 0.3µF, 30V.
7
DG
Digital Ground - To be connected to zero potential and serves as a reference for all digital inputs and outputs on the SLIC
microcircuit.
9
RS
Ring Synchronization Input - A TTL - compatible clock input. The clock should be arranged such that a positive pulse
transition occurs on the zero crossing of the ring voltage source, as it appears at the RFS terminal. For Tip side injected
systems, the RS pulse should occur on the negative going zero crossing and for Ring injected systems, on the positive
going zero crossing. This ensures that the ring relay activates and deactivates when the instantaneous ring voltage is
near zero. If synchronization is not required, the pin should be tied to 5V.
10
RD
Relay Driver - A low active open collector logic output. When enabled, the external ring relay is energized.
11
TF
Tip Feed - A low impedance analog output connected to the TIP terminal through a 150Ω feed resistor. Functions with
the RF terminal to provide loop current, feed voice signals to the telephone set, and sink longitudinal current.
12
RF
Ring Feed - A low impedance analog output connected to the RING terminal through a 150Ω feed resistor. Functions with
the TF terminal to provide loop current, feed voice signals to the telephone set, and sink longitudinal current.
13
VB-
Negative Voltage Source - Most negative supply. VB- is typically -48V with an operational range of -42V to -58V.
Frequently referred to as “battery”.
14
BG
Battery Ground - To be connected to zero potential. All loop current and some quiescent current flows into this ground
terminal.
16
SHD
Switch Hook Detection - A low active LS TTL-compatible logic output. This output is enabled for loop currents exceeding
10mA and disabled for loop currents less than 5mA.
17
GKD
Ground Key Detection - A low active LS TTL-compatible logic output. This output is enabled if the DC current into the ring
lead exceeds the DC current out of the tip lead by more than 20mA, and disabled if this current difference is less than
10mA.
18
PD
Power Denial - A low active TTL - Compatible logic input. When enabled, the switch hook detect (SHD) and ground key
detect (GKD) are not necessarily valid, and the relay driver (RD) output is disabled.
19
RC
Ring Command - A low active TTL - Compatible logic input. When enabled, the relay driver (RD) output goes low on the
next high level of the ring sync (RS) input, as long as the SLIC is not in the power denial state (PD = 0) or the subscriber
is not already off- hook (SHD = 0).
20
C2
Capacitor #2 - An external capacitor to be connected between this terminal and digital ground. Prevents false ground key
indications from occurring during ring trip detection. Typical value is 0.15µF, 10V. This capacitor is not used if ground key
function is not required and (Pin 17) may be left open or connected to digital ground.
21
OUT
23
-IN
The inverting analog input of the spare operational amplifier.
24
+IN
The non-inverting analog input of the spare operational amplifier.
25
RX
Receive Input, Four Wire Side - A high impedance analog input which is internally biased. Capacitive coupling to this input
is required. AC signals appearing at this input differentially drive the Tip feed and Ring feed terminals, which in turn drive
tip and ring through 300Ω of feed resistance on each side of the line.
The analog output of the spare operational amplifier. The output voltage swing is typically ±5V.
5
HC-5504B1
Pin Descriptions
(Continued)
28 PIN
PLCC
SYMBOL
DESCRIPTION
26
C4
Capacitor #4 - An external capacitor to be connected between this terminal and analog ground. This capacitor prevents
false ground key indication and false ring trip detection from occurring when longitudinal currents are induced onto the
subscriber loop from near by power lines and other noise sources. This capacitor is also required for the proper operation
of ring trip detection. Typical value is 0.5µF, to 1.0µF, 20V. This capacitor should be nonpolarized.
27
AG
Analog Ground - To be connected to zero potential and serves as a reference for the transmit output (TX) and receive
input (RX) terminals.
28
TX
Transmit Output, Four Wire Side - A low impedance analog output which represents the differential voltage across Tip
and Ring. Transhybrid balancing must be performed (using the SLIC microcircuit’s spare op amp) beyond this output to
completely implement two to four wire conversion. This output is unbalanced and referenced to analog ground. Since the
DC level of this output varies with loop current, capacitive coupling to the next stage is essential.
1, 8,
15, 22
NC
No internal connection.
NOTE: All grounds (AG, BG, and DG) must be applied before VB+ or VB-. Failure to do so may result in premature failure of the part. If a user wishes
to run separate grounds off a line card, the AG must be applied first.
Functional Diagram
RING SYNC
RING COMMAND
RING
TRIP
RS
RC
RD
RING
CONTROL
SHD SWITCH HOOK
DETECTION
GKD GROUND KEY
LOOP
MONITORING
DETECTION
1/2 RING
RELAY
TIP
TIP
150Ω
DIFF
AMP
+
150Ω
TX
TRANSMIT
OUTPUT
TF
2-WIRE
LOOP
VBSECONDARY
PROTECTION
BATTERY
FEED
VB-
OUT
+1
BG
+IN
RF
LOOP
CURRENT
LIMITER
RFS
1/2 RING
RELAY
LINE
DRIVERS
-IN
150Ω
RING
150Ω
RING
VOLTAGE
+
OP
AMP
RING
POWER DENIAL
V B-
6
PD
-1
SLIC MICROCIRCUIT
RX
RECEIVE
INPUT
HC-5504B1
Schematic
SLIC FUNCTIONAL SCHEMATIC
DIP/SOIC Pin Numbers Shown
21
22
11
12
23
6
4
20
19
18
RX
C4
VBAT
BAT
GND
ANA
GND
DIG
GND
VB+
+
-
OUT
VB+
VB+
VB1
VB2
VB3
VB4
VB5
5V
VOLTAGE AND CURRENT
BIAS NETWORK
A-400
TIP FEED
AMP
TF
9
R17
+
VB+
VB2
VBAT
RING TRIP DETECTOR
R12
R7
TIP
1
VB+
QD3 QD36
VB+
+
RING
FEED
SENSE
R9
3
R22
GK
R20
A-200
LONG’L
I / V AMP
R10
R11
VBAT
IB7
2
R1
-
R14
13
VB1
IB6
QD27
R18
R21
QD28
RC
THERMAL
LIMITING
LOAD CURRENT
LIMITING I
B2
16
RFC
VB5
-
PD
VB5
+
15
R19
VBAT
IB5
R13
VBAT
VBAT
C3
TX
RS
RD
5
24
7
8
7
17
SHD
SH
-
+
+
VBAT
C2
VB+
A-300
RING FEED
AMP
10
STTL
AND LOGIC
INTERFACE
VBAT
VBAT
VBAT/2 REFERENCE
VB2
RF
SWITCH HOOK
DETECTOR
R6
R15
+
VB3
IB6
R16
14
IB1
-
-
GKD
GND SHORTS
CURRENT
LIMITING
VB+
A-100
TRANSV’L
I/V AMP
R2
VB4
IB8
+
R4
VBAT
+
VBAT
R5
V + VBAT
R23 B
R3
RING
5V IB10 VB+
5V
-
R8
VBAT
IB3
IB1 IB2 IB3 IB4 IB5 IB6 IB7 IB8 VBAT IB9 IB10 IB11
-
IB4
A-500
OP AMP
HC-5504B1
Schematic
(Continued)
LOGIC GATE SCHEMATIC
C2
GK
1
LOGIC BIAS
2
DELAY
4
SH
6
8
7
9
3
5
12
16
10
13
11
RELAY
DRIVER
14
15
TTL
TO
STTL
TTL
TO
STTL
TTL
TO
STTL
TO
R21
A
STTL
TO
TTL
STTL
TO
TTL
C
B
A
B
RS
RC
PD
C
RD
SHD
GKD
SCHOTTKY LOGIC
Overvoltage Protection and Longitudinal
Current Protection
TABLE 1.
PERFORMANCE
(MAX)
UNITS
10µs Rise/
1000µs Fall
±1000 (Plastic)
VPEAK
Metallic Surge
10µs Rise/
1000µs Fall
±1000 (Plastic)
VPEAK
T/GND
R/GND
10µs Rise/
1000µs Fall
±1000 (Plastic)
VPEAK
50/60Hz Current
T/GND
R/GND
11 Cycles
Limited to
10ARMS
700 (Plastic)
VRMS
PARAMETER
The SLIC device, in conjunction with an external protection
bridge, will withstand high voltage lightning surges and
power line crosses.
Longitudinal
Surge
High voltage surge conditions are as specified in Table 1.
The SLIC will withstand longitudinal currents up to a
maximum or 30mARMS , 15mARMS per leg, without any
performance degradation.
8
TEST
CONDITION
HC-5504B1
Applications Diagram
5V TO
12V
SYSTEM CONTROLLER
15
RS1 CS1
K1
RB1
K1A
TIP
RB2
(NOTE 5)
SUBSCRIBER
LOOP
PRIMARY
PROTECTION
13
14
7
16
POWER SWITCH GROUND RING RING
SYNC CMD
DENIAL HOOK
KEY
8
DETECT DETECT
RD
RX
1
TIP
TX
9
SLIC
TIP FEED
+IN
HC-5504B1
-IN
OP AMP
VB K1B
OUT
10
RING FEED
RS2
CS2
RB3
RING
3
C2
RING FEED SENSE
C3
RB4
2
RING
C4
NEG.
BATT.
BATT.
GND.
DIG.
GND.
ANA.
GND.
VB+
11
12
6
23
4
PTC
C8
-48V
C9
BALANCE NETWORK
C5
21
C6
24
20
R1
C7
PCM
SWITCHING
FILTER/ NETWORK
CODEC
ZB
19
R3
R2
18
17
5
22
+
C4 C3 C2
+
VB+
150VPEAK (MAX)
Z1
RING GENERATOR
PIN NUMBERS GIVEN FOR DIP/SOIC PACKAGE.
-48V
FIGURE 1. TYPICAL LINE CIRCUIT APPLICATION WITH THE MONOLITHIC SLIC
Typical Component Values
C2 = 0.15µF, 10V.
R1 = R2 = R3 = 100kΩ (0.1% Match Required, 1% absolute
value) ZB = 0 for 600Ω Terminations (Note 6).
C3 = 0.3µF, 30V.
C4 = 0.5µF to 1.0µF, 10%, 20V (Should be nonpolarized).
C5 = 0.5µF, 20V.
RB1 = RB2 = RB3 = RB4 = 150Ω (0.1% Match Required, 1%
absolute value).
RS1 = RS2 = 1kΩ, typically.
C6 = C7 = 0.5µF (10% Match Required) (Note 6).
C8 = 0.01µF, 100V.
CS1 = CS2 = 0.1µF, 200V typically, depending on VRING
and line length.
C9 = 0.01µF, 20V, ±20%.
Z1 = 150V to 200V transient protection.
PTC used as ring generator ballast.
NOTES:
5. Secondary protection diode bridge recommended is a 2A, 200V type.
6. To obtain the specified transhybrid loss it is necessary for the three legs of the balance network, C6-R1 and R2 and C7-ZB-R3, to match in
impedance to within 0.3%. Thus, if C6 and C7 are 1µF each, a 20% match is adequate. It should be noted that the transmit output to C6 sees
a -22V step when the loop is closed. Too large a value for C6 may produce an excessively long transient at the op amp output to the PCM
Filter/CODEC.
7. A 0.5µF and 100kΩ gives a time constant of 50ms. The uncommitted op amp output is internally clamped to stay within ±6.6V and is current
limited.
8. All grounds (AG, BG, and DG) must be applied before VB+ or VB-. Failure to do so may result in premature failure of the part. If a user wishes
to run separate grounds off a line card, the AG must be applied first.
9. Application shows Ring Injected Ringing, Balanced or Tip injected configuration may be used.
9
HC-5504B1
Plastic Leaded Chip Carrier Packages (PLCC)
0.042 (1.07)
0.048 (1.22)
PIN (1) IDENTIFIER
0.042 (1.07)
0.056 (1.42)
0.004 (0.10)
C
0.025 (0.64)
R
0.045 (1.14)
0.050 (1.27) TP
C
L
D2/E2
C
L
E1 E
D2/E2
VIEW “A”
0.020 (0.51)
MIN
A1
A
D1
D
N28.45 (JEDEC MS-018AB ISSUE A)
28 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.165
0.180
4.20
4.57
-
A1
0.090
0.120
2.29
3.04
-
D
0.485
0.495
12.32
12.57
-
D1
0.450
0.456
11.43
11.58
3
D2
0.191
0.219
4.86
5.56
4, 5
E
0.485
0.495
12.32
12.57
-
E1
0.450
0.456
11.43
11.58
3
E2
0.191
0.219
4.86
5.56
4, 5
N
28
28
6
Rev. 2 11/97
SEATING
-C- PLANE
0.020 (0.51) MAX
3 PLCS
0.026 (0.66)
0.032 (0.81)
0.025 (0.64)
MIN
0.045 (1.14)
MIN
0.013 (0.33)
0.021 (0.53)
VIEW “A” TYP.
NOTES:
1. Controlling dimension: INCH. Converted millimeter dimensions are
not necessarily exact.
2. Dimensions and tolerancing per ANSI Y14.5M-1982.
3. Dimensions D1 and E1 do not include mold protrusions. Allowable
mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1
and E1 include mold mismatch and are measured at the extreme
material condition at the body parting line.
4. To be measured at seating plane -C- contact point.
5. Centerline to be determined where center leads exit plastic body.
6. “N” is the number of terminal positions.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
10
Similar pages