Si3464DV Datasheet

New Product
Si3464DV
Vishay Siliconix
N-Channel 20-V (D-S) MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V)
20
RDS(on) (Ω)
ID (A)e
0.024 at VGS = 4.5 V
8a
0.028 at VGS = 2.5 V
8a
0.030 at VGS = 1.8 V
7.1
• Halogen-free According to IEC 61249-2-21
Definition
• TrenchFET® Power MOSFET
• 100 % Rg Tested
• Compliant to RoHS Directive 2002/95/EC
Qg (Typ.)
11 nC
APPLICATIONS
• DC/DC Converters
• Load Switch for Portable Applications
TSOP-6
Top View
D
1
6
D
D
(1, 2, 5, 6)
3 mm D
2
5
D
Marking Code
G
3
4
AZ
S
XXX
Lot Traceability
and Date Code
G
(3)
Part # Code
2.85 mm
(4)
S
Ordering Information: Si3464DV-T1-GE3 (Lead (Pb)-free and Halogen-free)
N-Channel MOSFET
ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted
Parameter
Drain-Source Voltage
Gate-Source Voltage
Symbol
VDS
VGS
TC = 25 °C
TC = 70 °C
TA = 25 °C
TA = 70 °C
Continuous Drain Current (TJ = 150 °C)
Pulsed Drain Current
Limit
20
±8
8a
8a
7.5b, c
6.0b, c
20
3
1.7b, c
3.6
2.3
2b, c
1.3b, c
- 55 to 150
260
ID
IDM
TC = 25 °C
TA = 25 °C
TC = 25 °C
TC = 70 °C
Maximum Power Dissipation
TA = 25 °C
TA = 70 °C
Operating Junction and Storage Temperature Range
Continuous Source-Drain Diode Current
IS
PD
TJ, Tstg
Soldering Recommendations (Peak Temperature)
Unit
V
A
W
°C
THERMAL RESISTANCE RATINGS
Parameter
Maximum Junction-to-Ambientb, d
Maximum Junction-to-Foot (Drain)
t≤5s
Symbol
RthJA
Typical
50
Maximum
62.5
Steady State
RthJF
28
35
Unit
°C/W
Notes:
a. Package limited
b. Surface Mounted on 1" x 1" FR4 board.
c. t = 5 s.
d. Maximum under steady state conditions is 110 °C/W.
e. Based on TC = 25 °C.
Document Number: 65712
S10-0218-Rev. A, 25-Jan-10
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1
New Product
Si3464DV
Vishay Siliconix
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
Parameter
Symbol
Test Conditions
Min.
VDS
VGS = 0 V, ID = 250 µA
20
Typ.
Max.
Unit
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
ΔVDS/TJ
V
23
ID = 250 µA
mV/°C
VGS(th) Temperature Coefficient
ΔVGS(th)/TJ
Gate-Source Threshold Voltage
VGS(th)
VDS = VGS , ID = 250 µA
1.0
V
IGSS
VDS = 0 V, VGS = ± 8 V
± 100
nA
VDS = 20 V, VGS = 0 V
1
VDS = 20 V, VGS = 0 V, TJ = 70 °C
10
Gate-Source Leakage
- 2.6
0.45
Zero Gate Voltage Drain Current
IDSS
On-State Drain Currenta
ID(on)
VDS ≤ 5 V, VGS = 4.5 V
VGS = 4.5 V, ID = 7.5 A
0.020
0.024
RDS(on)
VGS = 2.5 V, ID = 7.0 A
0.023
0.028
VGS = 1.8 V, ID = 6.7 A
0.025
0.030
VDS = 10 V, ID = 7.5 A
17
Drain-Source On-State Resistancea
Forward Transconductancea
gfs
µA
A
20
Ω
S
b
Dynamic
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Total Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
Gate Resistance
Rg
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
1065
VDS = 10 V, VGS = 0 V, f = 1 MHz
150
pF
70
VDS = 10 V, VGS = 5 V, ID = 7.5 A
12
18
11
17
1.8
VDS = 10 V, VGS = 4.5 V, ID = 7.5 A
1.1
f = 1 MHz
td(on)
0.4
2.2
4.4
5
10
15
23
43
65
tf
10
20
td(on)
3
6
12
18
tr
td(off)
tr
td(off)
nC
VDD = 10 V, RL = 1.7 Ω
ID ≅ 6 A, VGEN = 4.5 V, Rg = 1 Ω
VDD = 10 V, RL = 1.7 Ω
ID ≅ 6 A, VGEN = 5 V, Rg = 1 Ω
tf
22
33
8
16
Ω
ns
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulse Diode Forward Current
ISM
Body Diode Voltage
VSD
TC = 25 °C
3
20
IS = 6 A, VGS = 0 V
0.75
1.2
A
V
Body Diode Reverse Recovery Time
trr
15
23
ns
Body Diode Reverse Recovery Charge
Qrr
6
12
nC
Reverse Recovery Fall Time
ta
Reverse Recovery Rise Time
tb
IF = 6 A, dI/dt = 100 A/µs, TJ = 25 °C
8
7
ns
Notes:
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
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Document Number: 65712
S10-0218-Rev. A, 25-Jan-10
New Product
Si3464DV
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
20
5
V GS = 5 V thru 1.5 V
4
T C = - 55 °C
I D - Drain Current (A)
I D - Drain Current (A)
15
10
3
T C = 25 °C
2
5
1
T C = 125 °C
V GS = 1 V
0
0.0
0.5
1.0
1.5
0
0.0
2.0
0.3
0.9
1.2
V GS - Gate-to-Source Voltage (V)
V DS - Drain-to-Source Voltage (V)
Output Characteristics
Transfer Characteristics
1500
0.031
1200
Ciss
0.027
C - Capacitance (pF)
R DS(on) - On-Resistance (Ω)
0.6
V GS = 1.8 V
V GS = 2.5 V
0.023
V GS = 4.5 V
900
600
0.019
Coss
300
Crss
0
0.015
0
5
10
15
0
20
5
ID - Drain Current (A)
10
15
20
V DS - Drain-to-Source Voltage (V)
On-Resistance vs. Drain Current and Gate Voltage
Capacitance
1.6
V DS = 10 V
1.4
V DS = 5 V
V DS = 16 V
2
(Normalized)
4
R DS(on) - On-Resistance
VGS - Gate-to-Source Voltage (V)
ID = 7.5 A
V GS = 2.5 V; I D = 7 A
1.2
V GS = 4.5 V; I D = 7.5 A
1.0
0.8
0
0
3
6
9
Qg - Total Gate Charge (nC)
Gate Charge
Document Number: 65712
S10-0218-Rev. A, 25-Jan-10
12
0.6
- 50
- 25
0
25
50
75
100
125
150
T J - Junction Temperature (°C)
On-Resistance vs. Junction Temperature
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New Product
Si3464DV
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
0.05
100
R DS(on) - On-Resistance (Ω)
I S - Source Current (A)
ID = 7.5 A
T J = 150 °C
10
T J = 25 °C
1
0.04
T J = 125 °C
0.03
T J = 25 °C
0.02
0.01
0.00
0.1
0.0
0.2
0.4
0.6
0.8
0
1.0
2
4
6
8
V GS - Gate-to-Source Voltage (V)
V SD - Source-to-Drain Voltage (V)
On-Resistance vs. Gate-to-Source Voltage
Source-Drain Diode Forward Voltage
45
0.9
36
0.7
Power (W)
VGS(th) (V)
ID = 250 µA
0.5
27
18
0.3
9
0.1
- 50
0
- 25
0
25
50
75
100
125
150
0.001
0.01
0.1
1
10
Time (s)
T J - Temperature (°C)
Single Pulse Power (Junction-to-Ambient)
Threshold Voltage
100
Limited by R DS(on)*
100 μs
I D - Drain Current (A)
10
1 ms
1
10 ms
100 ms
TA = 25
Single Pulse
1 s, 10 s
0.1
DC
BVDSS Limited
0.01
0.1
1
10
100
V DS - Drain-to-Source Voltage (V)
* V GS > minimum VGS at which RDS(on) is specified
Safe Operating Area, Junction-to-Ambient
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Document Number: 65712
S10-0218-Rev. A, 25-Jan-10
New Product
Si3464DV
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
12
I D - Drain Current (A)
9
Package Limited
6
3
0
0
25
50
75
100
125
150
T C - Case Temperature (°C)
5
2.5
4
2.0
3
1.5
Power (W)
Power (W)
Current Derating*
2
1
1.0
0.5
0
0.0
0
25
50
75
100
125
T C - Case Temperature (°C)
Power Derating, Junction-to-Foot
150
0
25
50
75
100
125
150
TA - Ambient Temperature (°C)
Power Derating, Junction-to-Ambient
* The power dissipation PD is based on TJ(max.) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.
Document Number: 65712
S10-0218-Rev. A, 25-Jan-10
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New Product
Si3464DV
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
1
Normalized Effective Transient
Thermal Impedance
Duty Cycle = 0.5
0.2
0.1
Notes:
0.1
PDM
0.05
t1
0.02
t2
1. Duty Cycle, D =
t1
t2
2. Per Unit Base = R thJA = 110 °C/W
3. T JM - TA = PDMZthJA(t)
Single Pulse
4. Surface Mounted
0.01
10 -4
10 -3
10 -2
10 -1
1
Square Wave Pulse Duration (s)
100
10
1000
Normalized Thermal Transient Impedance, Junction-to-Ambient
1
Normalized Effective Transient
Thermal Impedance
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
10 -4
10 -3
10 -2
10 -1
Square Wave Pulse Duration (s)
1
10
Normalized Thermal Transient Impedance, Junction-to-Foot
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for
Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?65712.
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Document Number: 65712
S10-0218-Rev. A, 25-Jan-10
Package Information
Vishay Siliconix
TSOP: 5/6−LEAD
JEDEC Part Number: MO-193C
e1
e1
5
4
6
E1
1
2
5
4
E
E1
1
3
2
3
-B-
e
b
E
-B-
e
0.15 M C B A
5-LEAD TSOP
b
0.15 M C B A
6-LEAD TSOP
4x 1
-A-
D
0.17 Ref
c
R
R
A2 A
L2
Gauge Plane
Seating Plane
Seating Plane
0.08
C
L
A1
-C-
(L1)
4x 1
MILLIMETERS
Dim
A
A1
A2
b
c
D
E
E1
e
e1
L
L1
L2
R
Min
Nom
Max
Min
Nom
Max
0.91
-
1.10
0.036
-
0.043
0.01
-
0.10
0.0004
-
0.004
0.90
-
1.00
0.035
0.038
0.039
0.30
0.32
0.45
0.012
0.013
0.018
0.10
0.15
0.20
0.004
0.006
0.008
2.95
3.05
3.10
0.116
0.120
0.122
2.70
2.85
2.98
0.106
0.112
0.117
1.55
1.65
1.70
0.061
0.065
0.067
0.95 BSC
0.0374 BSC
1.80
1.90
2.00
0.071
0.075
0.079
0.32
-
0.50
0.012
-
0.020
0.60 Ref
0.024 Ref
0.25 BSC
0.010 BSC
0.10
-
-
0.004
-
-
0
4
8
0
4
8
7 Nom
1
ECN: C-06593-Rev. I, 18-Dec-06
DWG: 5540
Document Number: 71200
18-Dec-06
INCHES
7 Nom
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AN823
Vishay Siliconix
Mounting LITTLE FOOTR TSOP-6 Power MOSFETs
Surface mounted power MOSFET packaging has been based on
integrated circuit and small signal packages. Those packages
have been modified to provide the improvements in heat transfer
required by power MOSFETs. Leadframe materials and design,
molding compounds, and die attach materials have been
changed. What has remained the same is the footprint of the
packages.
The basis of the pad design for surface mounted power MOSFET
is the basic footprint for the package. For the TSOP-6 package
outline drawing see http://www.vishay.com/doc?71200 and see
http://www.vishay.com/doc?72610 for the minimum pad footprint.
In converting the footprint to the pad set for a power MOSFET, you
must remember that not only do you want to make electrical
connection to the package, but you must made thermal connection
and provide a means to draw heat from the package, and move it
away from the package.
In the case of the TSOP-6 package, the electrical connections are
very simple. Pins 1, 2, 5, and 6 are the drain of the MOSFET and
are connected together. For a small signal device or integrated
circuit, typical connections would be made with traces that are
0.020 inches wide. Since the drain pins serve the additional
function of providing the thermal connection to the package, this
level of connection is inadequate. The total cross section of the
copper may be adequate to carry the current required for the
application, but it presents a large thermal impedance. Also, heat
spreads in a circular fashion from the heat source. In this case the
drain pins are the heat sources when looking at heat spread on the
PC board.
Since surface mounted packages are small, and reflow soldering
is the most common form of soldering for surface mount
components, “thermal” connections from the planar copper to the
pads have not been used. Even if additional planar copper area is
used, there should be no problems in the soldering process. The
actual solder connections are defined by the solder mask
openings. By combining the basic footprint with the copper plane
on the drain pins, the solder mask generation occurs automatically.
A final item to keep in mind is the width of the power traces. The
absolute minimum power trace width must be determined by the
amount of current it has to carry. For thermal reasons, this
minimum width should be at least 0.020 inches. The use of wide
traces connected to the drain plane provides a low impedance
path for heat to move away from the device.
REFLOW SOLDERING
Vishay Siliconix surface-mount packages meet solder reflow
reliability requirements. Devices are subjected to solder reflow as a
test preconditioning and are then reliability-tested using
temperature cycle, bias humidity, HAST, or pressure pot. The
solder reflow temperature profile used, and the temperatures and
time duration, are shown in Figures 2 and 3.
Figure 1 shows the copper spreading recommended footprint for
the TSOP-6 package. This pattern shows the starting point for
utilizing the board area available for the heat spreading copper. To
create this pattern, a plane of copper overlays the basic pattern on
pins 1,2,5, and 6. The copper plane connects the drain pins
electrically, but more importantly provides planar copper to draw
heat from the drain leads and start the process of spreading the
heat so it can be dissipated into the ambient air. Notice that the
planar copper is shaped like a “T” to move heat away from the
drain leads in all directions. This pattern uses all the available area
underneath the body for this purpose.
0.167
4.25
0.074
1.875
0.014
0.35
0.122
3.1
0.026
0.65
0.049
1.25
0.049
1.25
0.010
0.25
FIGURE 1. Recommended Copper Spreading Footprint
Document Number: 71743
27-Feb-04
Ramp-Up Rate
+6_C/Second Maximum
Temperature @ 155 " 15_C
120 Seconds Maximum
Temperature Above 180_C
70 − 180 Seconds
Maximum Temperature
240 +5/−0_C
Time at Maximum Temperature
20 − 40 Seconds
Ramp-Down Rate
+6_C/Second Maximum
FIGURE 2. Solder Reflow Temperature Profile
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1
AN823
Vishay Siliconix
10 s (max)
255 − 260_C
1X4_C/s (max)
3-6_C/s (max)
217_C
140 − 170_C
60 s (max)
60-120 s (min)
Pre-Heating Zone
3_C/s (max)
Reflow Zone
Maximum peak temperature at 240_C is allowed.
FIGURE 3. Solder Reflow Temperature and Time Durations
THERMAL PERFORMANCE
TABLE 1.
Equivalent Steady State Performance—TSOP-6
Thermal Resistance Rqjf
30_C/W
On-Resistance vs. Junction Temperature
1.6
VGS = 4.5 V
ID = 6.1 A
1.4
rDS(on) − On-Resiistance
(Normalized)
A basic measure of a device’s thermal performance is the
junction-to-case thermal resistance, Rqjc, or the
junction-to-foot thermal resistance, Rqjf. This parameter is
measured for the device mounted to an infinite heat sink and
is therefore a characterization of the device only, in other
words, independent of the properties of the object to which the
device is mounted. Table 1 shows the thermal performance
of the TSOP-6.
1.2
1.0
0.8
0.6
−50
SYSTEM AND ELECTRICAL IMPACT OF
TSOP-6
−25
0
25
50
75
100
125
150
TJ − Junction Temperature (_C)
FIGURE 4. Si3434DV
In any design, one must take into account the change in
MOSFET rDS(on) with temperature (Figure 4).
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Document Number: 71743
27-Feb-04
Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR TSOP-6
0.099
0.039
0.020
0.019
(1.001)
(0.508)
(0.493)
0.064
(1.626)
0.028
(0.699)
(3.023)
0.119
(2.510)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
APPLICATION NOTE
Return to Index
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Document Number: 72610
Revision: 21-Jan-08
Legal Disclaimer Notice
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requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference
to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21
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Revision: 02-Oct-12
1
Document Number: 91000