DATASHEET

ISL8563E
®
Data Sheet
July 2004
+/-15kV ESD Protected, +3V to +5.5V,
1Microamp, 250kbps, EIA/TIA-562,
EIA/TIA-232 Transmitters/Receivers
Features
• ESD Protection for RS-562 I/O Pins to ±15kV (IEC61000)
The Intersil ISL8563E contains 3.0V to 5.5V powered
transmitters/receivers which meet ElA/TIA-562 and
ElA/TIA-232 specifications, even at VCC = 3.0V. Additionally,
they provide ±15kV ESD protection (IEC61000-4-2 Air Gap
and Human Body Model) on transmitter outputs and receiver
inputs (RS-562 pins). Targeted applications are PDAs,
Palmtops, and notebook and laptop computers where the
low operational, and even lower standby, power
consumption is critical. Efficient on-chip charge pumps,
coupled with a manual powerdown function, reduce the
standby supply current to a 1µA trickle. Small footprint
packaging, and the use of small, low value capacitors ensure
board space savings as well. Data rates greater than
250kbps are guaranteed at worst case load conditions. The
ISL8563E is fully compatible with 3.3V only systems, mixed
3.3V and 5.0V systems, and 5.0V only systems.
This product features an improved charge pump which
delivers ±5V transmitter supplies, allowing the use of the
ISL8563E in RS-562 and RS-232 applications. RS-562
applications will benefit from the improved noise immunity
afforded by the ±5V output swing capability.
Table 1 summarizes the features of the device represented
by this data sheet, while Application Note AN9863
summarizes the features of each device comprising the 3V
RS-232 family.
Ordering Information
PART NO.
TEMP.
RANGE (°C)
PACKAGE
PKG.
DWG. #
ISL8563ECB
0 to 70
18 Ld SOIC
M18.3
ISL8563ECB-T
0 to 70
Tape and Reel
M18.3
FN6002.2
• Drop in Replacement for MAX563, with Improved Output
Voltage (±5V) for Enhanced Noise Immunity
• Meets EIA/TIA-562, and EIA/TIA-232 Specifications at 3V
• RS-232 Compatible Outputs at 2.7V
• Latch-Up Free
• On-Chip Voltage Converters Require Only Four External
0.1µF Capacitors
• Receivers Active in Powerdown
• Receiver Hysteresis For Improved Noise Immunity
• Guaranteed Minimum Data Rate . . . . . . . . . . . . . 250kbps
• Guaranteed Minimum Slew Rate . . . . . . . . . . . . . . . 4V/µs
• Wide Power Supply Range . . . . . . . Single +3V to +5.5V
• Low Supply Current in Powerdown State. . . . . . . . . . .1µA
Applications
• Any System Requiring RS-562/RS-232 Communication
Ports
- Battery Powered, Hand-Held, and Portable Equipment
- Laptop Computers, Notebooks, Palmtops
- Digital Cameras
- Bar Code Readers
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Application Note AN9863, “3V to +5.5V, 250K-1Mbps,
RS-232 Transmitters/Receivers”
Pinout
ISL8563E (SOIC)
TOP VIEW
EN 1
17 VCC
V+ 3
16 GND
C1- 4
15 T1OUT
C2+ 5
14 R1IN
C2- 6
13 R1OUT
V- 7
12 T1IN
T2OUT 8
11 T2IN
R2IN 9
1
18 SHDN
C1+ 2
10 R2OUT
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2001, 2004. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL8563E
TABLE 1. SUMMARY OF FEATURES
NO. OF NO. OF
PART NUMBER
Tx.
Rx.
ISL8563E
2
NO. OF
MONITOR Rx.
(ROUTB)
DATA
RATE
(kbps)
Rx. ENABLE
FUNCTION?
READY
OUTPUT?
MANUAL
POWERDOWN?
AUTOMATIC
POWERDOWN
FUNCTION?
0
250
Yes
No
Yes
No
2
Pin Descriptions
PIN
VCC
FUNCTION
System Power Supply Input (3.0V to 5.5V).
V+
Internally Generated Positive Transmitter Supply (+5.5V).
V-
Internally Generated Negative Transmitter Supply (-5.5V).
GND
Ground Connection.
C1+
External Capacitor (Voltage Doubler) is connected to this lead.
C1-
External Capacitor (Voltage Doubler) is connected to this lead.
C2+
External Capacitor (Voltage Inverter) is connected to this lead.
C2-
External Capacitor (Voltage Inverter) is connected to this lead.
TIN
TTL/CMOS Compatible Transmitter Inputs with pull-up resistors.
TOUT
RIN
±15kV ESD Protected, RS-562/RS-232 level (nominally ±5.5V) transmitter outputs.
±15kV ESD Protected, RS-562/RS-232 compatible receiver inputs.
ROUT
TTL/CMOS Level Receiver Outputs.
EN
Active Low Receiver Enable Control.
SHDN
Active Low Input which shuts down transmitters and on-board power supply, to place device in low power mode.
Typical Operating Circuit
ISL8563E
+3.3V
+
0.1µF
C1
0.1µF
+
C2
0.1µF
+
2
4
5
6
17
C1+
VCC
V+
3
C1C2+
7
V-
C2-
+
VCC
T1IN
TTL/CMOS
LOGIC LEVELS
T2IN
R1OUT
12
400kΩ
T1
T2
400kΩ
14
5kΩ
R1IN
9
10
R2IN
5kΩ
R2
GND
16
2
T1OUT
8
13
1 EN
C4
0.1µF
T2OUT
R1
R2OUT
15
VCC
11
+
C3
0.1µF
SHDN
18
VCC
RS-562/232
LEVELS
ISL8563E
Absolute Maximum Ratings
Thermal Information
VCC to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V
V+ to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V
V- to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3V to -7V
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14V
Input Voltages
TIN, EN, SHDN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V
RIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25V
Output Voltages
TOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±13.2V
ROUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC +0.3V
Short Circuit Duration
TOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . See Specification Table
Thermal Resistance (Typical, Note 1)
θJA (°C/W)
18 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . .
75
Maximum Junction Temperature (Plastic Package) . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
(Lead Tips Only)
Operating Conditions
Temperature Range
ISL8563ECX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
Test Conditions: VCC = 3V to 5.5V, C1 - C4 = 0.1µF; Unless Otherwise Specified.
Typicals are at TA = 25°C
PARAMETER
TEST CONDITIONS
TEMP
(°C)
MIN
TYP
MAX
UNITS
RS-562/RS-232 TRANSMITTERS
Output Voltage Swing
All Transmitter Outputs Loaded with 3kΩ to Ground
Full
±5.0
±5.4
-
V
Maximum Data Rate
RL = 3kΩ, CL = 1000pF, One Transmitter Switching and
Maintaining ±5V Output Swing
Full
250
500
-
kbps
Input Logic Threshold Low
TIN
Full
-
-
0.8
V
Input Logic Threshold High
TIN
VCC = 3.0V to 5.0V
Full
2.4
-
-
V
Transmitter Pull-Up Input Current
TIN
SHDN = VCC
Full
-
2
20
µA
SHDN = GND
Full
-
±0.01
±1.0
µA
Output Leakage Current
VOUT = ±12V, VCC = 0V or 3.6V to 5.5V, SHDN = GND
Full
-
-
±10
µA
Output Resistance
VCC = V+ = V- = 0V, Transmitter Output = ±2V
Full
300
10M
-
Ω
Output Short-Circuit Current
VOUT = 0V
Full
-
±35
±60
mA
Full
-25
-
25
V
VCC = 3.3V
Full
-
1.2
0.6
V
VCC = 5.0V
Full
-
1.5
0.8
V
VCC = 3.3V
Full
2.4
1.5
-
V
VCC = 5.0V
Full
2.4
1.8
-
V
Full
0.1
0.5
1.0
V
Full
3
5
7
kΩ
-
-
0.4
V
-
V
RS-562/RS-232 RECEIVERS
Input Voltage Range
Input Threshold Low
Input Threshold High
VCC = 3.0V to 3.6V
Input Hysteresis
Input Resistance
Output Voltage Low
IOUT = 3.2mA
Full
Output Voltage High
IOUT = -1.0mA
Full
Output Leakage Current
EN = VCC
Full
-
±0.05
±10
µA
Full
-
-
0.8
V
Full
2.4
-
-
V
EN Input Logic Threshold Low
EN Input Logic Threshold High
VCC = 3.0V to 5.0V
VCC -0.6 VCC -0.1
POWER SUPPLY
Operating Supply Voltage
SHDN = VCC
Supply Current
3
Full
3.0
-
5.5
V
All Outputs Unloaded
Full
-
0.5
6.0
mA
All Outputs loaded, RL = 3kΩ
25
-
14
-
mA
ISL8563E
Electrical Specifications
Test Conditions: VCC = 3V to 5.5V, C1 - C4 = 0.1µF; Unless Otherwise Specified.
Typicals are at TA = 25°C (Continued)
PARAMETER
TEST CONDITIONS
Supply Current, Powerdown
SHDN = GND
TEMP
(°C)
MIN
TYP
MAX
UNITS
25
-
1
10
µA
Full
-
1
25
µA
SHDN Input Leakage Current
Full
-
±0.01
±1.0
µA
SHDN Input Logic Threshold Low
Full
-
-
0.8
V
SHDN Input Logic Threshold High VCC = 3.0V to 5.0V
Full
2.4
-
-
V
25
4
-
30
V/µs
AC CHARACTERISTICS
Transition Region Slew Rate
VCC = 3.3V, RL = 3kΩ to 7kΩ, Measured From 3V to -3V or
-3V to 3V, CL = 50pF to 2500pF
Transmitter Propagation Delay
Transmitter Input to
Transmitter Output,
CL = 1000pF, RL = 3kΩ
tPHL (Note 2)
Full
-
1
3.5
µs
tPLH (Note 2)
Full
-
1
3.5
µs
tPHL (Note 3)
Full
-
0.3
1.0
µs
Receiver Propagation Delay
Receiver Input to Receiver
Output, CL = 150pF
tPLH (Note 3)
Full
-
0.3
1.0
µs
Receiver Output Enable Time
Figure 1
tER
Full
-
125
500
ns
Receiver Output Disable Time
Figure 1
tDR
Full
-
160
500
ns
Transmitter Output Enable Time
Figure 2
tET
25
-
17
-
µs
Transmitter Output Disable Time
Figure 2
tDT
25
-
600
-
ns
Transmitter Skew
tPHL - tPLH (Note 2)
25
-
100
-
ns
Receiver Skew
tPHL - tPLH (Note 3)
25
-
100
-
ns
ESD PERFORMANCE
RS-562 Pins (TOUT, RIN)
All Other Pins
Human Body Model
25
-
±15
-
kV
IEC61000-4-2 Contact Discharge
25
-
±8
-
kV
IEC61000-4-2 Air Gap Discharge
25
-
±15
-
kV
Human Body Model
25
-
±3
-
kV
NOTES:
2. Transmitter is measured at the transmitter zero crossing points.
3. Receiver is measured at the receiver 50 percent crossing points.
Test Waveforms
VCC
VCC
EN INPUT
0V
0V
SHDN INPUT
tER
tET
RECEIVER 0.5VCC
OUTPUT C = 150pF to GND
L
RL = 1kΩ to 0.5VCC
VCC - 0.6V
+0.4V
VCC
TRANSMITTER
OUTPUT
SHDN INPUT
CL = 50pF
RL = 3kΩ
0V
tDR
tDT
VOH
VOL
-3.7V
VCC
0V
EN INPUT
RECEIVER
OUTPUT
+3.7V
0V
V+
VOH - 0.1V
0.5VCC
VOL + 0.1V
CL = 150pF to GND
RL = 1kΩ to 0.5VCC
FIGURE 1. RECEIVER OUTPUT ENABLE AND DISABLE TIMING
4
TRANSMITTER
OUTPUT
+3.7V
0V
V-
-3.7V
CL = 50pF
RL = 3kΩ
FIGURE 2. TRANSMITTER OUTPUT ENABLE AND DISABLE
TIMING
ISL8563E
Detailed Description
The ISL8563E operates from a single +3V to +5.5V supply,
guarantees a 250kbps minimum data rate, requires only four
small external 0.1µF capacitors, features low power
consumption, and meets all ElA/TIA-562 and EIA/TIA-232
specifications. The circuit is divided into three sections: The
charge pump, the transmitters, and the receivers.
(VCC = 0V). The receivers’ Schmitt trigger input stage uses
hysteresis (even in powerdown) to increase noise immunity
and decrease errors due to slow input signal transitions.
The ISL8563E inverting receivers disable only when EN is
driven high. Standard receivers driving powered down
peripherals must be disabled to prevent current flow through
the peripheral’s protection diodes (see Figures 4 and 5).
Charge-Pump
VCC
Intersil’s new ISL8563E utilizes regulated on-chip dual
charge pumps as voltage doublers, and voltage inverters to
generate ±5.5V transmitter supplies from a VCC supply as
low as 3.0V. This allows these devices to maintain RS-232
compliant output levels over the ±10% tolerance range of
3.3V powered systems. The efficient on-chip power supplies
require only four small, external 0.1µF capacitors for the
voltage doubler and inverter functions over the full VCC
range. The charge pumps operate discontinuously (i.e., they
turn off as soon as the V+ and V- supplies are pumped up to
the nominal values), resulting in significant power savings.
Transmitters
The transmitters are proprietary, low dropout, inverting
drivers that translate TTL/CMOS inputs to EIA/TIA-562/232
output levels. Coupled with the on-chip ±5.5V supplies,
these transmitters deliver true RS-562/232 levels over a
wide range of single supply system voltages.
All transmitter outputs disable and assume a high
impedance state when the device enters the powerdown
mode (see Table 2). These outputs may be driven to ±12V
when disabled.
All devices guarantee a 250kbps data rate (VOUT = ±5V) for
full load conditions (3kΩ and 1000pF), VCC ≥ 3.0V, with one
transmitter operating at full speed. Under more typical
conditions of VCC ≥ 3.3V, RL = 3kΩ, and CL = 250pF, one
transmitter easily operates at 900kbps.
Unused transmitter inputs may be left unconnected because
they will be pulled to VCC by the on-chip pull-up resistors.
Forcing the ISL8563E into power down disables the pull-up
resistors to further minimize power.
Receivers
The ISL8563E contains standard inverting receivers that
three-state via the EN control line. All the receivers convert
RS-562/232 signals to CMOS output levels and accept
inputs up to ±25V while presenting the required 3kΩ to 7kΩ
input impedance (see Figure 3) even if the power is off
RXOUT
RXIN
-25V ≤ VRIN ≤ +25V
5kΩ
GND ≤ VROUT ≤ VCC
GND
FIGURE 3. INVERTING RECEIVER CONNECTIONS
Powerdown Functionality
This 3V device requires a nominal supply current of 0.3mA
during normal operation (not in powerdown mode). This is
considerably less than the 5mA to 11mA current required by
5V devices. The already low current requirement drops
significantly when the device enters powerdown mode. In
powerdown, supply current drops to 1µA, because the onchip charge pump turns off (V+ collapses to VCC, Vcollapses to GND), the transmitter outputs three-state, and
the transmitter input pull-ups disable. This micro-power
mode makes the ISL8563E ideal for battery powered and
portable applications.
Software Controlled (Manual) Powerdown
The ISL8563E, is forced into its low power, stand by state via
a simple shutdown (SHDN) pin. Driving this pin high enables
normal operation, while driving it low forces the IC into its
powerdown state. Connect SHDN to VCC if the powerdown
function isn’t needed. Note that all the receiver outputs
remain enabled during shutdown (see Table 2). For the
lowest power consumption during powerdown, the receivers
should also be disabled by driving the EN input high (see
next section, and Figures 4 and 5). The time required to exit
powerdown, and resume transmission is less than 30µs.
Receiver ENABLE Control
The device also features an EN input to control the receiver
outputs. Driving EN high disables all the receiver outputs
placing them in a high impedance state. This is useful to
eliminate supply current, due to a receiver output forward
biasing the protection diode, when driving the input of a
powered down (VCC = GND) peripheral (see Figure 4). The
enable input has no effect on transmitters.
TABLE 2. POWERDOWN AND ENABLE LOGIC TRUTH TABLE
SHDN INPUT
EN INPUT
TRANSMITTER OUTPUTS
RECEIVER OUTPUTS
L
L
High-Z
Active
MODE OF OPERATION
Manual Powerdown
L
H
High-Z
High-Z
Manual Powerdown w/Rcvr. Disabled
H
L
Active
Active
Normal Operation
H
H
Active
High-Z
Normal Operation w/Rcvr. Disabled
5
ISL8563E
Power Supply Decoupling
VCC
In most circumstances a 0.1µF bypass capacitor is
adequate. In applications that are particularly sensitive to
power supply noise, decouple VCC to ground with a
capacitor of the same value as the charge-pump capacitor C1.
Connect the bypass capacitor as close as possible to the IC.
VCC
VCC
CURRENT
FLOW
VOUT = VCC
Rx
POWERED
DOWN
UART
Operation Down to 2.7V
Tx
GND
SHDN = GND
ISL8563E transmitter outputs meet RS-562 levels (±3.7V), at
the full data rate, with VCC as low as 2.7V. RS-562 levels
typically ensure interoperability with RS-232 devices.
OLD
RS-562/232 CHIP
FIGURE 4. POWER DRAIN THROUGH POWERED DOWN
PERIPHERAL
Figure 6 shows the response of two transmitter outputs
when exiting powerdown mode. As they activate, the two
transmitter outputs properly go to opposite RS-562/232
levels, with no glitching, ringing, nor undesirable transients.
Each transmitter is loaded with 3kΩ in parallel with 2500pF.
Note that the transmitters enable only when the magnitude
of the supplies exceed approximately 3V.
VCC
TRANSITION
DETECTOR
TO
WAKE-UP
LOGIC
ISL8563E
VCC
5V/DIV
RX
POWERED
DOWN
UART
Transmitter Outputs When Exiting
Powerdown
T1
VOUT = HI-Z
R2OUT
TX
SHDN
R2IN
T1IN
2V/DIV
T1OUT
SHDN = GND, EN = VCC
T2
FIGURE 5. DISABLED RECEIVERS PREVENT POWER DRAIN
VCC = +3.3V
C1 - C4 = 0.1µF
Capacitor Selection
TIME (20µs/DIV)
The charge pumps operate with 0.1µF (or greater)
capacitors for 3.0V ≤ VCC ≤ 5.5V. Increasing the capacitor
values (by a factor of 2) reduces ripple on the transmitter
outputs and slightly reduces power consumption. C2, C3, and
C4 can be increased without increasing C1’s value, however,
do not increase C1 without also increasing C2, C3, and C4 to
maintain the proper ratios (C1 to the other capacitors).
When using minimum required capacitor values, make sure
that capacitor values do not degrade excessively with
temperature. If in doubt, use capacitors with a larger nominal
value. The capacitor’s equivalent series resistance (ESR)
usually rises at low temperatures and it influences the
amount of ripple on V+ and V-.
6
FIGURE 6. TRANSMITTER OUTPUTS WHEN EXITING
POWERDOWN
High Data Rates
The ISL8563E maintains the RS-232 ±5V minimum
transmitter output voltages even at high data rates. Figure 7
details a transmitter loopback test circuit, and Figure 8
illustrates the loopback test result at 120kbps. For this test,
all transmitters were simultaneously driving RS-232 loads in
parallel with 1000pF, at 120kbps. Figure 9 shows the
loopback results for a single transmitter driving 1000pF and
an RS-232 load at 250kbps. The static transmitters were
also loaded with an RS-232 receiver.
ISL8563E
VCC
0.1µF
Interconnection with 3V and 5V Logic
+
+
C1
VCC
C1+
V+
C1+
C2
ISL8563E
C2+
C2-
VCC
C4
+
400kΩ
TIN
TOUT
RIN
ROUT
EN
VCC
V-
+
C3
1000pF
5K
SHDN
FIGURE 7. TRANSMITTER LOOPBACK TEST CIRCUIT
The ISL8563E directly interfaces with 5V CMOS and TTL
logic families. Nevertheless, with the device at 3.3V, and the
logic supply at 5V, AC, HC, and CD4000 outputs can drive
ISL83563E inputs, but ISL83563E outputs do not reach the
minimum VIH for these logic families. See Table 3 for more
information.
TABLE 3. LOGIC FAMILY COMPATIBILITY WITH VARIOUS
SUPPLY VOLTAGES
VCC
SYSTEM
POWER-SUPPLY SUPPLY
VOLTAGE
VOLTAGE
(V)
(V)
3.3
3.3
5
5
5
3.3
5V/DIV.
T1IN
COMPATIBILITY
Compatible with all CMOS families.
Compatible with all TTL and
CMOS logic families.
Compatible with ACT and HCT
CMOS, and with TTL. ISL83563E
outputs are incompatible with AC,
HC, and CD4000 CMOS inputs.
±15kV ESD Protection
T1OUT
R1OUT
VCC = +3.3V
C1 - C4 = 0.1µF
5µs/DIV.
FIGURE 8. LOOPBACK TEST AT 120kbps
All pins on Intersil 3V interface devices include ESD
protection structures, but the ISL8XXXE family incorporates
advanced structures which allow the RS-562/232 pins
(transmitter outputs and receiver inputs) to survive ESD
events up to ±15kV. These pins are particularly vulnerable to
ESD damage because they typically connect to an exposed
port on the exterior of the finished product. Simply touching
the port pins, or connecting a cable, can cause an ESD event
that might destroy unprotected ICs. These new ESD
structures protect the device whether or not it is powered up,
protect without allowing any latchup mechanism to activate,
and don’t interfere with RS-562/232 signals as large as ±25V.
Human Body Model (HBM) Testing
As the name implies, this test method emulates the ESD
event delivered to an IC during human handling. The tester
delivers the charge through a 1.5kΩ current limiting resistor,
making the test less severe than the IEC61000 test which
utilizes a 330Ω limiting resistor. The HBM method
determines an ICs ability to withstand the ESD transients
typically present during handling and manufacturing. Due to
the random nature of these events, each pin is tested with
respect to all other pins. The RS-562/232 pins on “E” family
devices can withstand HBM ESD events to ±15kV.
5V/DIV
T1IN
T1OUT
IEC61000-4-2 Testing
R1OUT
VCC = +3.3V
C1 - C4 = 0.1µF
2µs/DIV
FIGURE 9. LOOPBACK TEST AT 250kbps
7
The IEC61000 test method applies to finished equipment,
rather than to an individual IC. Therefore, the pins most likely
to suffer an ESD event are those that are exposed to the
outside world (the RS-562/232 pins in this case), and the IC
is tested in its typical application configuration (power
applied) rather than testing each pin-to-pin combination. The
lower current limiting resistor coupled with the larger charge
ISL8563E
storage capacitor yields a test that is much more severe than
the HBM test. The extra ESD protection built into this
device’s RS-562/232 pins allows the design of equipment
meeting level 4 criteria without the need for additional board
level protection on the RS-562/232 port.
AIR-GAP DISCHARGE TEST METHOD
For this test method, a charged probe tip moves toward the
IC pin until the voltage arcs to it. The current waveform
delivered to the IC pin depends on approach speed,
humidity, temperature, etc., so it is difficult to obtain
Typical Performance Curves
repeatable results. The “E” device RS-562/232 pins
withstand ±15kV air-gap discharges.
CONTACT DISCHARGE TEST METHOD
During the contact discharge test, the probe contacts the
tested pin before the probe tip is energized, thereby
eliminating the variables associated with the air-gap
discharge. The result is a more repeatable and predictable
test, but equipment limits prevent testing devices at voltages
higher than ±8kV. All “E” family devices survive ±8kV contact
discharges on the RS-562/232 pins.
VCC = 3.3V, TA = 25°C
25
VOUT+
4
20
2
SLEW RATE (V/µs)
TRANSMITTER OUTPUT VOLTAGE (V)
6
1 TRANSMITTER AT 250kbps
1 TRANSMITTER AT 30kbps
0
-2
15
-SLEW
+SLEW
10
VOUT -
-4
-6
0
1000
2000
3000
4000
5
5000
0
1000
LOAD CAPACITANCE (pF)
3.5
40
SUPPLY CURRENT (mA)
30
25
120kbps
20
15
5000
NO LOAD
ALL OUTPUTS STATIC
3.0
250kbps
35
4000
FIGURE 11. SLEW RATE vs LOAD CAPACITANCE
45
SUPPLY CURRENT (mA)
3000
LOAD CAPACITANCE (pF)
FIGURE 10. TRANSMITTER OUTPUT VOLTAGE vs LOAD
CAPACITANCE
20kbps
10
2.5
2.0
1.5
1.0
0.5
5
0
2000
0
1000
2000
3000
4000
5000
0
2.5
3.0
LOAD CAPACITANCE (pF)
FIGURE 12. SUPPLY CURRENT vs LOAD CAPACITANCE
WHEN TRANSMITTING DATA
GND
338
8
4.5
5.0
5.5
FIGURE 13. SUPPLY CURRENT vs SUPPLY VOLTAGE
PROCESS:
Si Gate CMOS
TRANSISTOR COUNT:
4.0
SUPPLY VOLTAGE (V)
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
3.5
6.0
ISL8563E
Small Outline Plastic Packages (SOIC)
N
INDEX
AREA
0.25(0.010) M
H
M18.3 (JEDEC MS-013-AB ISSUE C)
B M
18 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
E
INCHES
-B-
1
2
3
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
e
µα
A1
B
0.10(0.004)
0.25(0.010) M
C A M
MIN
MAX
MIN
MAX
NOTES
A
0.0926
0.1043
2.35
2.65
-
A1
0.0040
0.0118
0.10
0.30
-
B
0.013
0.0200
0.33
0.51
9
C
0.0091
0.0125
0.23
0.32
-
D
0.4469
0.4625
11.35
11.75
3
E
0.2914
0.2992
7.40
7.60
4
e
C
B S
0.050 BSC
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
1.27 BSC
-
H
0.394
0.419
10.00
10.65
-
h
0.010
0.029
0.25
0.75
5
L
0.016
0.050
0.40
1.27
6
8o
0o
N
NOTES:
MILLIMETERS
SYMBOL
α
18
0o
18
7
8o
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
9
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