DATASHEET

QFN Packaged, ±15kV ESD Protected, +2.7V to +3.6V,
250kbps, RS-232 Transmitters/Receivers with
Separate Logic Supply Pin
ISL3241E, ISL3243E
Features
The Intersil ISL324xE devices are 2.7V to 3.6V powered
RS-232 transmitters/receivers which meet ElA/TIA-232 and
V.28/V.24 specifications, even at VCC = 3.0V. Additionally, they
provide ±15kV ESD protection (IEC61000-4-2 Air Gap and
Human Body Model) on transmitter outputs and receiver
inputs (RS-232 pins). Targeted applications are POS systems,
and notebook and laptop computers where the low
operational, and even lower standby, power consumption is
critical. Efficient on-chip charge pumps, coupled with manual
and automatic power-down functions, reduce the standby
supply current to a 0.5µA trickle. Tiny 5mmx5mm Quad Flat
No-Lead (QFN) packaging and the use of small, low value
capacitors ensure board space savings as well. Data rates
greater than 250kbps are guaranteed at worst case load
conditions.
• VL Pin for Compatibility in Mixed Voltage Systems Adjusts
Logic Output Levels and Input Thresholds for Compatibility
with Lower Supply Voltage Logic
ISL324xE are 3 driver, 5 receiver devices that, coupled with the
5x5 QFN package, provide the industry’s smallest, lowest
power complete serial port. The 5x5 QFN requires 60% less
board area than a 28 Ld TSSOP, and is nearly 20% thinner.
These devices also include a noninverting always-active
receiver for “wake-up” capability.
The ISL3243E features an automatic powerdown function that
powers down the on-chip power supply and driver circuits. This
occurs when an attached peripheral device is shut off or the
RS-232 cable is removed, conserving system power
automatically without changes to the hardware or operating
system. It powers up again when a valid RS-232 voltage is
applied to any receiver input.
The ISL324xE feature a VL pin that adjusts the logic pin (see
“Pin Descriptions” on page 2) output levels and input
thresholds to values compatible with the VCC powering the
external logic (e.g., a UART).
Table 1 summarizes the features of the ISL324xE.
• Parameters Specified for 10% Tolerance Supplies and Full
Industrial Temp Range
• Pb-free Small QFN (5mmx5mm) Package is 60% Smaller
than a 28 Lead TSSOP
• ESD Protection for RS-232 I/O Pins to ±15kV (IEC61000)
• Meets EIA/TIA-232 and V.28/V.24 Specifications at 3V
• RS-232 Compatible with VCC = 2.7V
• On-Chip Voltage Converters Require Only Four External
0.1µF Capacitors
• Manual and Automatic Power-down Features
• Receiver Hysteresis for Improved Noise Immunity
• Guaranteed Minimum Data Rate. . . . . . . . . . . . . . . . 250kbps
• Low Supply Current in Power-down State . . . . . . . . . . . 0.5µA
• Pb-Free (RoHS compliant)
Applications
• Any Space Constrained System Requiring RS-232 Ports
- Battery Powered, Hand-Held, and Portable Equipment
- POS Systems and Scanners
- Laptop Computers, Notebooks
- GPS Receivers
• Mixed Voltage Serial Ports
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
• Technical Brief TB379 “Thermal Characterization of
Packages for ICs”
• Technical Brief TB389 “PCB Land Pattern Design and
Surface Mount Guidelines for QFN Packages”
TABLE 1. SUMMARY OF FEATURES
PART NUMBER
NO. OF
Tx.
NO. OF
Rx.
LOGIC SUPPLY
(VL) PIN?
NO. OF
MONITOR Rx.
(ROUTB)
DATA RATE
(kbps)
Rx. ENABLE
FUNCTION?
ISL3241E
3
5
YES
2
250
YES
ISL3243E
3
5
YES
1
250
NO
June 18, 2012
FN6768.2
1
Pb-FREE?
MANUAL
POWERDOWN?
AUTOMATIC
POWERDOWN
FUNCTION?
YES
YES
NO
YES
YES
YES
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2008, 2010, 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL3241E, ISL3243E
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL3241EIRZ
ISL3241 EIRZ
-40 to +85
32 Ld 5X5 QFN
L32.5x5B
ISL3243EIRZ
ISL3243 EIRZ
-40 to +85
32 Ld 5X5 QFN
L32.5x5B
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pbfree products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL3241E, ISL3243E. For more information on MSL please see tech brief
TB363.
Pin Configurations
32
31
30
1
27
26
25
GND
R1IN
1
24
GND
R2IN
2
23
C1-
22
FORCEON
21
FORCEOFF
20
INVALID
R2IN
2
23
R3IN
3
22
EN
R3IN
3
R4IN
4
21
SHDN
R4IN
4
PD
R2OUTB
T1OUT
6
19
R2OUTB
7
18
R1OUT
T2OUT
7
18
R1OUT
17
R2OUT
T3OUT
8
17
R2OUT
T2OUT
9
10
11
12
13
14
15
16
9
NC
T3IN
T2IN
T1IN
R5OUT
R4OUT
R3OUT
NC
NC
8
10
11
12
13
14
15
16
NC
19
R3OUT
6
T1OUT
R4OUT
5
R5OUT
R5IN
T1IN
R1OUTB
5
T2IN
20
R5IN
T3OUT
28
24
C1-
PD
29
VL
C2-
25
VCC
V-
26
V+
NC
27
C1+
VL
28
VCC
29
V+
C230
C1+
V31
C2+
NC
32
T3IN
R1IN
C2+
ISL3243E
(32 LEAD QFN)
TOP VIEW
ISL3241E
(32 LEAD QFN)
TOP VIEW
Pin Descriptions
PIN NUMBER
ISL3241E
PIN NUMBER
ISL3243E
PIN NAME
26
26
VCC
System power supply input (2.7V to 3.6V).
25
25
VL
Logic power supply. Sets the VOH of all the logic outputs and the switching point of all logic
inputs. Keep VL greater than 1.6V (1.8V - 10%) and less than or equal to VCC. If VL isn't
connected to the Vcc supply, ensure that the VL supply powers up after the Vcc supply.
27
27
V+
Internally generated positive transmitter supply (typically +5.5V).
31
31
V-
Internally generated negative transmitter supply (typically -5.5V).
24
24
GND
Ground connection. This is also the potential of the thermal pad (PD).
28
28
C1+
External capacitor (voltage doubler) is connected to this lead.
23
23
C1-
External capacitor (voltage doubler) is connected to this lead.
29
29
C2+
External capacitor (voltage inverter) is connected to this lead.
2
FUNCTION
FN6768.2
June 18, 2012
ISL3241E, ISL3243E
Pin Descriptions (Continued)
PIN NUMBER
ISL3241E
PIN NUMBER
ISL3243E
PIN NAME
30
30
C2-
12, 11, 10
12, 11, 10
T1IN, T2IN, T3IN
6, 7, 8
6, 7, 8
T1OUT, T2OUT,
T3OUT
1, 2, 3, 4, 5
1, 2, 3, 4, 5
18, 17
18, 17
20,19
19
External capacitor (voltage inverter) is connected to this lead.
TTL/CMOS compatible transmitter Inputs. The VL voltage sets the input switching point.
±15kV ESD Protected, RS-232 level (nominally ±5.5V) transmitter outputs.
R1IN, R2IN, R3IN, ±15kV ESD Protected, RS-232 compatible receiver inputs.
R4IN, R5IN
R1OUT, R2OUT
TTL/CMOS level receiver outputs. Swings between GND and VL.
R1OUTB, R2OUTB TTL/CMOS level, noninverting, always enabled receiver outputs. Swings between GND and VL.
20
INVALID
21
FORCEOFF
Active low to shut down transmitters and on-chip power supply. This overrides any automatic
circuitry and FORCEON (see Table 2). The VL voltage sets the input switching point.
22
FORCEON
Active high input to override automatic powerdown circuitry thereby keeping transmitters
active. (FORCEOFF must be high). The VL voltage sets the input switching point.
22
EN
21
SHDN
9, 16, 32
FUNCTION
9, 16, 32
3
Active low output that indicates if no valid RS-232 levels are present on any receiver input.
Swings between GND and VL.
Active low receiver enable control. The VL voltage sets the input switching point.
Active low input to shut down transmitters and on-board power supply, to place device in low
power mode. The VL voltage sets the input switching point.
NC
No Connection
PAD
Exposed Thermal Pad. Connect to GND.
FN6768.2
June 18, 2012
ISL3241E, ISL3243E
Typical Operating Circuits
ISL3241E
+3.3V
+
C1
0.1µF
C2
0.1µF
T1IN
T2IN
ISL3243E
0.1µF
0.1µF
26
28
C1+
+
23
C129
C2+
+
30
C212
VCC
R2OUTB
TTL/CMOS
LOGIC
LEVELS
R1OUT
VL V+
VT1
11
T2
10
T3
27
31
+ C3
0.1µF
C1
0.1µF
C2
0.1µF
C4
0.1µF
+
T1OUT
0.1µF
7
8
T2OUT
28
+
C1+
26
VCC
25
VL
23
C129
C2+
+
30
C2-
27
V+
V-
12
T1
RS-232
LEVELS
11
T2
T2IN
31
C3
0.1µF
C4
0.1µF
+
T1OUT
7
T2OUT
RS-232
LEVELS
8
T3IN
19
+
6
T3
10
+1.8V
+
T1IN
T3OUT
T3OUT
19
R2OUTB
18
1
17
R1IN
R1
TTL/CMOS
LOGIC
LEVELS
R2IN
5kΩ
R2OUT
14
4
R4OUT
R4
13
RS-232
LEVELS
15
R3IN
EN
5kΩ
R5
R5IN
R5OUT
GND
24
VCC
TO POWER
CONTROL
LOGIC
21
20
RS-232
LEVELS
R4IN
5kΩ
13
22
4
4
R4
21
SHDN
5kΩ
14
5
R5OUT
3
R3OUT
R4OUT
R2IN
5kΩ
R3
R4IN
5kΩ
2
R2
R3IN
5kΩ
R3
5kΩ
17
3
R3OUT
1
R1OUT
2
15
22
18
R1IN
5kΩ
R2
VCC
0.1µF
+
6
20
R1
R2OUT
+3.3V
25
T3IN
R1OUTB
+1.8V
+
5
5kΩ
R5
R5IN
FORCEON
FORCEOFF
INVALID
GND
24
FN6768.2
June 18, 2012
ISL3241E, ISL3243E
Absolute Maximum Ratings
Thermal Information
VCC to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V
VL to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VCC + 0.3V)
V+ to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V
V- to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3V to -7V
V+ to V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14V
Input Voltages
TIN, FORCEOFF, FORCEON, EN, SHDN . . . . . . . . . . . . . . . . . . . -0.3V to 6V
RIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25V
Output Voltages
TOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±13.2V
ROUT, INVALID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VL + 0.3V)
Short Circuit Duration
TOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous
ESD Rating . . . . . . . . . . . . . . . . . . . . See “ESD PERFORMANCE” on page 7
Thermal Resistance (Typical, Notes 4, 5)
θJA (°C/W) θJC (°C/W)
32 Ld QFN Package . . . . . . . . . . . . . . . . . . .
32
1.8
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . -65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379 for details.
5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Test Conditions: VCC = 3V to 3.6V, VL = 1.8V ±10%, C1 to C4 = 0.1µF, Unless Otherwise Specified.
Typicals are at TA = +25°C, VCC = 3.3V, VL = 1.8V, Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40°C
to +85°C.
PARAMETER
TEST CONDITIONS
TEMP
(°C)
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
Full
2.7
-
3.6
V
DC CHARACTERISTICS
Operating Voltage Range
Supply Current, Automatic
Powerdown
All RIN Open, FORCEON = GND, FORCEOFF = VL
VL = VCC (ISL3243E Only)
Full
-
0.5
3
µA
Supply Current, Powerdown
All RIN Open, FORCEOFF = SHDN = GND, VL = VCC
Full
-
0.5
3
µA
Supply Current,
Automatic Powerdown Disabled
All Outputs Unloaded,
FORCEON = FORCEOFF = SHDN = VL, VCC = VL = 3.0V
25
-
0.3
1.0
mA
Full
-
0.3
1.5
mA
Full
-
-
0.5
V
VL = VCC = 3V
Full
-
-
0.8
V
Full
1.25
-
-
V
VL = VCC = 3.6V
Full
2.0
-
-
V
LOGIC AND TRANSMITTER INPUTS; RECEIVER AND LOGIC OUTPUTS
Input Logic Threshold Low
Input Logic Threshold High
TIN, FORCEON, FORCEOFF, EN, SHDN
TIN, FORCEON, FORCEOFF, EN, SHDN
Input Leakage Current
TIN, FORCEON, FORCEOFF, EN, SHDN
Full
-
±0.01
±1.0
µA
Output Leakage Current
FORCEOFF = GND (ISL3243E) or EN = VL (ISL3241E)
Full
-
±0.05
±10
µA
Output Voltage Low
(See Figure 21)
IOUT = 250µA, ROUT, ROUTB, INVALID
Full
-
-
0.45
V
IOUT = 1.6mA, VL = VCC, ROUT, ROUTB, INVALID
Full
-
-
0.4
V
Output Voltage High
(See Figure 21)
IOUT = -250µA, ROUT, ROUTB, INVALID
Full
VL - 0.25
VL - 0.1
-
V
IOUT = -1.0mA, VL = VCC, ROUT, ROUTB, INVALID
Full
VL - 0.6
VL - 0.1
-
V
AUTOMATIC POWERDOWN (ISL3243E Only, FORCEON = GND, FORCEOFF = VL)
Receiver Input Thresholds to
Enable Transmitters
ISL3243E Powers Up (See Figure 10)
Full
-2.7
-
2.7
V
Receiver Input Thresholds to
Disable Transmitters
ISL3243E Powers Down (See Figure 10)
Full
-0.3
-
0.3
V
5
FN6768.2
June 18, 2012
ISL3241E, ISL3243E
Electrical Specifications
Test Conditions: VCC = 3V to 3.6V, VL = 1.8V ±10%, C1 to C4 = 0.1µF, Unless Otherwise Specified.
Typicals are at TA = +25°C, VCC = 3.3V, VL = 1.8V, Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40°C
to +85°C. (Continued)
TEMP
(°C)
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
Receiver Threshold to
Transmitters Enabled Delay (tWU)
25
-
20
-
µs
Receiver Positive or Negative
Threshold to INVALID High Delay
(tINVH)
25
-
0.7
-
µs
Receiver Positive or Negative
Threshold to INVALID Low Delay
(tINVL)
25
-
20
-
µs
PARAMETER
TEST CONDITIONS
RECEIVER INPUTS
Input Voltage Range
Input Threshold Low
Full
-25
-
25
V
VCC ≥ 2.7V
Full
-
-
0.6
V
VCC ≥ 3V
Full
-
-
0.8
V
Full
2.0
1.5
-
V
Input Threshold High
Input Hysteresis
25
-
0.5
-
V
Input Resistance
Full
3
5
7
kΩ
Full
±5.0
±5.4
-
V
TRANSMITTER OUTPUTS
Output Voltage Swing (VO)
All Transmitter Outputs Loaded with 3kΩ to
Ground
Output Resistance
VCC = VL = V+ = V- = 0V, Transmitter Output = ±2V
VCC = 2.7V
Full
±4.0
±4.7
-
V
Full
300
10M
-
Ω
Full
-
±35
±60
mA
VOUT = ±12V, VCC = VL = 0V or 3V to 3.6V,
Automatic Powerdown or FORCEOFF = SHDN = GND
Full
-
-
±25
µA
RL = 3kΩ, CL = 1000pF, One Transmitter Switching
Full
250
400
-
kbps
RL = 3kΩ CL = 200pF, VCC = 3.15V, One Transmitter Switching
Full
-
1.3
-
Mbps
Receiver Input to Receiver Output,
CL = 30pF, RIN = ±3V (See Figure 2)
25
-
0.23
0.55
µs
Full
-
0.26
0.6
µs
25
-
0.16
0.55
µs
Full
-
0.18
0.6
µs
Output Short-Circuit Current
Output Leakage Current
TIMING CHARACTERISTICS
Maximum Data Rate
Receiver Propagation Delay
tPHL
tPLH
Receiver Skew
Transmitter Propagation Delay
|tPHL - tPLH|
Transmitter Input to Transmitter Output,
CL = 1000pF, RL = 3kΩ (See Figure 1)
(Note 7)
tPHL
tPLH
Transmitter Skew
Receiver Output Enable Time
Receiver Output Disable Time
Transmitter Output Enable Time
From Powerdown
|tPHL - tPLH|
From EN or FORCEOFF, VL = VCC, RL = 1kΩ, CL = 15pF
(See Figure 3)
From SHDN or FORCEOFF, RL = 3kΩ, CL = 1000pF
6
25
-
70
300
ns
Full
-
80
350
ns
25
-
0.7
1.5
µs
Full
-
0.8
1.7
µs
25
-
0.7
1.5
µs
Full
-
0.8
1.7
µs
25
-
20
500
ns
Full
-
20
550
ns
25
-
120
-
ns
25
-
200
-
ns
25
-
20
-
µs
FN6768.2
June 18, 2012
ISL3241E, ISL3243E
Electrical Specifications
Test Conditions: VCC = 3V to 3.6V, VL = 1.8V ±10%, C1 to C4 = 0.1µF, Unless Otherwise Specified.
Typicals are at TA = +25°C, VCC = 3.3V, VL = 1.8V, Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40°C
to +85°C. (Continued)
PARAMETER
TEST CONDITIONS
Transition Region Slew Rate
VCC = 3V to 3.6V, RL = 3kΩto 7kΩ,
Measured From 3V to -3V or -3V to 3V
CL = 150pF to
2500pF
CL = 150pF to
1000pF
TEMP
(°C)
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
25
4
12
30
V/µs
Full
4
11
30
V/µs
25
6
18
30
V/µs
Full
6
17
30
V/µs
25
-
±15
-
kV
ESD PERFORMANCE
RS-232 Pins (TOUT, RIN)
Human Body Model
All Pins
IEC61000-4-2 Contact Discharge
25
-
±8
-
kV
IEC61000-4-2 Air Gap Discharge
25
-
±15
-
kV
Human Body Model
25
-
±2
-
kV
Machine Model
25
-
±200
-
V
NOTES:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
7. Transmitter propagation delays are measured at the transmitter output 0V crossing points.
Test Circuits and Waveforms
VL
SHDN
OR
FORCEOFF
VL
TIN
TIN
1.5V
1.5V
0V
TOUT
D
tPHL
RL
SIGNAL
GENERATOR
CL
tPLH
+VO
TOUT
0V
0V
-VO
SKEW = |tPHL - tPLH|
FIGURE 1A. TEST CIRCUIT
FIGURE 1B. MEASUREMENT POINTS
FIGURE 1. DRIVER PROPAGATION DELAY AND SKEW
+3V
EN = GND
OR
FORCEOFF = VL
RIN
RIN
1.5V
-3V
ROUT
R
1.5V
tPLH
tPHL
VOH
CL
SIGNAL
GENERATOR
50%
ROUT
50%
VOL
SKEW = |tPHL - tPLH|
FIGURE 2A. TEST CIRCUIT
FIGURE 2B. MEASUREMENT POINTS
FIGURE 2. RECEIVER PROPAGATION DELAY AND SKEW
7
FN6768.2
June 18, 2012
ISL3241E, ISL3243E
Test Circuits and Waveforms (Continued)
EN
OR
FORCEOFF
SIGNAL
GENERATOR
VCC
OR
GND
VL
FORCEOFF
50%
50%
0V
RIN
1kΩ
ROUT
R
FORCEON
OR SHDN
VL
VL
SW
GND
VL
EN
CL
50%
50%
0V
tPHZ
tPZH
OUTPUT HIGH
VOH - 0.3V
50%
ROUT
VOH
0V
PARAMETER
RIN
SW
tPHZ and tPZH
GND
GND
tPLZ and tPZL
VCC
VL
tPZL
tPLZ
VL
ROUT
50%
OUTPUT LOW
VOL + 0.3V V
OL
FIGURE 3B. MEASUREMENT POINTS
FIGURE 3A. TEST CIRCUIT
FIGURE 3. RECEIVER ENABLE AND DISABLE TIMES
Detailed Description
The ISL324xE operate from a single +2.7V to +3.6V supply,
guarantee a 250kbps minimum data rate, require only four
small external 0.1µF capacitors, feature low power
consumption, and meet all ElA RS-232 and V.28 specifications
even with VCC = 3.0V. The circuit is divided into three sections:
The charge pump, the transmitters, and the receivers.
The transmitter input switching threshold is set by the voltage
applied to the VL pin, so tying VL to a voltage lower than VCC
reduces the Tx input VIH and VIL to values compatible with
logic ICs (e.g., UARTs and µcontrollers) powered by the VL
voltage (see Figure 9 and Table 3). Transmitter inputs float if
left unconnected (there are no pull-up resistors), and may
cause supply current increases. Connect unused inputs to GND
for the best performance.
Charge-Pump
Receivers
Intersil’s new ISL324xE devices utilize regulated on-chip dual
charge pumps as voltage doublers, and voltage inverters to
generate ±5.5V transmitter supplies from a VCC supply as low
as 3.0V. This allows them to maintain RS-232 compliant output
levels over the ±10% tolerance range of 3.3V powered
systems. The efficient on-chip power supplies require only four
small, external 0.1µF capacitors for the voltage doubler and
inverter functions. The charge pumps operate discontinuously
(i.e., they turn off as soon as the V+ and V- supplies are
pumped up to the nominal values), resulting in significant
power savings.
All the ISL324xE devices contain standard inverting receivers
that three-state via the EN or FORCEOFF control lines.
Additionally, these products include noninverting “monitor”
receivers (denoted by the ROUTB label) that are always active,
regardless of the state of any control lines. All the receivers
convert RS-232 signals to CMOS output levels, swinging
between GND and VL, and accept inputs up to ±25V while
presenting the required 3kΩ to 7kΩ input impedance (see
Figure 4) even if the power is off (VCC = 0V). The receivers’
Schmitt trigger input stage uses hysteresis to increase noise
immunity and decrease errors due to slow input signal
transitions.
Transmitters
The transmitters are proprietary, low dropout, inverting drivers
that translate logic input levels to EIA/TIA-232 output levels.
Coupled with the on-chip ±5.5V supplies, these transmitters
deliver true RS-232 levels over a wide range of single supply
system voltages.
All transmitter outputs disable and assume a high impedance
state when the device enters the power-down mode (see Table
2). These outputs may be driven to F12V when disabled.
The devices guarantee a 250kbps data rate for full load
conditions (3kΩ and 1000pF), VCC ≥ 3.0V, with one transmitter
operating at full speed. Under more typical conditions of VCC ≥
3.3V, RL = 3kΩ and CL = 200pF, one transmitter easily
operates at greater than 1Mbps.
8
VL
RXIN
-25V ≤ VRIN ≤ +25V
RXOUT
5kΩ
GND ≤ VROUT ≤ VL
GND
FIGURE 4. INVERTING RECEIVER CONNECTIONS
The ISL3241E inverting receivers disable only when EN is
driven high. ISL3243E receivers disable during forced (manual)
powerdown, but not during automatic powerdown (see
Table 2).
FN6768.2
June 18, 2012
ISL3241E, ISL3243E
TABLE 2. POWER-DOWN AND ENABLE LOGIC TRUTH TABLE (NOTE: “H” = VL)
RS-232
SIGNAL
PRESENT
AT
RECEIVER
INPUT?
SHDN OR
FORCEOFF
INPUT
FORCEON
INPUT
EN
INPUT
TRANSMITTER
OUTPUTS
RECEIVER
OUTPUTS
ROUTB
OUTPUTS
INVALID
OUTPUT
N/A
L
N/A
L
High-Z
Active
Active
N/A
Manual Power-down
N/A
L
N/A
H
High-Z
High-Z
Active
N/A
Manual Power-down w/Rcvr. Disabled
N/A
H
N/A
L
Active
Active
Active
N/A
Normal Operation
N/A
H
N/A
H
Active
High-Z
Active
N/A
Normal Operation w/Rcvr. Disabled
NO
H
H
N.A.
Active
Active
Active
L
Normal Operation
(Auto Powerdown Disabled)
YES
H
L
N.A.
Active
Active
Active
H
Normal Operation
(Auto Power-down Enabled)
NO
H
L
N.A.
High-Z
Active
Active
L
Power-down Due to Auto Power-down
Logic
YES
L
X
N.A.
High-Z
High-Z
Active
H
Manual Power-down
NO
L
X
N.A.
High-Z
High-Z
Active
L
Manual Power-down
MODE OF OPERATION
ISL3241E
ISL3243E
ISL324xE monitor receivers remain active even during manual
powerdown, making them extremely useful for Ring Indicator
monitoring. Standard receivers driving powered down
peripherals must be disabled to prevent current flow through
the peripheral’s protection diodes (see Figures 5 and 6). This
renders them useless for wake up functions, but the
corresponding monitor receiver can be dedicated to this task
as shown in Figure 6.
Low Power Operation
These 3V devices require a nominal supply current of 0.3mA,
even at VCC = 3.6V, during normal operation (not in powerdown mode). This is considerably less than the 5mA to 11mA
current required by comparable 5V RS-232 devices, allowing
users to reduce system power simply by switching to this new
family.
Power-down Functionality
VCC
VCC
VCC
CURRENT
FLOW
VOUT = VCC
Rx
POWERED
DOWN
UART
Tx
GND
SHDN = GND
OLD
RS-232 CHIP
FIGURE 5. POWER DRAIN THROUGH POWERED DOWN
PERIPHERAL
The already low current requirement drops significantly when
the device enters powerdown mode. In powerdown, supply
current drops to less than 1µA, because the on-chip charge
pump turns off (V+ collapses to VCC, V- collapses to GND), and
the transmitter outputs three-state. Inverting receiver outputs
disable only in manual powerdown (ISL3243E) or when EN =
VL (ISL3241E); refer to Table 2 for details. This micro-power
mode makes the ISL324xE ideal for battery powered and
portable applications.
9
FN6768.2
June 18, 2012
ISL3241E, ISL3243E
VCCL
FORCEOFF
PWR
MGT
LOGIC
VCCI
TRANSITION
DETECTOR
VL
TO
WAKE-UP
LOGIC
VCC
FORCEON
VCCI
VCCL
INVALID
VCC
VL
VCC
ISL324XE
VCC
ISL3243E
R2OUTB
RX
POWERED
DOWN
UART
VOUT = HI-Z
R2OUT
TX
I/O
UART
R2IN
CPU
T1IN
FORCEOFF = GND
OR
SHDN = GND, EN = VL
T1OUT
FIGURE 6. DISABLED RECEIVERS PREVENT POWER DRAIN
Software Controlled (Manual) Powerdown
The devices in this family provide pins that allow the user to
force the IC into the low power, standby state.
On the ISL3241E, the powerdown control is via a simple
shutdown (SHDN) pin. Driving this pin high enables normal
operation, while driving it low forces the IC into it’s powerdown
state. Connect SHDN to VL if the powerdown function isn’t
needed. Note that all the receiver outputs remain controlled by
EN during shutdown (see Table 2). For the lowest power
consumption during powerdown, the receivers should also be
disabled by driving the EN input high (see next section, and
Figures 5 and 6).
The ISL3243E utilizes a two pin approach where the FORCEON
and FORCEOFF inputs determine the IC’s mode. For always
enabled operation, FORCEON and FORCEOFF are both
strapped high. To switch between active and powerdown
modes, under logic or software control, only the FORCEOFF
input need be driven. The FORCEON state isn’t critical, as
FORCEOFF dominates over FORCEON. Nevertheless, if strictly
manual control over powerdown is desired, the user must strap
FORCEON high to disable the automatic powerdown circuitry.
ISL3243E inverting (standard) receiver outputs also disable
when the device is in manual powerdown, thereby eliminating
the possible current path through a shutdown peripheral’s
input protection diode (see Figures 5 and 6).
Connecting FORCEOFF and FORCEON together disables the
automatic powerdown feature, enabling them to function as a
manual SHUTDOWN input (see Figure 7).
10
FIGURE 7. CONNECTIONS FOR MANUAL POWERDOWN WHEN NO
VALID RECEIVER SIGNALS ARE PRESENT
With any of the previous mentioned control schemes, the time
required to exit powerdown, and resume transmission is only
20µs. A mouse, or other application, may need more time to
wake up from shutdown. If automatic power-down is being
utilized, the RS-232 device will reenter power-down if valid
receiver levels aren’t reestablished within 20µs of the
ISL3243E powering up. Figure 8 illustrates a circuit that keeps
the ISL3243E from initiating automatic power-down for 100ms
after powering up. This gives the slow-to-wake peripheral
circuit time to reestablish valid RS-232 output levels.
POWER
MANAGEMENT
UNIT
MASTER POWERDOWN LINE
0.1µF
FORCEOFF
1MΩ
FORCEON
ISL3243E
FIGURE 8. CIRCUIT TO PREVENT AUTO POWERDOWN FOR
100ms AFTER FORCED POWERUP
VL Logic Supply Input
Note: If VL isn't connected to the Vcc supply, power-up Vcc
before powering up the VL supply.
The ISL324xE feature a VL pin that powers the logic input and
output pins. These pins interface with “logic” devices such as
UARTs, ASICs, and µcontrollers, and today most of these
devices use power supplies significantly lower than 3.3V. Thus,
the logic device’s low VOH might not exceed the VIH of a 3.3V
powered ISL324xE logic input, or a 3.3V receiver output high
level might overdrive and damage the input diodes on an input
of a 1.8V powered logic device, as shown in Figure 9.
Connecting the VL pin to the power supply of the logic device
(see Figure 9) reduces the ISL324xE’s logic input switching
points, and limits the receiver output high voltage, to values
compatible with the logic device’s I/O levels. Tailoring the
ISL324XE’s logic pin input switching points and output levels
FN6768.2
June 18, 2012
ISL3241E, ISL3243E
to the supply voltage of the UART, ASIC, or µcontroller
eliminates the need for a level shifter/translator between the
two ICs.
TABLE 3. VIH AND VIL vs VL FOR VCC = 3.3V
VL (V)
VIH (V)
VIL (V)
1.6
0.85
0.8
1.8
0.95
0.9
2.5
1.25
1.2
the receiver inputs, INVALID switches high, and the power
management logic wakes up the interface block. INVALID can
also be used to indicate the DTR or RING INDICATOR signal, as
long as the other receiver inputs are floating, or driven to GND
(as in the case of a powered down driver).
2.7V
VALID RS-232 LEVEL - ISL3243E IS ACTIVE
INDETERMINATE - POWERDOWN MAY OR
MAY NOT OCCUR
0.3V
VL may range from 1.6V to VCC, and Table 3 indicates the
ISL324xE’s typical VIH and VIL levels for several VL values. Note
that the VL supply current increases significantly when
VL exceeds VCC (see Figure 20).
If logic translation isn’t required, connect VL to VCC.
VCCI = +3.3V
INVALID LEVEL - POWER-DOWN OCCURS AFTER 20ms
-0.3V
INDETERMINATE - POWERDOWN MAY OR
MAY NOT OCCUR
-2.7V
VALID RS-232 LEVEL - ISL3243E IS ACTIVE
VCCL = +1.8V
FIGURE 10. DEFINITION OF VALID RS-232 RECEIVER LEVELS
TIN
ROUT
VIH ≥ 2V
VOH ≤ 1.8V
TXD
INPUT
DIODE
VOH ≥ 3V
RXD
GND
GND
RS-232 IC WITH NO
VL PIN
INVALID switches low after invalid levels have persisted on all
of the receiver inputs for more than 20µs (see Figure 11).
INVALID switches back high 1µs after detecting a valid RS-232
level on a receiver input. INVALID operates in all modes (forced
or automatic power-down, or forced on), so it is also useful for
systems employing manual power-down circuitry. When
automatic powerdown is utilized, INVALID = 0 indicates that the
ISL3243E is in powerdown mode.
UART/PROCESSOR
VCCI = +3.3V
VCCL = +1.8V
TRANSMITTER
OUTPUTS
VL
TIN
ROUT
VIH ≤ 1V
TXD
VOH ≤ 1.8V
INPUT
DIODE
VOH ≤ 1.8V
RXD
GND
INVALID
} REGION
RECEIVER
INPUTS
GND
INVALID
OUTPUT
VL
0
tINVL
AUTOPWDN
tINVH
PWR UP
V+
VCC
ISL324xE
UART/PROCESSOR
FIGURE 9. USING VL PIN TO ADJUST LOGIC LEVELS
INVALID Output (ISL3243E Only)
The INVALID output always indicates whether or not a valid
RS-232 signal (see Figure 10) is present at any of the receiver
inputs (see Table 2), giving the user an easy way to determine
when the interface block should power down. Invalid receiver
levels occur whenever the driving peripheral’s outputs are shut
off (powered down) or when the RS-232 interface cable is
disconnected. In the case of a disconnected interface cable
where all the receiver inputs are floating (but pulled to GND by
the internal receiver pull down resistors), the INVALID logic
detects the invalid levels and drives the output low. The power
management logic then uses this indicator to power-down the
interface block. Reconnecting the cable restores valid levels at
11
0
V-
FIGURE 11. AUTOMATIC POWERDOWN AND INVALID TIMING
DIAGRAMS
Automatic Power-down (ISL3243E Only)
Even greater power savings is available by using the ISL3243E
which features an automatic power-down function. When no
valid RS-232 voltages (see Figure 11) are sensed on any
receiver input for 20µs, the charge pump and transmitters
power-down, thereby reducing supply current to less than 1µA.
Invalid receiver levels occur whenever the driving peripheral’s
outputs are shut off (powered down) or when the RS-232
interface cable is disconnected. The ISL3243E powers back up
whenever it detects a valid RS-232 voltage level on any
receiver input. This automatic power-down feature provides
FN6768.2
June 18, 2012
ISL3241E, ISL3243E
additional system power savings without changes to the
existing operating system.
Automatic power-down operates when the FORCEON input is
low, and the FORCEOFF input is high. Tying FORCEON high
disables automatic power-down, but manual powerdown is
always available via the overriding FORCEOFF input. Table 2
summarizes the automatic power-down functionality.
The time to recover from automatic power-down mode is
typically 20µs.
Capacitor Selection
The charge pumps require 0.1µF, or greater, capacitors for
proper operation. Increasing the capacitor values (by a factor
of 2) reduces ripple on the transmitter outputs and slightly
reduces power consumption.
When using minimum required capacitor values, make sure
that capacitor values do not degrade excessively with
temperature. If in doubt, use capacitors with a larger nominal
value. The capacitor’s equivalent series resistance (ESR)
usually rises at low temperatures and it influences the amount
of ripple on V+ and V-.
Power Supply Decoupling
Operation Down to 2.7V
ISL324xE transmitter outputs meet RS-562 levels (±3.7V), at
the full data rate, with VCC as low as 2.7V. RS-562 levels
typically ensure inter operability with RS-232 devices.
High Data Rates
The ISL324xE maintain the RS-232 ±5V minimum transmitter
output voltages even at high data rates. Figure 13 details a
transmitter loopback test circuit, and Figure 14 illustrates the
loopback test result at 120kbps. For this test, all transmitters
were simultaneously driving RS-232 loads in parallel with
1000pF, at 120kbps. Figure 15 shows the loopback results for
a single transmitter driving 1000pF and an RS-232 load at
250kbps. The static transmitters were also loaded with an
RS-232 receiver.
VCC
+
C1
0.1µF
VCC
C1+
C2
V+
ISL324xE
TIN
EN
FORCEON
VL
+
C3
C4
+
TOUT
RIN
ROUT
VL
V-
C2+
C2-
Transmitter Outputs when
Exiting Power-down
Figure 12 shows the response of two transmitter outputs when
exiting powerdown mode. As they activate, the two transmitter
outputs properly go to opposite RS-232 levels, with no
glitching, ringing, nor undesirable transients. Each transmitter
is loaded with 3kΩ in parallel with 1000pF. Note that the
transmitters enable only when the magnitude of V+ and Vexceeds approximately 3V.
VL
+
C1+
In most circumstances a 0.1µF bypass capacitor is adequate.
In applications that are particularly sensitive to power supply
noise, decouple VCC and VL to ground with a capacitor of the
same value as the charge-pump capacitor C1. Connect the
bypass capacitor as close as possible to the IC.
+
0.1µF
1000pF
5kΩ
FORCEOFF OR SHDN
FIGURE 13. TRANSMITTER LOOPBACK TEST CIRCUIT
3V/DIV.
T1IN
5V/DIV.
T1OUT
5V/DIV.
FORCEOFF
T1
3V/DIV.
R1OUT
VCC = +3.3V, VL = 1.8V
C1 TO C4 = 0.1µF
2V/DIV.
4µs/DIV.
FIGURE 14. LOOPBACK TEST AT 120kbps
T2
VCC = +3.3V, VL = 1.8V
C1 TO C4 = 0.1µF
TIME (20µs/DIV.)
FIGURE 12. TRANSMITTER OUTPUTS WHEN EXITING
POWERDOWN
12
FN6768.2
June 18, 2012
ISL3241E, ISL3243E
Human Body Model (HBM) Testing
As the name implies, this test method emulates the ESD event
delivered to an IC during human handling. The tester delivers
the charge through a 1.5kΩ current limiting resistor, making
the test less severe than the IEC61000 test which utilizes a
330Ω limiting resistor. The HBM method determines an ICs
ability to withstand the ESD transients typically present during
handling and manufacturing. Due to the random nature of
these events, each pin is tested with respect to all other pins.
The RS-232 pins on “E” family devices can withstand HBM ESD
events to ±15kV.
3V/DIV.
T1IN
5V/DIV.
T1OUT
3V/DIV.
R1OUT
IEC61000-4-2 Testing
VCC = +3.3V, VL = 1.8V
C1 TO C4 = 0.1µF
2µs/DIV.
FIGURE 15. LOOPBACK TEST AT 250kbps
Interconnection to 1.8V, and
2.5V Logic
Standard 3.3V powered RS-232 devices interface well with 3V
powered TTL compatible logic families (e.g., ACT and HCT).
The ISL324xE VL supply pin allows interconnection to 1.8V or
2.5V logic. By connecting VL to the same supply (1.8V or 2.5V)
powering the logic device, the ISL324XE logic outputs will
swing from GND to the logic VCC.
±15kV ESD Protection
All pins on ISL324xE devices include ESD protection structures,
but the RS-232 pins (transmitter outputs and receiver inputs)
incorporate advanced structures which allow them to survive
ESD events up to ±15kV. The RS-232 pins are particularly
vulnerable to ESD damage because they typically connect to
an exposed port on the exterior of the finished product. Simply
touching the port pins, or connecting a cable, can cause an
ESD event that might destroy unprotected ICs. These new ESD
structures protect the device whether or not it is powered up,
protect without allowing any latchup mechanism to activate,
and don’t interfere with RS-232 signals as large as ±25V.
13
The IEC61000 test method applies to finished equipment,
rather than to an individual IC. Therefore, the pins most likely
to suffer an ESD event are those that are exposed to the
outside world (the RS-232 pins in this case), and the IC is
tested in its typical application configuration (power applied)
rather than testing each pin-to-pin combination. The lower
current limiting resistor coupled with the larger charge storage
capacitor yields a test that is much more severe than the HBM
test. The extra ESD protection built into this device’s RS-232
pins allows the design of equipment meeting level 4 criteria
without the need for additional board level protection on the
RS-232 port.
AIR-GAP DISCHARGE TEST METHOD
For this test method, a charged probe tip moves toward the IC
pin until the voltage arcs to it. The current waveform delivered
to the IC pin depends on approach speed, humidity,
temperature, etc., so it is difficult to obtain repeatable results.
The “E” device RS-232 pins withstand ±15kV air-gap
discharges.
CONTACT DISCHARGE TEST METHOD
During the contact discharge test, the probe contacts the
tested pin before the probe tip is energized, thereby
eliminating the variables associated with the air-gap
discharge. The result is a more repeatable and predictable
test, but equipment limits prevent testing devices at voltages
higher than ±8kV. All “E” family devices survive ±8kV contact
discharges on the RS-232 pins.
FN6768.2
June 18, 2012
ISL3241E, ISL3243E
Typical Performance Curves
VCC = 3.3V, VL = 1.8V, TA = +25°C
25
TRANSMITTER OUTPUT VOLTAGE (V)
6
RL = 3kΩ
+VOUT
4
SLEW RATE (V/µs)
20
2
1 TRANSMITTER AT 250kbps
OTHER TRANSMITTERS AT 30kbps
RL = 3kΩ ON ALL TOUTS
0
-2
15
+SLEW
-SLEW
10
-VOUT
-4
-6
0
1000
2000
3000
4000
5
5000
0
1000
2000
250kbps
35
30
120kbps
25
20
20kbps
15
5
4
3
2
1
10
1000
0
2000
4000
3000
0
5000
0
0.5
1.0
1.5
LOAD CAPACITANCE (pF)
2.5
3.0
3.5
4.0
FIGURE 19. SUPPLY CURRENT vs SUPPLY VOLTAGE
10
50
RECEIVER OUTPUT CURRENT (mA)
NO LOAD
ALL OUTPUTS STATIC
VCC = 3.3V
40
IL (nA)
2.0
SUPPLY VOLTAGE (V)
FIGURE 18. SUPPLY CURRENT vs LOAD CAPACITANCE WHEN
TRANSMITTING DATA
30
VL ≤ VCC
20
VL > VCC
10
0
5000
NO LOAD, VL = VCC
ALL OUTPUTS STATIC
6
SUPPLY CURRENT (mA)
40
SUPPLY CURRENT (mA)
7
1 TRANSMITTER SWITCHING
OTHER TRANSMITTERS STATIC
RL = 3kΩ ON ALL TOUTS
4000
FIGURE 17. SLEW RATE vs LOAD CAPACITANCE
FIGURE 16. TRANSMITTER OUTPUT VOLTAGE vs LOAD
CAPACITANCE
45
3000
LOAD CAPACITANCE (pF)
LOAD CAPACITANCE (pF)
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VL (V)
FIGURE 20. VL SUPPLY CURRENT vs VL VOLTAGE
14
4.0
VOL, VL = 3.3V
9
VOH, VL = 3.3V
VOL, VL = 2.5V
8
7
6
VOH, VL = 2.5V
5
VOL, VL = 1.8V
4
VOL, VL = 1.6V
3
2
VOH, VL = 1.6V
1
0
0
0.5
VOH, VL = 1.8V
1.0
1.5
2.0
2.5
3.0
3.3
RECEIVER OUTPUT VOLTAGE (V)
FIGURE 21. RECEIVER OUTPUT CURRENT vs RECEIVER OUTPUT
VOLTAGE
FN6768.2
June 18, 2012
ISL3241E, ISL3243E
Die Characteristics
SUBSTRATE AND QFN THERMAL PAD POTENTIAL (POWERED UP):
GND
TRANSISTOR COUNT:
464
PROCESS:
SI GATE BICMOS
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
15
FN6768.2
June 18, 2012
ISL3241E, ISL3243E
Package Outline Drawing
L32.5x5B
32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 11/07
4X 3.5
5.00
28X 0.50
A
B
6
PIN 1
INDEX AREA
6
PIN #1 INDEX AREA
32
25
1
5.00
24
3 .30 ± 0 . 15
17
(4X)
8
0.15
9
16
0.10 M C A B
+ 0.07
32X 0.40 ± 0.10
TOP VIEW
4 32X 0.23 - 0.05
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
0 . 90 ± 0.1
C
BASE PLANE
SEATING PLANE
0.08 C
( 4. 80 TYP )
( 28X 0 . 5 )
SIDE VIEW
( 3. 30 )
(32X 0 . 23 )
C
0 . 2 REF
5
( 32X 0 . 60)
0 . 00 MIN.
0 . 05 MAX.
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance: Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
16
FN6768.2
June 18, 2012
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