ESD110-B1-02EL Data Sheet (886 KB, EN)

Protection Device
TVS (Transient Voltage Suppressor)
ESD110-B1 Series
Bi-directional, 18.5 V (AC), 0.3 pF, 0201, 0402, RoHS and Halogen Free compliant
ESD110-B1-02ELS
ESD110-B1-02EL
Data Sheet
Revision 1.4, 2014-10-23
Final
Power Management & Multimarket
Edition 2014-10-23
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2014 Infineon Technologies AG
All Rights Reserved.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com)
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
ESD110-B1 Series
Product Overview
1
Product Overview
1.1
Features
•
•
•
•
•
•
ESD / transient protection according to:
– IEC61000-4-2 (ESD): ±15 kV (air), ±12 kV (contact)
– IEC61000-4-5 (Surge): ±2 A (tp = 8 / 20 µs)
Bi-directional, working voltage up to VRWM = ±18.5 V (AC)
Ultra-low capacitance: CL = 0.3 pF (typical)
Low clamping voltage: VCL = 28 V (typical) at ITLP = 16 A
Very low reverse current: IR < 1 nA (typical)
Pb-free (RoHS compliant) and halogen free package
1.2
•
Application Examples
ESD Protection of RF signal lines in Near Field Communication (NFC) applications
1.3
Product Description
Pin 1 marking
(lasered)
Pin 1
Pin 1
Pin 2
Pin 2
PinConf_and_SchematicDiag.vsd
Figure 1-1
Pin Configuration and Schematic Diagram
Table 1-1
Part Information
Type
Package
Configuration
Marking code
ESD110-B1-02ELS
TSSLP-2-4
1 line, bi-directional
X
ESD110-B1-02EL
TSLP-2-20
1 line, bi-directional
XX
Final Data Sheet
3
Revision 1.4, 2014-10-23
ESD110-B1 Series
Maximum Ratings
2
Maximum Ratings
Table 2-1
Maximum Ratings at TA = 25 °C, unless otherwise specified1)
Parameter
Symbol
2)
Values
Unit
ESD air discharge
ESD contact discharge2)
VESD
±15
±12
kV
Peak pulse power3)
PPK
58
W
Peak pulse current3)
IPP
±2
A
Operating temperature
TOP
-40 to 125
°C
Storage temperature
Tstg
-55 to 150
°C
1) Device is electrically symmetrical
2) VESD according to IEC61000-4-2
3) Non-repetitive current pulse 8/20µs exponential decay waveform according to IEC61000-4-5
Attention: Stresses above the max. values listed here may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect device
reliability. Maximum ratings are absolute ratings; exceeding only one of these values may
cause irreversible damage to the integrated circuit.
3
Electrical Characteristics at TA = 25 °C, unless otherwise specified
( )!! %! )*
!
+! )#! % ##%# !"!!""!" #$%"&!'!! Figure 3-1 Definitions of electrical characteristics
Final Data Sheet
4
Revision 1.4, 2014-10-23
ESD110-B1 Series
Electrical Characteristics at TA = 25 °C, unless otherwise specified
Table 3-1
DC Characteristics at TA = 25 °C, unless otherwise specified1)
Parameter
Symbol
Reverse working voltage VRWM
Values
Min.
Typ.
Max.
-18.5
–
18.5
-15
–
15
Unit
Note / Test Condition
V
for AC voltages (NFC)
for DC voltages
Trigger voltage
Vt1
20
–
–
V
Holding voltage
Vh
20
21
26
V
–
19
–
–
<1
30
–
10
–
Reverse leakage current
IR
TA = 25 °C, IT = 0.5 mA
TA = 125 °C, IT = 0.5 mA
nA
TA = 25 °C, VR = 18.5 V
TA = 125 °C, VR = 18.5 V
1) Device is electrically symmetrical
Table 3-2
AC Characteristics at TA = 25 °C, unless otherwise specified
Parameter
Symbol
CL
Line capacitance
LS
Serie inductance
Table 3-3
Values
Min.
Typ.
Max.
0.15
0.3
0.5
0.15
0.3
0.5
–
0.2
–
–
0.4
–
Unit
Note / Test Condition
pF
VR = 0 V, f = 1 MHz
VR = 0 V, f = 1 GHz
nH
ESD110-B1-02ELS
ESD110-B1-02EL
ESD and Surge Characteristics at TA = 25 °C, unless otherwise specified1)
Parameter
Symbol
2)
VCL
Clamping voltage
3)
VCL
Clamping voltage
Dynamic resistance
2)
RDYN
Values
Unit
Note / Test Condition
V
ITLP = 16 A, tp = 100 ns
Min.
Typ.
Max.
–
30
35
–
39
44
ITLP = 30 A, tp = 100 ns
–
19
24
IPP = 1 A, tp = 8/20 μs
–
24
29
IPP = 2 A, tp = 8/20 μs
–
0.6
–
Ω
tp = 100 ns
1) Device is electrically symmetrical
2) Please refer to Application Note AN210[1]. TLP parameter: Z0 = 50 Ω , tp = 100ns, tr = 300ps
3) Non-repetitive current pulse 8/20µs exponential decay waveform according to IEC61000-4-5
Final Data Sheet
5
Revision 1.4, 2014-10-23
ESD110-B1 Series
Typical Characteristics Diagrams
4
Typical Characteristics Diagrams
Typical characteristics diagrams at TA=25°C, unless otherwise specified
-3
10
-4
10
-5
10
-6
10
IR [A]
10-7
-8
10
-9
10
10-10
10
-11
10
-12
0
5
10
VR [V]
15
20
Figure 4-1 Reverse leakage current: IR = f(VR)
0.6
0.5
CL [pF]
0.4
1 MHz
0.3
0.2
1 GHz
0.1
0
0
2
4
6
8
10
VR [V]
12
14
16
18
20
Figure 4-2 Line capacitance: CL = f(VR)
Final Data Sheet
6
Revision 1.4, 2014-10-23
ESD110-B1 Series
Typical Characteristics Diagrams
160
Scope: 6 GHz, 20 GS/s
140
120
VCL [V]
100
VCL-max-peak = 142 V
80
VCL-30ns-peak = 26 V
60
40
20
0
-20
-50
0
50
100
150
200
tp [ns]
250
300
350
400
450
Figure 4-3 Clamping voltage (ESD): VCL = f(t), 8 kV positiv pulse from pin 1 to pin 2
20
Scope: 6 GHz, 20 GS/s
0
-20
VCL [V]
-40
-60
-80
-100
VCL-max-peak = -144 V
-120
VCL-30ns-peak = -25 V
-140
-160
-50
0
50
100
150
200
tp [ns]
250
300
350
400
450
Figure 4-4 Clamping voltage (ESD): VCL = f(t), 8 kV negativ pulse from pin 1 to pin 2
Final Data Sheet
7
Revision 1.4, 2014-10-23
ESD110-B1 Series
Typical Characteristics Diagrams
200
Scope: 6 GHz, 20 GS/s
175
150
VCL [V]
125
VCL-max-peak = 187 V
100
VCL-30ns-peak = 33 V
75
50
25
0
-25
-50
0
50
100
150
200
tp [ns]
250
300
350
400
450
Figure 4-5 Clamping voltage (ESD): VCL = f(t), 15 kV positiv pulse from pin 1 to pin 2
25
Scope: 6 GHz, 20 GS/s
0
-25
VCL [V]
-50
-75
-100
-125
VCL-max-peak = -181 V
-150
VCL-30ns-peak = -31 V
-175
-200
-50
0
50
100
150
200
tp [ns]
250
300
350
400
450
Figure 4-6 Clamping voltage (ESD): VCL = f(t), 15 kV negativ pulse from pin 1 to pin 2
Final Data Sheet
8
Revision 1.4, 2014-10-23
ESD110-B1 Series
Typical Characteristics Diagrams
30
15
ESD110-B1 Series
RDYN
25
12.5
20
10
15
7.5
10
5
5
2.5
0
0
-5
-2.5
-10
-5
-15
-7.5
Equivalent VIEC [kV]
ITLP [A]
RDYN = 0.6 Ω
RDYN = 0.6 Ω
-20
-10
-25
-12.5
-30
-15
-40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40
VTLP [V]
Figure 4-7 Clamping voltage (TLP): ITLP = f(VTLP) [1], pin 1 to pin 2
Final Data Sheet
9
Revision 1.4, 2014-10-23
ESD110-B1 Series
Typical Characteristics Diagrams
2.5
2
1.5
1
IPP [A]
0.5
0
-0.5
-1
-1.5
-2
-2.5
-30
-25
-20
-15
-10
-5
0
5
VCL [V]
10
15
20
25
30
Figure 4-8 Clamping voltage(Surge): IPP = f(VCL)
Final Data Sheet
10
Revision 1.4, 2014-10-23
ESD110-B1 Series
Typical Characteristics Diagrams
0
-2
Insertion Loss [dB]
-4
-6
-8
-10
-12
ESD110-B1-02EL
ESD110-B1-02ELS
-14
-16
10
100
1000
f [MHz]
10000
Figure 4-9 Insertion loss vs. frequency in a 50 Ω system
Final Data Sheet
11
Revision 1.4, 2014-10-23
ESD110-B1 Series
Application Information
Application Information
Mobile phone
Main PCB / Top shell
differential antenna
Interconnection
top/bottom shell
“external pads”
RF=13. 56MHz
signal vs . GND<+-18V p
+V signal vs . -V signal <36V!!!
TX+
NFC Mo dule
T X/ RX sectio n
Bottom shell
loop +
TXGND
E MI- LP filter
Antenna
m atching
RX
Lo opan te nna
~ 1µH
5
GND
loop-
Ca p s sho uld b e hig h
vo lta g e typ e to b e sa ve
r e g a r d s the r e sid ua l
E SD p e a k
Mobile phone
Main PCB / Top shell
single ended antenna
Interconnection
top /bottom shell
“external pads”
Bottom shell
RF=13. 56MHz
signal vs . GND<+-18V p
NFC Modul e
TX/ RX sectio n
TX+
loop
TXGND
RX
E MI
- LP filter
Antenna
m atching
GND
Ca p s sho uld b e hig h
vo lta g e typ e to b e sa ve
r e g a r d s the r e sid ua l
E SD p e a k
E S D18V_applic ation ex ample . v s d
Figure 5-1 Bi-directional ESD / Transient protection for NFC Frontend [3]
Final Data Sheet
12
Revision 1.4, 2014-10-23
ESD110-B1 Series
Package Information
6
Package Information
6.1
TSSLP-2-4
Top view
Bottom view
0.31 +0.01
-0.02
0.32 ±0.05
0.355
0.62 ±0.05
2
Pin 1
marking
0.05 MAX.
0.26 ±0.035
0.2 ±0.035 1)
1
1)
1) Dimension applies to plated terminals
TSSLP-2-3, -4-PO V01
Figure 6-1 TSSLP-2-4: Package outline
0.19
0.24
Solder mask
0.19
0.57
0.14
0.62
Copper
0.19
0.27
0.24
0.32
Stencil apertures
TSSLP-2-3, -4-FP V02
Figure 6-2 TSSLP-2-4: Footprint
0.35
Tape type
Ex Ey
Punched Tape
0.43 0.73
Embossed Tape 0.37 0.67
8
Ey
4
Deliveries can be both tape types (no selection possible).
Specification allows identical processing (pick & place) by users.
Pin 1
marking
Ex
TSSLP-2-3, -4-TP V03
Figure 6-3 TSSLP-2-4: Packing
1
Type code
Pin 1 marking
TSSLP-2-3, -4-MK V01
Figure 6-4 TSSLP-2-4: Marking (example) Table 1-1 “Part Information” on Page 3
Final Data Sheet
13
Revision 1.4, 2014-10-23
ESD110-B1 Series
Package Information
6.2
TSLP-2-20
Top view
Bottom view
0.31 +0.01
-0.02
0.6 ±0.05
1±0.05
2
1
0.25 ±0.035 1)
0.65 ±0.05
0.05 MAX.
0.5 ±0.035 1)
Pin 1
marking
1) Dimension applies to plated terminals
TSLP-2-19, -20-PO V01
Figure 6-5 TSLP-2-20: Package overview
0.28
0.35
Solder mask
0.38
0.93
0.3
1
Copper
0.28
0.45
0.35
0.6
Stencil apertures
TSLP-2-19, -20-FP V01
Figure 6-6 TSLP-2-20: Footprint
0.4
1.16
Pin 1
marking
8
4
0.76
TSLP-2-19, -20-TP V02
Figure 6-7 TSLP-2-20: Packing
Type code
12
Pin 1 marking
TSLP-2-19, -20-MK V01
Figure 6-8 TSLP-2-20: Marking example Table 1-1 “Part Information” on Page 3
Final Data Sheet
14
Revision 1.4, 2014-10-23
ESD110-B1 Series
References
References
[1]
Infineon AG - Application Note AN210: Effective ESD Protection design at System Level Using VF-TLP
Characterization Methodology
[2]
Infineon AG - Recommendations for PCB Assembly of Infineon TSLP and TSSLP Packages
[3]
Infineon AG - Application Note AN244: Tailored ESD Protection for the NFC Frontend
Final Data Sheet
15
Revision 1.4, 2014-10-23
ESD110-B1 Series
Revision History: Rev. 1.3, 2014-04-08
Page or Item
Subjects (major changes since previous revision)
Revision 1.4, 2014-10-23
4
Table 2-1) updated
Trademarks of Infineon Technologies AG
AURIX™, BlueMoon™, COMNEON™, C166™, CROSSAVE™, CanPAK™, CIPOS™, CoolMOS™, CoolSET™,
CORECONTROL™, DAVE™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPACK™, EconoPIM™,
EiceDRIVER™, EUPEC™, FCOS™, HITFET™, HybridPACK™, ISOFACE™, I²RF™, IsoPACK™, MIPAQ™,
ModSTACK™, my-d™, NovalithIC™, OmniTune™, OptiMOS™, ORIGA™, PROFET™, PRO-SIL™,
PRIMARION™, PrimePACK™, RASIC™, ReverSave™, SatRIC™, SIEGET™, SINDRION™, SMARTi™,
SmartLEWIS™, TEMPFET™, thinQ!™, TriCore™, TRENCHSTOP™, X-GOLD™, XMM™, X-PMU™,
XPOSYS™.
Other Trademarks
Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, PRIMECELL™,
REALVIEW™, THUMB™ of ARM Limited, UK. AUTOSAR™ is licensed by AUTOSAR development partnership.
Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™, FirstGPS™ of Trimble Navigation
Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of Epcos AG. FLEXGO™ of Microsoft Corporation.
FlexRay™ is licensed by FlexRay Consortium. HYPERTERMINAL™ of Hilgraeve Incorporated. IEC™ of
Commission Electrotechnique Internationale. IrDA™ of Infrared Data Association Corporation. ISO™ of
INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of MathWorks, Inc. MAXIM™ of
Maxim Integrated Products, Inc. MICROTEC™, NUCLEUS™ of Mentor Graphics Corporation. Mifare™ of NXP.
MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™ of MURATA
MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc., OmniVision™ of
OmniVision Technologies, Inc. Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF
Micro Devices, Inc. SIRIUS™ of Sirius Sattelite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™
of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co.
TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™
of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas
Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes
Zetex Limited.
Last Trademarks Update 2010-06-09
Final Data Sheet
16
Revision 1.4, 2014-10-23
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Published by Infineon Technologies AG
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