Si1401EDH Datasheet

New Product
Si1401EDH
Vishay Siliconix
P-Channel 12 V (D-S) MOSFET
FEATURES
PRODUCT SUMMARY
RDS(on) ()
ID (A)a
0.034 at VGS = - 4.5 V
-4
VDS (V)
- 12
0.046 at VGS = - 2.5 V
-4
0.070 at VGS = - 1.8 V
-4
0.110 at VGS = - 1.5 V
-4
• Halogen-free According to IEC 61249-2-21
Definition
• TrenchFET® Power MOSFET
• Typical ESD Performance 1500 V
• 100 % Rg Tested
• Compliant to RoHS Directive 2002/95/EC
Qg (Typ.)
14.1 nC
APPLICATIONS
• Load Switch, PA Switch and Battery Switch for Portable
SOT-363
SC-70 (6-LEADS)
D
1
6
D
D
2
5
D
G
3
4
S
Marking Code
Devices
- Cellular Phone
- DSC
- Portable Game Console
- MP3
- GPS
S
G
R
BPX
Part # code
XXX
Lot Traceability
and Date code
Top View
D
Ordering Information: Si1401EDH-T1-GE3 (Lead (Pb)-free and Halogen-free)
P-Channel MOSFET
ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted
Parameter
Symbol
Limit
Drain-Source Voltage
VDS
- 12
Gate-Source Voltage
VGS
± 10
TC = 70 °C
TA = 25 °C
- 4a
ID
- 4a, b, c
- 4a, b, c
TA = 70 °C
Pulsed Drain Current
Continuous Source-Drain Diode Current
IDM
TC = 25 °C
TA = 25 °C
TC = 70 °C
TA = 25 °C
- 2.3
IS
- 1.3b, c
2.8
1.8
PD
W
1.6b, c
1.0b, c
TA = 70 °C
Operating Junction and Storage Temperature Range
A
- 25
TC = 25 °C
Maximum Power Dissipation
V
- 4a
TC = 25 °C
Continuous Drain Current (TJ = 150 °C)
Unit
TJ, Tstg
- 55 to 150
°C
260
Soldering Recommendations (Peak Temperature)
THERMAL RESISTANCE RATINGS
Parameter
Symbol
Typical
Maximum
Maximum Junction-to-Ambientb, d
t5s
RthJA
60
80
Maximum Junction-to-Foot (Drain)
Steady State
RthJF
34
45
Unit
°C/W
Notes:
a. Package limited.
b. Surface mounted on 1" x 1" FR4 board.
c. t = 5 s.
d. Maximum under steady state conditions is 125 °C/W.
Document Number: 70080
S10-1537-Rev. A, 19-Jul-10
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1
New Product
Si1401EDH
Vishay Siliconix
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
Parameter
Symbol
Test Conditions
Min.
VDS
VGS = 0 V, ID = - 250 µA
- 12
Typ.
Max.
Unit
Static
Drain-Source Breakdown Voltage
VDS/TJ
VDS Temperature Coefficient
VGS(th) Temperature Coefficient
VGS(th)/TJ
Gate-Source Threshold Voltage
VGS(th)
Gate-Source Leakage
ID = - 250 µA
VDS = VGS, ID = - 250 µA
IGSS
Zero Gate Voltage Drain Current
IDSS
On-State Drain Currenta
ID(on)
- 0.4
Forward Transconductancea
-1
VDS = 0 V, VGS = ± 8 V
±5
VDS = 0 V, VGS = ± 4.5 V
±1
VDS = - 12 V, VGS = 0 V
-1
VDS = - 12 V, VGS = 0 V, TJ = 55 °C
VDS - 5 V, VGS = - 10 V
RDS(on)
gfs
mV/°C
2.5
V
µA
- 10
- 15
VGS = - 4.5 V, ID = - 5.5 A
Drain-Source On-State Resistancea
V
- 5.2
A
0.028
0.034
VGS = - 2.5 V, ID = - 4.8 A
0.038
0.046
VGS = - 1.8 V, ID = - 1.4 A
0.053
0.070
VGS = - 1.5 V, ID = - 0.9 A
0.072
0.110
VDS = - 6 V, ID = - 5.5 A
16

S
Dynamicb
Total Gate Charge
Gate-Source Charge
Qgd
Gate Resistance
Rg
Rise Time
Turn-Off Delay Time
Fall Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
VDS = - 6 V, VGS = - 4.5 V, ID = - 5.5 A
Qgs
Gate-Drain Charge
Turn-On Delay Time
VDS = - 6 V, VGS = - 8 V, ID = - 5.5 A
Qg
24
36
14.1
22
1.9
nC
4
f = 1 MHz
td(on)
VDD = - 6 V, RL = 1.4 
ID  - 4.4 A, VGEN = - 4.5 V, Rg = 1 
tr
td(off)
0.08
0.42
0.84
160
240
420
630
1325
1990
tf
985
1480
td(on)
72
110
VDD = - 6 V, RL = 1.4 
ID  - 4.4 A, VGEN = - 8 V, Rg = 1 
tr
td(off)
tf
210
320
2100
3150
1015
1525
k
ns
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
TC = 25 °C
IS
Pulse Diode Forward Current
ISM
Body Diode Voltage
VSD
- 2.3
- 25
IS = - 5.5 A, VGS = 0 V
- 0.85
- 1.2
A
V
Body Diode Reverse Recovery Time
trr
27
50
ns
Body Diode Reverse Recovery Charge
Qrr
12
25
nC
Reverse Recovery Fall Time
ta
Reverse Recovery Rise Time
tb
IF = - 5.5 A, dI/dt = 100 A/µs, TJ = 25 °C
10
17
ns
Notes:
a. Pulse test; pulse width  300 µs, duty cycle  2 %.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
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Document Number: 70080
S10-1537-Rev. A, 19-Jul-10
New Product
Si1401EDH
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
0.1
10-3
10-4
IGSS - Gate Current (A)
IGSS - Gate Current (mA)
0.08
0.06
0.04
10-5
TJ = 150 °C
10-6
10-7
TJ = 25 °C
10-8
0.02
10-9
10-10
0
0
3
6
9
12
15
0
3
6
VGS - Gate-Source Voltage (V)
12
Gate Current vs. Gate-Source Voltage
25
5
VGS = 5 V thru 3 V
VGS = 2.5 V
20
ID - Drain Current (A)
4
15
VGS = 2 V
10
5
3
TC = 25 °C
2
TC = 125 °C
1
VGS = 1.5 V
TC = - 55 °C
0
0
0.5
1.0
1.5
0
2.0
0
0.4
0.8
1.2
1.6
VDS - Drain-to-Source Voltage (V)
VGS - Gate-to-Source Voltage (V)
Output Characteristics
Transfer Characteristics
8
0.10
VGS = 1.5 V
VGS - Gate-to-Source Voltage (V)
ID = 5.5 A
VGS = 1.8 V
0.08
RDS(on) - On-Resistance (Ω)
15
VGS - Gate-Source Voltage (V)
Gate Current vs. Gate-Source Voltage
ID - Drain Current (A)
9
0.06
VGS = 2.5 V
0.04
VGS = 4.5 V
0.02
6
VDS = 3 V
VDS = 6 V
4
VDS = 9.6 V
2
0
0.00
0
5
10
15
20
ID - Drain Current (A)
On-Resistance vs. Drain Current
Document Number: 70080
S10-1537-Rev. A, 19-Jul-10
25
0
5
10
15
20
25
Qg - Total Gate Charge (nC)
Gate Charge
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New Product
Si1401EDH
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
1.5
100
V GS = - 4.5 V; I D = - 5.5 A
IS - Source Current (A)
RDS(on) - On-Resistance
(Normalized)
10
1.3
1.1
0.9
1
TJ = 150 °C
TJ = 25 °C
0.1
TJ = - 50 °C
0.01
V GS = - 2.5 V; I D = - 4.8 A
0.7
- 50
- 25
0
25
50
75
100
125
0.001
0.0
150
0.2
TJ - Junction Temperature (°C)
0.4
0.6
0.8
1.0
1.2
VSD - Source-to-Drain Voltage (V)
On-Resistance vs. Junction Temperature
Source-Drain Diode Forward Voltage
30
0.12
ID = 5.5 A
0.06
Power (W)
RDS(on) - On-Resistance (Ω)
24
0.09
TJ = 125 °C
0.03
TJ = 25 °C
2
12
6
0
0.001
0.00
1
18
3
4
5
0.01
0.1
VGS - Gate-to-Source Voltage (V)
0.80
100
Limited by RDS(on)*
10
ID - Drain Current (A)
0.65
ID = - 250 μA
VGS(th) (V)
10
Single Pulse Power, Junction-to-Ambient
On-Resistance vs. Gate-to-Source Voltage
0.50
0.35
100 μs
1 ms
1
10 ms
100 ms
1s
10 s
DC
0.1
BVDSS Limited
TA = 25 °C
Single Pulse
0.20
- 50
1
Time (s)
- 25
0
25
50
75
100
TJ - Junction Temperature (°C)
Threshold Voltage
125
150
0.01
0.1
1
10
100
VDS - Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified
Safe Operating Area, Junction-to-Ambient
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Document Number: 70080
S10-1537-Rev. A, 19-Jul-10
New Product
Si1401EDH
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
10
ID - Drain Current (A)
8
6
Package Limited
4
2
0
0
25
50
75
100
125
150
TC - Case Temperature (°C)
1.2
4
0.9
3
Power (W)
Power (W)
Current Derating*
0.6
0.3
2
1
0
0
0
25
50
75
100
125
150
0
25
50
75
100
125
TA - Ambient Temperature (°C)
TC - Case Temperature (°C)
Power Derating, Junction-to-Ambient
Power Derating, Junction-to-Foot
150
* The power dissipation PD is based on TJ(max) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.
Document Number: 70080
S10-1537-Rev. A, 19-Jul-10
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New Product
Si1401EDH
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
1
Normalized Effective Transient
Thermal Impedance
Duty Cycle = 0.5
0.2
Notes:
0.1
0.1
PDM
0.05
t1
t2
0.02
1. Duty Cycle, D =
t1
t2
2. Per Unit Base = RthJA = 125 °C/W
3. TJM - TA = PDMZthJA (t)
Single Pulse
0.01
10-4
10
4. Surface Mounted
-3
-2
10
-1
10
1
10
100
1000
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient
1
Normalized Effective Transient
Thermal Impedance
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
10-4
10-3
10-2
10-1
1
10
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Foot
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?70080.
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6
Document Number: 70080
S10-1537-Rev. A, 19-Jul-10
Package Information
Vishay Siliconix
SCĆ70:
6ĆLEADS
MILLIMETERS
6
5
Dim
A
A1
A2
b
c
D
E
E1
e
e1
L
4
E1 E
1
2
3
-B-
e
b
e1
D
-Ac
A2 A
L
A1
Document Number: 71154
06-Jul-01
INCHES
Min
Nom
Max
Min
Nom
Max
0.90
–
1.10
0.035
–
0.043
–
–
0.10
–
–
0.004
0.80
–
1.00
0.031
–
0.039
0.15
–
0.30
0.006
–
0.012
0.10
–
0.25
0.004
–
0.010
1.80
2.00
2.20
0.071
0.079
0.087
1.80
2.10
2.40
0.071
0.083
0.094
1.15
1.25
1.35
0.045
0.049
0.053
0.65BSC
0.026BSC
1.20
1.30
1.40
0.047
0.051
0.055
0.10
0.20
0.30
0.004
0.008
0.012
7_Nom
7_Nom
ECN: S-03946—Rev. B, 09-Jul-01
DWG: 5550
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AN815
Vishay Siliconix
Single-Channel LITTLE FOOTR SC-70 6-Pin MOSFET
Copper Leadframe Version
Recommended Pad Pattern and Thermal Performance
INTRODUCTION
EVALUATION BOARDS SINGLE SC70-6
The new single 6-pin SC-70 package with a copper leadframe
enables improved on-resistance values and enhanced
thermal performance as compared to the existing 3-pin and
6-pin packages with Alloy 42 leadframes. These devices are
intended for small to medium load applications where a
miniaturized package is required. Devices in this package
come in a range of on-resistance values, in n-channel and
p-channel versions. This technical note discusses pin-outs,
package outlines, pad patterns, evaluation board layout, and
thermal performance for the single-channel version.
The evaluation board (EVB) measures 0.6 inches by
0.5 inches. The copper pad traces are the same as in Figure 2.
The board allows examination from the outer pins to 6-pin DIP
connections, permitting test sockets to be used in evaluation
testing. See Figure 3.
52 (mil)
BASIC PAD PATTERNS
See Application Note 826, Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs, (http://www.vishay.com/doc?72286) for the basic
pad layout and dimensions. These pad patterns are sufficient
for the low to medium power applications for which this
package is intended. Increasing the drain pad pattern yields a
reduction in thermal resistance and is a preferred footprint.
The availability of four drain leads rather than the traditional
single drain lead allows a better thermal path from the package
to the PCB and external environment.
96 (mil)
6
5
4
1
2
3
71 (mil)
26 (mil)
13 (mil)
0, 0 (mil)
18 (mil)
26 (mil)
PIN-OUT
16 (mil)
Figure 1 shows the pin-out description and Pin 1
identification.The pin-out of this device allows the use of four
pins as drain leads, which helps to reduce on-resistance and
junction-to-ambient thermal resistance.
SOT-363
SC-70 (6-LEADS)
D
1
6
D
D
2
5
D
G
3
4
S
FIGURE 2.
SC-70 (6 leads) Single
The thermal performance of the single 6-pin SC-70 has been
measured on the EVB, comparing both the copper and
Alloy 42 leadframes. This test was first conducted on the
traditional Alloy 42 leadframe and was then repeated using the
1-inch2 PCB with dual-side copper coating.
Top View
FIGURE 1.
For package dimensions see outline drawing SC-70 (6-Leads)
(http://www.vishay.com/doc?71154)
Document Number: 71334
12-Dec-03
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1
AN815
Vishay Siliconix
Front of Board SC70-6
Back of Board SC70-6
vishay.com
FIGURE 3.
THERMAL PERFORMANCE
Junction-to-Foot Thermal Resistance
(Package Performance)
COOPER LEADFRAME
Room Ambient 25 _C
The junction to foot thermal resistance is a useful method of
comparing different packages thermal performance.
A helpful way of presenting the thermal performance of the
6-Pin SC-70 copper leadframe device is to compare it to the
traditional Alloy 42 version.
Thermal performance for the 6-pin SC-70 measured as
junction-to-foot thermal resistance, where the “foot” is the
drain lead of the device at the bottom where it meets the PCB.
The junction-to-foot thermal resistance is typically 40_C/W in
the copper leadframe and 163_C/W in the Alloy 42 leadframe
— a four-fold improvement. This improved performance is
obtained by the enhanced thermal conductivity of copper over
Alloy 42.
The typical RqJA for the single 6-pin SC-70 with copper
leadframe is 103_C/W steady-state, compared with 212_C/W
for the Alloy 42 version. The figures are based on the 1-inch2
FR4 test board. The following example shows how the thermal
resistance impacts power dissipation for the two different
leadframes at varying ambient temperatures.
ALLOY 42 LEADFRAME
PD +
Rq JA
Elevated Ambient 60 _C
PD +
T J(max) * T A
Rq JA
o
o
P D + 150 Co* 25 C
212 CńW
o
o
P D + 150 Co* 25 C
212 CńW
P D + 590 mW
P D + 425 mW
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2
T J(max) * T A
T J(max) * T A
Rq JA
PD +
T J(max) * T A
Rq JA
o
o
P D + 150 Co* 25 C
124 CńW
o
o
P D + 150 Co* 60 C
124 CńW
P D + 1.01 W
P D + 726 mW
As can be seen from the calculations above, the compact 6-pin
SC-70 copper leadframe LITTLE FOOT power MOSFET can
handle up to 1 W under the stated conditions.
Testing
To further aid comparison of copper and Alloy 42 leadframes,
Figure 5 illustrates single-channel 6-pin SC-70 thermal
performance on two different board sizes and two different pad
patterns. The measured steady-state values of RqJA for the
two leadframes are as follows:
LITTLE FOOT 6-PIN SC-70
Power Dissipation
Room Ambient 25 _C
PD +
Elevated Ambient 60 _C
1) Minimum recommended pad pattern on
the EVB board V (see Figure 3.
1-inch2
2) Industry standard
PCB with
maximum copper both sides.
Alloy 42
Copper
329.7_C/W
208.5_C/W
211.8_C/W
103.5_C/W
The results indicate that designers can reduce thermal
resistance (RqJA) by 36% simply by using the copper
leadframe device rather than the Alloy 42 version. In this
example, a 121_C/W reduction was achieved without an
increase in board area. If increasing in board size is feasible,
a further 105_C/W reduction could be obtained by utilizing a
1-inch2 square PCB area.
The copper leadframe versions have the following suffix:
Single:
Si14xxEDH
Dual:
Si19xxEDH
Complementary: Si15xxEDH
Document Number: 71334
12-Dec-03
AN815
400
250
320
200
240
Thermal Resistance (C/W)
Thermal Resistance (C/W)
Vishay Siliconix
Alloy
42
160
Copper
80
150
Alloy
42
100
50
Copper
0
0
10-5
10-4
10-3
10-2
10-1
1
10
100
1000
10-5
Leadframe Comparison on EVB
Document Number: 71334
12-Dec-03
10-3
10-2
10-1
1
10
100
1000
Time (Secs)
Time (Secs)
FIGURE 4.
10-4
FIGURE 5.
Leadframe Comparison on Alloy 42 1-inch2 PCB
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3
Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR SC-70: 6-Lead
0.067
0.026
(0.648)
0.045
(1.143)
0.096
(2.438)
(1.702)
0.016
0.026
0.010
(0.406)
(0.648)
(0.241)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
APPLICATION NOTE
Return to Index
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18
Document Number: 72602
Revision: 21-Jan-08
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definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council
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Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that
all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU.
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requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference
to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21
conform to JEDEC JS709A standards.
Revision: 02-Oct-12
1
Document Number: 91000