ESD3V3U4ULC Data Sheet (1.4 MB, EN)

TVS Diodes
Transient Voltage Suppressor Diodes
ESD3V3U4ULC
Ultra-low Capacitance ESD / Transient Protection Array
ESD3V3U4ULC
Data Sheet
Rev. 1.6, 2013-02-20
Final
Power Management & Multimarket
Edition 2013-02-20
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2013 Infineon Technologies AG
All Rights Reserved.
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ESD3V3U4ULC
Revision History Revision 1.5, 2012-12-05
Page or Item
Subjects (major changes since previous revision)
Rev. 1.6, 2013-02-20
6
Small updateds in Table 3
Trademarks of Infineon Technologies AG
AURIX™, BlueMoon™, COMNEON™, C166™, CROSSAVE™, CanPAK™, CIPOS™, CoolMOS™, CoolSET™,
CORECONTROL™, DAVE™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPACK™, EconoPIM™,
EiceDRIVER™, EUPEC™, FCOS™, HITFET™, HybridPACK™, ISOFACE™, I²RF™, IsoPACK™, MIPAQ™,
ModSTACK™, my-d™, NovalithIC™, OmniTune™, OptiMOS™, ORIGA™, PROFET™, PRO-SIL™,
PRIMARION™, PrimePACK™, RASIC™, ReverSave™, SatRIC™, SIEGET™, SINDRION™, SMARTi™,
SmartLEWIS™, TEMPFET™, thinQ!™, TriCore™, TRENCHSTOP™, X-GOLD™, XMM™, X-PMU™,
XPOSYS™.
Other Trademarks
Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, PRIMECELL™,
REALVIEW™, THUMB™ of ARM Limited, UK. AUTOSAR™ is licensed by AUTOSAR development partnership.
Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™, FirstGPS™ of Trimble Navigation
Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of Epcos AG. FLEXGO™ of Microsoft Corporation.
FlexRay™ is licensed by FlexRay Consortium. HYPERTERMINAL™ of Hilgraeve Incorporated. IEC™ of
Commission Electrotechnique Internationale. IrDA™ of Infrared Data Association Corporation. ISO™ of
INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of MathWorks, Inc. MAXIM™ of
Maxim Integrated Products, Inc. MICROTEC™, NUCLEUS™ of Mentor Graphics Corporation. Mifare™ of NXP.
MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™ of MURATA
MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc., OmniVision™ of
OmniVision Technologies, Inc. Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF
Micro Devices, Inc. SIRIUS™ of Sirius Sattelite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™
of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co.
TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™
of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas
Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes
Zetex Limited.
Last Trademarks Update 2010-06-09
Final Data Sheet
3
Rev. 1.6, 2013-02-20
ESD3V3U4ULC
Ultra-low Capacitance ESD / Transient Protection Array
1
Ultra-low Capacitance ESD / Transient Protection Array
1.1
Features
•
•
•
•
•
•
•
ESD / transient protection of high speed data lines exceeding:
– IEC61000-4-2 (ESD): ±20 kV (air/contact)
– IEC61000-4-4 (EFT): ±2.5 kV (5/50ns)
– IEC61000-4-5 (Surge): ±3 A (8/20μs)
Maximum working voltage: VRWM = 3.3 V
Ultra low capacitance CL = 0.4 pF I/O to GND (typical)
Very low clamping voltage: VCL = 8 V (typical) at IPP = 16 A
Very low dynamic resistance: RDYN = 0.19 Ω (typical)
TSLP-9-1 package with pad pitch 0.5 mm, optimized pad design to simplify PCB layout
Pb-free and halogen free package (RoHS compliant)
1.2
•
•
•
Application Examples
USB 3.0, 10/100/1000 Ethernet, Firewire
DVI, HDMI, S-ATA, DisplayPort
Mobile HDMI Link, MDDI, MIPI, etc.
1.3
Product Description
Pin 9
Pin 8
Pin 1
Pin 2
Pin 3
Pin 7
Pin 6
Pin 4
Pin 5
Pin 1 Pin 2
Pin 4 Pin 5
GND
Pin 3
a) Pin configuration
b) Schematic diagram
PG-TSLP-9-1_PinConf_and_SchematicDiag.vsd
Figure 1
Pin Configuration and Schematic Diagram
Table 1
Ordering Information
Type
Package
Configuration
ESD3V3U4ULC
TSLP-9-1
4 lines, uni-directional
Final Data Sheet
4
Marking code
Z2
Rev. 1.6, 2013-02-20
ESD3V3U4ULC
Characteristics
2
Characteristics
Table 2
Maximum Rating at TA = 25 °C, unless otherwise specified
Parameter
Symbol
Values
Unit
Min.
Typ.
Max.
VESD
-20
–
20
kV
IPP
-3
–
3
A
Operating temperature
TOP
-40
–
125
°C
Storage temperature
1) VESD according to IEC61000-4-2
2) IPP according to IEC61000-4-5
Tstg
-65
–
150
°C
ESD contact discharge
1)
Peak pulse current (tp = 8/20 μs)
2.1
2)
Electrical Characteristics at TA = 25 °C, unless otherwise specified
Figure 2
&
"
%
!
!#$
"
$
!#$
Definitions of electrical characteristics[1]
Final Data Sheet
5
Rev. 1.6, 2013-02-20
ESD3V3U4ULC
Characteristics
Table 3
DC Characteristics at TA = 25 °C, unless otherwise specified
Parameter
Symbol
Values
Unit
Note /
Test Condition
Min.
Typ.
Max.
VRWM
–
–
3.3
V
I/O to GND
Reverse current
IR
–
1
50
nA
I/O to GND,
VR = 3.3 V
Breakdown voltage1)
VBR
–
6.2
–
V
I/O to GND,
Vt1
–
6.2
–
V
I/O to GND,
Vh
3.35
4
4.4
V
I/O to GND,
IR = 10 mA
Reverse working voltage
1)
1)
Reverse trigger voltage2)
Reverse holding voltage
2)
1) Voltage forced
2) Current forced
Table 4
RF Characteristics at TA = 25 °C, unless otherwise specified
Parameter
Symbol
1)
Line capacitance
CL
Values
Unit
Note /
Test Condition
Min.
Typ.
Max.
–
0.4
0.65
pF
VR = 0 V, f = 1 MHz,
I/O to GND
–
0.2
0.35
pF
VR = 0 V, f = 1 MHz,
I/O to I/O
Channel capacitance
matching between
I/O to GND
∆Ci/o-GND –
0.035
–
pF
VR = 0 V, f = 1 MHz,
I/O to GND
Channel capacitance
matching between
I/O to I/O
∆Ci/o-i/o
–
0.017
–
pF
VR = 0 V, f = 1 MHz,
I/O to I/O
1) Total capacitance line to ground
Final Data Sheet
6
Rev. 1.6, 2013-02-20
ESD3V3U4ULC
Characteristics
Table 5
ESD Characteristics at TA = 25 °C, unless otherwise specified
Parameter
Symbol
1)
Clamping volage
VCL
Values
Min.
Typ.
Max.
–
4.8
–
–
6.2
–
Unit
Note /
Test Condition
V
IPP = 1 A, tp = 8/20µs
from I/O to GND
IPP = 3 A, tp = 8/20µs
from I/O to GND
2)
Clamping voltage
Forward clamping voltage1)
VCL
VFC
–
8
–
ITLP = 16 A,
from I/O to GND
–
11
–
ITLP = 30 A,
from I/O to GND
–
1.4
–
IPP = 1 A, tp = 8/20µs
from GND to I/O
Forward clamping voltage2)
Dynamic resistance2)
VFC
RDYN
–
2.3
–
IPP = 3 A, tp = 8/20µs
from GND to I/O
–
6
–
ITLP = 16 A,
from GND to I/O
–
9
–
ITLP = 30 A,
from GND to I/O
–
0.19
–
Ω
I/O to GND
–
0.23
–
Ω
GND to any I/O
1) IPP according to IEC61000-4-5
2) Please refer to Application Note AN210. TLP parameter: Z0 = 50 Ω , tp = 100ns, tr = 300ps, averaging window: t1 = 30 ns
to t2 = 60 ns, extraction of dynamic resistance using least squares fit of TLP characteristic between IPP1 = 10 A and
IPP2 = 40 A [2].
Final Data Sheet
7
Rev. 1.6, 2013-02-20
ESD3V3U4ULC
Typical Characteristics at TA = 25 °C, unless otherwise specified
Typical Characteristics at TA = 25 °C, unless otherwise specified
IR [A]
3
-7
10
-8
10
-9
10
-10
10
-11
10
-12
0
1
2
VR [V]
3
4
Reverse current, IR = (VR)
10
-6
10
-7
10
-8
IR [A]
Figure 3
10
10-9
25
50
75
100
125
150
TA [°C]
Figure 4
Reverse current: IR = f(TA), VR = 3.3 V
Final Data Sheet
8
Rev. 1.6, 2013-02-20
ESD3V3U4ULC
Typical Characteristics at TA = 25 °C, unless otherwise specified
0.8
1MHz
1GHz
0.7
CL [pF]
0.6
0.5
0.4
0.3
0.2
Figure 5
0
0.5
1
1.5
2
VR [V]
2.5
3
3.5
Line capacitance: CL = f(VR), f = 1MHz, from I/O to GND
Final Data Sheet
9
Rev. 1.6, 2013-02-20
ESD3V3U4ULC
Typical Characteristics at TA = 25 °C, unless otherwise specified
50
ESD3V3U4UCL
RDYN
20
40
15
30
RDYN = 0.19 Ω
ITLP [A]
10
5
0
0
-10
-5
-20
Equivalent VIEC [kV]
10
20
-10
RDYN = 0.23 Ω
-30
-15
-40
-20
-50
-20
-15
-10
-5
0
5
10
15
20
VTLP [V]
Figure 6
Clamping voltage (TLP): ITLP = f(VTLP) according ANSI/ESD STM5.5.1- Electrostatic Discharge
Sensitivity Testing using Transmission Line Pulse (TLP) Model. TLP conditions: Z0 = 50 Ω,
tp = 100 ns, tr = 0.6 ns, ITLP and VTLP averaging window: t1 = 30 ns to t2 = 60 ns, extraction of
dynamic resistance using squares fit to TLP characteristics between ITLP1 = 10 A and
ITLP2 = 40 A. Please refer to Application Note AN210[2]
Final Data Sheet
10
Rev. 1.6, 2013-02-20
ESD3V3U4ULC
Typical Characteristics at TA = 25 °C, unless otherwise specified
5
ESD3V3U4ULC
RDYN
4
3
RDYN = 0.70 Ω
2
IPP [A]
1
0
-1
-2
RDYN = 0.44 Ω
-3
-4
-5
-10
Figure 7
-8
-6
-4
-2
0
VCL [V]
2
4
6
8
10
Pulse current (IEC61000-4-5) versus clamping voltage: IPP = f(VCL)
Final Data Sheet
11
Rev. 1.6, 2013-02-20
ESD3V3U4ULC
Typical Characteristics at TA = 25 °C, unless otherwise specified
100
Scope: 6 GHz, 20 GS/s
80
VCL [V]
60
VCL-max-peak = 89 V
40
VCL-30ns-peak = 8 V
20
0
-20
Figure 8
0
100
200
300
tp [ns]
400
500
600
Clamping voltage at +8 kV discharge according IEC61000-4-2 (R = 330 Ω, C = 150 pF)
20
Scope: 6 GHz, 20 GS/s
0
VCL [V]
-20
-40
VCL-max-peak = -86 V
-60
VCL-30ns-peak = -6 V
-80
-100
Figure 9
0
100
200
tp [ns]
300
400
Clamping voltage at -8 kV discharge according IEC61000-4-2 (R = 330 Ω, C = 150 pF)
Final Data Sheet
12
Rev. 1.6, 2013-02-20
ESD3V3U4ULC
Typical Characteristics at TA = 25 °C, unless otherwise specified
150
Scope: 6 GHz, 20 GS/s
125
100
VCL [V]
75
VCL-max-peak = 124 V
50
VCL-30ns-peak = 12 V
25
0
-25
-50
Figure 10
0
100
200
tp [ns]
300
400
Clamping voltage at +15 kV discharge according IEC61000-4-2 (R = 330 Ohm, C = 150 pF)
50
Scope: 6 GHz, 20 GS/s
25
0
VCL [V]
-25
-50
-75
VCL-max-peak = -121 V
-100
VCL-30ns-peak = -9 V
-125
-150
Figure 11
0
100
200
tp [ns]
300
400
Clamping voltage at -15 kV discharge according IEC61000-4-2 (R = 330 Ω, C = 150 pF)
Final Data Sheet
13
Rev. 1.6, 2013-02-20
ESD3V3U4ULC
Application Information
4
Application Information
To design USB3.0 link for best system level ESD performance and error free Signal Integrity is mandatory.
To bring both requirements together, the ESD protection devices has to provide excellent ESD and a very low
device capacitance. The Infineon ESD3V3U4ULC in “array” configuration, combined with a clear and straight
forward “full through” layout fulfills these requirements in the best way.
TVS ESD diodes
TX+
TX+
TX+
+
-
SuperSpeed
Data IN
RXTX-
USB3.0: SS-Hub
e.g. PC
TXmated
connector
+ RX+
RX-
SuperSpeed
Data OUT
+
-
TXUSB3.0 cable
SS transmission
channel
RX+
SuperSpeed
Data OUT
RX+
mated
connector
USB3.0: SS-Device
e.g. storage
RX+
TX+
TX-
RX-
+
-
SuperSpeed
Data IN
RX-
TVS ESD diodes
Figure 12
USB3.0 structure with ESD protection devices [3]
Final Data Sheet
14
Rev. 1.6, 2013-02-20
ESD3V3U4ULC
Ordering Information Scheme
5
ESD
Ordering Information Scheme
0P1
RF
- XX YY
Package
XX = Pin number (i.e.: 02 = 2 pins; 03 = 3 pins)
YY = Package family:
LS = TSSLP
LRH = TSLP
For Radio Frequency Applications
Line Capacitance C L in pF: (i.e.: 0P1 = 0.1pF)
ESD 5V3 U n U - XX YY
Package or Application
XX = Pin number (i.e.: 02 = 2 pins; 03 = 3 pins)
YY = Package family:
LS = TSSLP
LRH = TSLP
S = SOT363
U = SC74
XX = Application family:
LC = Low Clamp
HDMI
Uni- / Bi-directional or Rail to Rail protection
Number of protected lines (i.e.: 1 = 1 line; 4 = 4 lines)
Capacitance: Standard (>10pF), Low (<10pF), Ultra-low (<1pF)
Maximum working voltage VRWM in V: (i.e.: 5V3 = 5.3V)
Figure 13
Ordering information scheme
Final Data Sheet
15
Rev. 1.6, 2013-02-20
ESD3V3U4ULC
Package Information
6
Package Information
6.1
TSLP-9-1 (mm)
Bottom view
1±0.035
A
(0.03)
0.59
5
6
0.5
B
7
4
0.94 ±0.025 1)
3
2
0.05 A B
0.4 ±0.025 1)
0.05 A B
4 x 0.5 = 2
(0.05)
0.05 MAX.
0.05 A B
8
1
9
Pin 1 marking
8 x 0.35 ±0.025 1)
0.05 A B
1) Dimension applies to plated terminals
TSLP-9-1-PO V02
TSLP-9-1: Package overview
1
0.3
0.2
0.3
0.38
0.3
0.38
0.38
0.38
0.2
0.2
0.3
2.3
0.3
0.2
0.3
0.3
0.3
0.3
0.2
2.3
0.2
0.3
0.2
1
0.2
Figure 14
2.3 ±0.035
0.31+0.01
-0.02
8 x 0.2 ±0.025 1)
Top view
0.24
0.24
Copper
Stencil apertures
Solder mask
TSLP-9-1-FP V01
Figure 15
TSLP-9-1: Footprint
0.5
8
2.3
4
Pin 1
marking
Figure 16
1.6
TSLP-9-1-TP V03
TSLP-9-1: Packing
1234567
Type code
Data code (YYWW)
Pin 1 marking
TSLP-9-1-MK V02
Figure 17
TSLP-9-1: Marking
Final Data Sheet
16
Rev. 1.6, 2013-02-20
ESD3V3U4ULC
References
References
[1]
On-chip ESD protection for integrated circuits, Albert Z. H. Wang, ISBN:0-7923-7647-1
[2]
Infineon Technologie AG - Application Note AN210: Effective ESD Protection Design at System Level
Using VF-TLP Characterization Methodology
[3]
Infineon Technologie AG - Application Note AN240: Effective ESD Protection for USB3.0, combined with
perfect Signal Intergrity.
Final Data Sheet
17
Rev. 1.6, 2013-02-20
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Published by Infineon Technologies AG
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