DATASHEET

ISL8487, ISL81483, ISL81487
Data Sheet
March 14, 2016
1/8 Unit Load, 5V, Low Power, High Speed
or Slew Rate Limited, RS-485/RS-422
Transceivers
FN6050.8
Features
• Fractional Unit Load Allows up to 256 Devices on the Bus
• Specified for 10% Tolerance Supplies
These Intersil RS-485/RS-422 devices are “fractional” unit
load (UL), BiCMOS, 5V powered, single transceivers that
meet both the RS-485 and RS-422 standards for balanced
communication. Unlike competitive devices, this Intersil
family is specified for 10% tolerance supplies (4.5V to 5.5V).
• Class 3 ESD Protection (HBM) on all Pins. . . . . . . . >7kV
• High Data Rate Version (ISL81487) . . . . . . . up to 5Mbps
• Slew Rate Limited Versions for Error Free Data
Transmission (ISL8487, ISL81483) . . . . . . .up to 250kbps
The ISL81483 and ISL81487 present a 1/8 unit load to the
RS-485 bus, which allows up to 256 transceivers on the
network for large node count systems (e.g., process
automation, remote meter reading systems). The 1/4 UL
ISL8487 allows up to 128 transceivers on the bus. In a
remote utility meter reading system, individual (apartments
for example) utility meter readings are routed to a
concentrator via an RS-485 network, so the high allowed
node count minimizes the number of repeaters required to
network all the meters. Data for all meters is then read out
from the concentrator via a single access port, or a wireless
link.
• Low Current Shutdown Mode (Except ISL81487) . . 0.5A
• Low Quiescent Supply Current:
- ISL8487, ISL81483. . . . . . . . . . . . . . . . . . 145A (Max.)
- ISL81487 . . . . . . . . . . . . . . . . . . . . . . . . . 420A (Max.)
• -7V to +12V Common Mode Input Voltage Range
• Three State Rx and Tx Outputs
• 30ns Propagation Delays, 5ns Skew (ISL81487)
• Half Duplex Pinouts
• Operate from a Single +5V Supply (10% Tolerance)
Slew rate limited drivers on the ISL8487 and ISL81483
reduce EMI, and minimize reflections from improperly
terminated transmission lines, or unterminated stubs in
multidrop and multipoint applications. Data rates up to
250kbps are achievable with these devices.
• Current Limiting and Thermal Shutdown for Driver
Overload Protection
• Drop-In Replacements for: MAX487 (ISL8487); MAX1483
(ISL81483); MAX1487, LMS1487 (ISL81487)
• Pb-Free Plus Anneal Available (RoHS Compliant)
Data rates up to 5Mbps are achievable by using the
ISL81487, which features higher slew rates.
Applications
Receiver (Rx) inputs feature a “fail-safe if open” design,
which ensures a logic high Rx output if Rx inputs are floating.
• High Node Count Networks
Driver (Tx) outputs are short circuit protected, even for
voltages exceeding the power supply voltage. Additionally,
on-chip thermal shutdown circuitry disables the Tx outputs to
prevent damage if power dissipation becomes excessive.
• Factory Automation
These half duplex devices multiplex the Rx inputs and Tx
outputs to allow transceivers with Rx and Tx disable
functions in 8 lead packages.
• Industrial/Process Control Networks
• Automated Utility Meter Reading Systems
• Security Networks
• Building Environmental Control Systems
TABLE 1. SUMMARY OF FEATURES
PART
NUMBER
HALF/FULL
NO. OF DEVICES DATA RATE SLEW-RATE
DUPLEX
ALLOWED ON BUS
(Mbps)
LIMITED?
RECEIVER/
DRIVER
ENABLE?
QUIESCENT
ICC (A)
LOW POWER
SHUTDOWN?
PIN
COUNT
ISL8487
(No longer
available or
supported)
Half
128
0.25
Yes
Yes
120
Yes
8
ISL81483
Half
256
0.25
Yes
Yes
120
Yes
8
ISL81487
Half
256
5
No
Yes
350
No
8
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas LLC 2004, 2006, 2016. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL8487, ISL81483, ISL81487
Pinout
Truth Tables
ISL8487, ISL81483, ISL81487 (PDIP, SOIC)
TOP VIEW
RO 1
8
R
TRANSMITTING
INPUTS
OUTPUTS
VCC
RE
DE
DI
Z
Y
1
1
0
1
RE 2
7
B/Z
X
DE 3
6
A/Y
X
1
0
1
0
5
GND
0
0
X
High-Z
High-Z
1
0
X
High-Z *
High-Z *
DI 4
D
*Shutdown Mode for ISL8487, ISL81483 (see Note 7)
RECEIVING
INPUTS
OUTPUT
RE
DE
A-B
RO
0
0
 +0.2V
1
0
0
 -0.2V
0
0
0
Inputs Open
1
1
0
X
High-Z *
1
1
X
High-Z
*Shutdown Mode for ISL8487, ISL81483 (see Note 7)
Ordering Information
PART NO.
PART MARKING
TEMP. RANGE (°C)
PACKAGE
PKG. DWG. #
ISL8487IBZ (Note) (No longer
available, recommended
replacement ISL8487EIBZ)
8487IBZ
-40 to 85
8 Ld SOIC* (Pb-free)
M8.15
ISL8487IPZ (Note) (No longer
available, recommended
replacement ISL8487EIPZ)
8487IPZ
-40 to 85
8 Ld PDIP** (Pb-free)
E8.3
ISL81483IBZ (Note)
81483IBZ
-40 to 85
8 Ld SOIC* (Pb-free)
M8.15
ISL81483IPZ (Note)
81483IPZ
-40 to 85
8 Ld PDIP** (Pb-free)
E8.3
ISL81487IBZ (Note)
81487IBZ
-40 to 85
8 Ld SOIC* (Pb-free)
M8.15
*SOIC also available in Tape and Reel; Add “-T” to suffix.
**Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish,
which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2
FN6050.8
March 14, 2016
ISL8487, ISL81483, ISL81487
Pin Descriptions
PIN
FUNCTION
RO
Receiver output: If A > B by at least 0.2V, RO is high; If A < B by 0.2V or more, RO is low; RO = High if A and B are unconnected (floating).
RE
Receiver output enable. RO is enabled when RE is low; RO is high impedance when RE is high.
DE
Driver output enable. The driver outputs, Y and Z, are enabled by bringing DE high. They are high impedance when DE is low.
DI
Driver input. A low on DI forces output Y low and output Z high. Similarly, a high on DI forces output Y high and output Z low.
GND
Ground connection.
A/Y
RS-485/422 level, noninverting receiver input and noninverting driver output. Pin is an input (A) if DE = 0; pin is an output (Y) if DE = 1.
B/Z
RS-485/422 level, inverting receiver input and inverting driver output. Pin is an input (B) if DE = 0; pin is an output (Z) if DE = 1.
VCC
System power supply input (4.5V to 5.5V).
Typical Operating Circuits
ISL8487, ISL81483, ISL81487
+5V
+5V
+
8
0.1F
0.1F
+
8
VCC
1 RO
R
D
2 RE
B/Z
A/Y
3 DE
4 DI
VCC
7
6
RT
RT
7
B/Z
DE 3
6
A/Y
RE 2
R
D
GND
GND
5
5
3
DI 4
RO 1
FN6050.8
March 14, 2016
ISL8487, ISL81483, ISL81487
Absolute Maximum Ratings
Thermal Information
VCC to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V
Input Voltages
DI, DE, RE . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to (VCC +0.5V)
Input/Output Voltages
A/Y, B/Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -8V to +12.5V
RO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to (VCC +0.5V)
Short Circuit Duration
Y, Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous
ESD Rating
HBM (Per MIL-STD-883, Method 3015.7) . . . . . . . . . . . . . . >7kV
Thermal Resistance (Typical, Note 1)
JA (°C/W)
8 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . .
170
8 Ld PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . .
140
Maximum Junction Temperature (Plastic Package) . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
(SOIC - Lead Tips Only)
*Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.
Operating Conditions
Temperature Range
ISL8XXXIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
Test Conditions: VCC = 4.5V to 5.5V; Unless Otherwise Specified. Typicals are at VCC = 5V, TA = 25°C,
(Note 2)
PARAMETER
SYMBOL
TEST CONDITIONS
TEMP
(°C)
MIN
TYP
MAX
UNITS
Full
-
-
VCC
V
Full
2
3
-
V
DC CHARACTERISTICS
Driver Differential VOUT (no load)
VOD1
Driver Differential VOUT (with load)
VOD2
R = 27 (RS-485), (Figure 1)
Full
1.5
2.3
5
V
Change in Magnitude of Driver
Differential VOUT for
Complementary Output States
VOD
R = 27 or 50, (Figure 1)
Full
-
0.01
0.2
V
VOC
R = 27 or 50, (Figure 1)
Full
-
-
3
V
VOC
R = 27 or 50, (Figure 1)
Full
-
0.01
0.2
V
Driver Common-Mode VOUT
Change in Magnitude of Driver
Common-Mode VOUT for
Complementary Output States
R = 50 (RS-422), (Figure 1)
Logic Input High Voltage
VIH
DE, DI, RE
Full
2
-
-
V
Logic Input Low Voltage
VIL
DE, DI, RE
Full
-
-
0.8
V
Logic Input Current
IIN1
DE, DI, RE
Full
-2
-
2
A
Input Current (A/Y, B/Z), (Note 10)
(ISL81483, ISL81487)
IIN2
DE = 0V, VCC = 4.5 to
5.5V
VIN = 12V
Full
-
-
140
A
VIN = -7V
Full
-
-
-120
A
IIN2
DE = 0V, VCC = 0V
VIN = 12V
Full
-
-
180
A
VIN = -7V
Full
-
-
-100
A
VIN = 12V
Full
-
-
250
A
VIN = -7V
Full
-
-
-100
A
Full
-0.2
-
0.2
V
Input Current (A/Y, B/Z), (Note 11)
(ISL8487 Only)
IIN2
DE = 0V, VCC = 0V, or
4.5 to 5.5V
Receiver Differential Threshold
Voltage
VTH
-7V  VCM  12V
Receiver Input Hysteresis
VTH
VCM = 0V
25
-
70
-
mV
Receiver Output High Voltage
VOH
IO = -4mA, VID = 200mV
Full
3.5
-
-
V
Receiver Output Low Voltage
VOL
IO = -4mA, VID = 200mV
Full
-
-
0.4
V
Three-State (high impedance)
Receiver Output Current
IOZR
0.4V  VO  2.4V
Full
-
-
1
A
4
FN6050.8
March 14, 2016
ISL8487, ISL81483, ISL81487
Electrical Specifications
Test Conditions: VCC = 4.5V to 5.5V; Unless Otherwise Specified. Typicals are at VCC = 5V, TA = 25°C,
(Note 2) (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
TEMP
(°C)
MIN
TYP
MAX
UNITS
Full
96
-
-
k
Receiver Input Resistance
RIN
-7V  VCM  12V
ISL81483, ISL81487
ISL8487
Full
48
-
-
k
No-Load Supply Current, (Note 3)
ICC
ISL81487, DI, RE = 0V
or VCC
DE = VCC
Full
-
400
500
A
DE = 0V
Full
-
350
420
A
DE = VCC
Full
-
160
200
A
DE = 0V
ISL8487, ISL81483, DI,
RE = 0V or VCC
Full
-
120
145
A
Shutdown Supply Current
ISHDN
(Note 7), DE = 0V, RE = VCC, DI = 0V or VCC
Full
-
0.5
8
A
Driver Short-Circuit Current,
VO = High or Low
IOSD1
DE = VCC, -7V  VY or VZ  12V, (Note 4)
Full
35
-
250
mA
Receiver Short-Circuit Current
IOSR
0V  VO  VCC
Full
7
-
85
mA
tPLH, tPHL
RDIFF = 54, CL = 100pF, (Figure 2)
Full
15
24
50
ns
tSKEW
RDIFF = 54, CL = 100pF, (Figure 2)
Full
-
2
10
ns
tR, tF
RDIFF = 54, CL = 100pF, (Figure 2)
Full
3
12
25
ns
SWITCHING CHARACTERISTICS (ISL81487)
Driver Input to Output Delay
Driver Output Skew
Driver Differential Rise or Fall Time
Driver Enable to Output High
tZH
CL = 100pF, SW = GND, (Figure 3)
Full
-
14
70
ns
Driver Enable to Output Low
tZL
CL = 100pF, SW = VCC, (Figure 3)
Full
-
14
70
ns
Driver Disable from Output High
tHZ
CL = 15pF, SW = GND, (Figure 3)
Full
-
44
70
ns
Driver Disable from Output Low
tLZ
CL = 15pF, SW = VCC, (Figure 3)
Full
-
21
70
ns
Receiver Input to Output Delay
tPLH, tPHL
(Figure 4)
Full
30
90
150
ns
tSKD
(Figure 4)
25
-
5
-
ns
Receiver Skew | tPLH - tPHL |
Receiver Enable to Output High
tZH
CL = 15pF, SW = GND, (Figure 5)
Full
-
9
50
ns
Receiver Enable to Output Low
tZL
CL = 15pF, SW = VCC, (Figure 5)
Full
-
9
50
ns
Receiver Disable from Output High
tHZ
CL = 15pF, SW = GND, (Figure 5)
Full
-
9
50
ns
Receiver Disable from Output Low
tLZ
CL = 15pF, SW = VCC, (Figure 5)
Full
-
9
50
ns
Full
5
-
-
Mbps
Maximum Data Rate
fMAX
SWITCHING CHARACTERISTICS (ISL8487, ISL81483)
Driver Input to Output Delay
Driver Output Skew
tPLH, tPHL
RDIFF = 54, CL = 100pF, (Figure 2)
Full
250
650
2000
ns
tSKEW
RDIFF = 54, CL = 100pF, (Figure 2)
Full
-
160
800
ns
tR, tF
RDIFF = 54, CL = 100pF, (Figure 2)
Full
250
900
2000
ns
Driver Enable to Output High
tZH
CL = 100pF, SW = GND, (Figure 3, Note 5)
Full
250
1000
2000
ns
Driver Enable to Output Low
tZL
CL = 100pF, SW = VCC, (Figure 3, Note 5)
Full
250
860
2000
ns
Driver Disable from Output High
tHZ
CL = 15pF, SW = GND, (Figure 3)
Full
300
660
3000
ns
Driver Disable from Output Low
tLZ
CL = 15pF, SW = VCC, (Figure 3)
Full
300
640
3000
ns
Receiver Input to Output Delay
tPLH, tPHL
(Figure 4)
Full
250
500
2000
ns
tSKD
(Figure 4)
25
-
60
-
ns
tZH
CL = 15pF, SW = GND, (Figure 5, Note 6)
Full
-
10
50
ns
Receiver Enable to Output Low
tZL
CL = 15pF, SW = VCC, (Figure 5, Note 6)
Full
-
10
50
ns
Receiver Disable from Output High
tHZ
CL = 15pF, SW = GND, (Figure 5)
Full
-
10
50
ns
Receiver Disable from Output Low
tLZ
CL = 15pF, SW = VCC, (Figure 5)
Full
-
10
50
ns
Full
250
-
-
kbps
Full
50
120
600
ns
Driver Differential Rise or Fall Time
Receiver Skew | tPLH - tPHL |
Receiver Enable to Output High
Maximum Data Rate
fMAX
Time to Shutdown
tSHDN
5
(Note 7)
FN6050.8
March 14, 2016
ISL8487, ISL81483, ISL81487
Electrical Specifications
Test Conditions: VCC = 4.5V to 5.5V; Unless Otherwise Specified. Typicals are at VCC = 5V, TA = 25°C,
(Note 2) (Continued)
SYMBOL
TEST CONDITIONS
TEMP
(°C)
MIN
TYP
MAX
UNITS
Driver Enable from Shutdown to
Output High
tZH(SHDN)
CL = 100pF, SW = GND, (Figure 3, Notes 7, 8)
Full
-
1000
2000
ns
Driver Enable from Shutdown to
Output Low
tZL(SHDN)
CL = 100pF, SW = VCC, (Figure 3, Notes 7, 8)
Full
-
1000
2000
ns
Receiver Enable from Shutdown to
Output High
tZH(SHDN)
CL = 15pF, SW = GND, (Figure 5, Notes 7, 9)
Full
-
800
2500
ns
Receiver Enable from Shutdown to
Output Low
tZL(SHDN)
CL = 15pF, SW = VCC, (Figure 5, Notes 7, 9)
Full
-
800
2500
ns
PARAMETER
NOTES:
2. All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless
otherwise specified.
3. Supply current specification is valid for loaded drivers when DE = 0V.
4. Applies to peak current. See “Typical Performance Curves” for more information.
5. When testing the ISL8487 and ISL81483, keep RE = 0 to prevent the device from entering SHDN.
6. When testing the ISL8487 and ISL81483, the RE signal high time must be short enough (typically <200ns) to prevent the device from entering
SHDN.
7. The ISL8487 and ISL81483 are put into shutdown by bringing RE high and DE low. If the inputs are in this state for less than 50ns, the parts are
guaranteed not to enter shutdown. If the inputs are in this state for at least 600ns, the parts are guaranteed to have entered shutdown. See
“Low-Power Shutdown Mode” section.
8. Keep RE = VCC, and set the DE signal low time >600ns to ensure that the device enters SHDN.
9. Set the RE signal high time >600ns to ensure that the device enters SHDN.
10. Devices meeting these limits are denoted as “1/8 unit load (1/8 UL)” transceivers. The RS-485 standard allows up to 32 Unit Loads on the bus,
so there can be 256 1/8 UL devices on a bus.
11. Devices meeting these limits are denoted as “1/4 unit load (1/4 UL)” transceivers. The RS-485 standard allows up to 32 Unit Loads on the bus,
so there can be 128 1/4 UL devices on a bus.
Test Circuits and Waveforms
VCC
R
DE
DI
Z
VOD
D
Y
R
VOC
FIGURE 1. DRIVER VOD AND VOC
6
FN6050.8
March 14, 2016
ISL8487, ISL81483, ISL81487
Test Circuits and Waveforms (Continued)
3V
DI
1.5V
1.5V
0V
tPLH
tPHL
VOH
VCC
CL = 100pF
DE
50%
OUT (Y)
50%
VOL
Z
DI
tPLH
tPHL
RDIFF
D
Y
VOH
CL = 100pF
OUT (Z)
SIGNAL
GENERATOR
50%
50%
VOL
90%
DIFF OUT (Y - Z)
+VOD
90%
10%
10%
tR
-VOD
tF
SKEW = |tPLH (Y or Z) - tPHL (Z or Y)|
FIGURE 2A. TEST CIRCUIT
FIGURE 2B. MEASUREMENT POINTS
FIGURE 2. DRIVER PROPAGATION DELAY AND DIFFERENTIAL TRANSITION TIMES
DE
Z
DI
500
VCC
D
SIGNAL
GENERATOR
SW
Y
3V
GND
DE
CL
1.5V
NOTE 7
1.5V
0V
tZH, tZH(SHDN)
(SHDN) for ISL8487 and ISL81483 only.
PARAMETER OUTPUT
RE
DI
SW
CL (pF)
tHZ
Y/Z
X
1/0
GND
15
tLZ
Y/Z
X
0/1
VCC
15
tZH
Y/Z
0 (Note 5)
1/0
GND
100
tZL
Y/Z
tZH(SHDN)
Y/Z
1 (Note 7)
1/0
GND
100
tZL(SHDN)
Y/Z
1 (Note 7)
0/1
VCC
100
0 (Note 5)
OUTPUT HIGH
NOTE 7
0/1
VCC
tHZ
VOH - 0.5V
OUT (Y, Z)
VOH
2.3V
0V
tZL, tZL(SHDN)
tLZ
NOTE 7
100
VCC
OUT (Y, Z)
2.3V
OUTPUT LOW
FIGURE 3A. TEST CIRCUIT
VOL + 0.5V V
OL
FIGURE 3B. MEASUREMENT POINTS
FIGURE 3. DRIVER ENABLE AND DISABLE TIMES
RE
+1.5V
15pF
B
A
R
RO
3V
A
1.5V
1.5V
0V
tPLH
tPHL
VCC
SIGNAL
GENERATOR
50%
RO
50%
0V
FIGURE 4A. TEST CIRCUIT
FIGURE 4B. MEASUREMENT POINTS
FIGURE 4. RECEIVER PROPAGATION DELAY
7
FN6050.8
March 14, 2016
ISL8487, ISL81483, ISL81487
Test Circuits and Waveforms (Continued)
RE
NOTE 7
B
RO
R
SIGNAL
GENERATOR
1k
A
15pF
VCC
SW
RE
3V
1.5V
GND
1.5V
0V
tZH, tZH(SHDN)
OUTPUT HIGH
NOTE 7
(SHDN) for ISL8487 and ISL81483 only.
PARAMETER
DE
A
SW
tHZ
0
+1.5V
GND
tLZ
0
-1.5V
VCC
tZH (Note 6)
0
+1.5V
GND
tZL (Note 6)
0
-1.5V
VCC
tZH(SHDN) (Note 7)
0
+1.5V
GND
tZL(SHDN) (Note 7)
0
-1.5V
VCC
FIGURE 5A. TEST CIRCUIT
tHZ
VOH - 0.5V
RO
VOH
1.5V
0V
tZL, tZL(SHDN)
NOTE 7
RO
tLZ
VCC
1.5V
OUTPUT LOW
VOL + 0.5V V
OL
FIGURE 5B. MEASUREMENT POINTS
FIGURE 5. RECEIVER ENABLE AND DISABLE TIMES
Application Information
RS-485 and RS-422 are differential (balanced) data
transmission standards for use in long haul or noisy
environments. RS-422 is a subset of RS-485, so RS-485
transceivers are also RS-422 compliant. RS-422 is a pointto-multipoint (multidrop) standard, which allows only one
driver and up to 10 (assuming one unit load devices)
receivers on each bus. RS-485 is a true multipoint standard,
which allows up to 32 one unit load devices (any
combination of drivers and receivers) on each bus. To allow
for multipoint operation, the RS-485 spec requires that
drivers must handle bus contention without sustaining any
damage.
Another important advantage of RS-485 is the extended
common mode range (CMR), which specifies that the driver
outputs and receiver inputs withstand signals that range from
+12V to -7V. RS-422 and RS-485 are intended for runs as
long as 4000’, so the wide CMR is necessary to handle
ground potential differences, as well as voltages induced in
the cable by external fields.
Receiver Features
These devices utilize a differential input receiver for maximum
noise immunity and common mode rejection. Input sensitivity
is 200mV, as required by the RS-422 and RS-485
specifications.
Receiver input resistance of 96k surpasses the RS-422
spec of 4k, and is eight times the RS-485 “Unit Load (UL)”
requirement of 12k minimum. Thus, these products are
known as “one-eighth UL” transceivers, and there can be up
to 256 of these devices on a network while still complying
with the RS-485 loading spec.
8
Receiver inputs function with common mode voltages as
great as 7V outside the power supplies (i.e., +12V and
-7V), making them ideal for long networks where induced
voltages are a realistic concern.
All the receivers include a “fail-safe if open” function that
guarantees a high level receiver output if the receiver inputs
are unconnected (floating).
Receivers easily meet the data rates supported by the
corresponding driver, and receiver outputs are three-statable
via the active low RE input.
Driver Features
The RS-485 and RS-422 driver is a differential output device
that delivers at least 1.5V across a 54 load (RS-485), and
at least 2V across a 100 load (RS-422). The drivers feature
low propagation delay skew to maximize bit width, and to
minimize EMI.
Driver outputs are three-statable via the active high DE
input.
The ISL8487 and ISL81483 driver outputs are slew rate
limited to minimize EMI, and to minimize reflections in
unterminated or improperly terminated networks. Data rate
on these slew rate limited versions is a maximum of
250kbps. ISL81487 drivers are not limited, so faster output
transition times allow data rates of at least 5Mbps.
Data Rate, Cables, and Terminations
RS-485 and RS-422 are intended for network lengths up to
4000’, but the maximum system data rate decreases as the
transmission length increases. Devices operating at 5Mbps
are limited to lengths less than a few hundred feet, while the
FN6050.8
March 14, 2016
ISL8487, ISL81483, ISL81487
250kbps versions can operate at full data rates with lengths
in excess of 1000’.
Twisted pair is the cable of choice for RS-485/RS-422
networks. Twisted pair cables tend to pick up noise and
other electromagnetically induced voltages as common
mode signals, which are effectively rejected by the
differential receivers in these ICs.
To minimize reflections, proper termination is imperative
when using the 5Mbps device. Short networks using the
250kbps versions need not be terminated, but, terminations
are recommended unless power dissipation is an overriding
concern.
In point-to-point, or point-to-multipoint (single driver on bus)
networks, the main cable should be terminated in its
characteristic impedance (typically 120) at the end farthest
from the driver. In multi-receiver applications, stubs
connecting receivers to the main cable should be kept as
short as possible. Multipoint (multi-driver) systems require
that the main cable be terminated in its characteristic
impedance at both ends. Stubs connecting a transceiver to
the main cable should be kept as short as possible.
Built-In Driver Overload Protection
As stated previously, the RS-485 spec requires that drivers
survive worst case bus contentions undamaged. These
devices meet this requirement via driver output short circuit
current limits, and on-chip thermal shutdown circuitry.
The driver output stages incorporate short circuit current
limiting circuitry which ensures that the output current never
In the event of a major short circuit condition, these devices
also include a thermal shutdown feature that disables the
drivers whenever the die temperature becomes excessive.
This eliminates the power dissipation, allowing the die to
cool. The drivers automatically re-enable after the die
temperature drops about 15 degrees. If the contention
persists, the thermal shutdown/re-enable cycle repeats until
the fault is cleared. Receivers stay operational during
thermal shutdown.
Low Power Shutdown Mode (Excluding ISL81487)
These CMOS transceivers all use a fraction of the power
required by their bipolar counterparts, but the ISL8487 and
ISL81483 include a shutdown feature that reduces the
already low quiescent ICC to a 500nA trickle. They enter
shutdown whenever the receiver and driver are
simultaneously disabled (RE = VCC and DE = GND) for a
period of at least 600ns. Disabling both the driver and the
receiver for less than 50ns guarantees that shutdown is not
entered.
Note that receiver and driver enable times increase when
enabling from shutdown. Refer to Notes 5-9, at the end of
the Electrical Specification table, for more information.
VCC = 5V, TA = 25°C, ISL8487, ISL81483 and ISL81487; Unless Otherwise Specified
90
3.6
80
3.4
DIFFERENTIAL OUTPUT VOLTAGE (V)
DRIVER OUTPUT CURRENT (mA)
Typical Performance Curves
exceeds the RS-485 spec, even at the common mode
voltage range extremes. Additionally, these devices utilize a
foldback circuit which reduces the short circuit current, and
thus the power dissipation, whenever the contending voltage
exceeds either supply.
70
60
50
40
30
20
10
0
0
1
2
3
4
DIFFERENTIAL OUTPUT VOLTAGE (V)
FIGURE 6. DRIVER OUTPUT CURRENT vs DIFFERENTIAL
OUTPUT VOLTAGE
9
5
3.2
RDIFF = 100
3
2.8
2.6
2.4
RDIFF = 54
2.2
2
-40
-25
0
25
50
75
85
TEMPERATURE (°C)
FIGURE 7. DRIVER DIFFERENTIAL OUTPUT VOLTAGE vs
TEMPERATURE
FN6050.8
March 14, 2016
ISL8487, ISL81483, ISL81487
Typical Performance Curves
VCC = 5V, TA = 25°C, ISL8487, ISL81483 and ISL81487; Unless Otherwise Specified (Continued)
400
160
ISL81487E, DE = VCC, RE = X
140
ISL81487E
120
ISL81487E, DE = GND, RE = X
80
ISL8487E, ISL81487L
300
60
40
ICC (µA)
OUTPUT CURRENT (mA)
350
Y OR Z = LOW
100
20
0
-20
200
Y OR Z = HIGH
-40
ISL8487E, ISL81487L, DE = VCC, RE = X
-60
ISL81487E
-80 ISL8487E, ISL81487L
-100
-120
-7 -6
-4
-2
250
150
ISL8487E, ISL81487L, DE = GND, RE = GND
0
2
4
6
OUTPUT VOLTAGE (V)
8
10
100
-40
12
FIGURE 8. DRIVER OUTPUT CURRENT vs SHORT CIRCUIT
VOLTAGE
0
25
TEMPERATURE (°C)
50
75
85
FIGURE 9. SUPPLY CURRENT vs TEMPERATURE
250
750
700
200
tPLHY
tPLHZ
650
|tPLHY - tPHLZ|
150
600
SKEW (ns)
PROPAGATION DELAY (ns)
-25
tPHLY
550
tPHLZ
50
500
450
-40
|tPHLY - tPLHZ|
100
|CROSS PT. OF Y & Z - CROSS PT. OF Y & Z|
-25
0
25
TEMPERATURE (°C)
50
75
0
-40
85
FIGURE 10. DRIVER PROPAGATION DELAY vs
TEMPERATURE (ISL8487, ISL81483)
-25
0
25
TEMPERATURE (°C)
50
75
85
FIGURE 11. DRIVER SKEW vs TEMPERATURE
(ISL8487, ISL81483)
30
5
4
|tPHLY - tPLHZ|
26
3
24
22
20
SKEW (ns)
PROPAGATION DELAY (ns)
28
tPLHY
tPHLZ
tPLHZ
|tPLHY - tPHLZ|
2
1
18
|CROSSING PT. OF Y & Z - CROSSING PT. OF Y & Z|
tPHLY
16
-40
-25
0
25
50
TEMPERATURE (°C)
FIGURE 12. DRIVER PROPAGATION DELAY vs
TEMPERATURE (ISL81487)
10
75
85
0
-40
-25
0
25
50
75
85
TEMPERATURE (°C)
FIGURE 13. DRIVER SKEW vs TEMPERATURE
(ISL81487)
FN6050.8
March 14, 2016
ISL8487, ISL81483, ISL81487
5
RO
0
3
2
DRIVER OUTPUT (V)
4
B/Z
A/Y
1
0
TIME (400ns/DIV)
5
0
5
RO
0
4
3
2
DRIVER INPUT (V)
RDIFF = 54, CL = 100pF
DI
B/Z
A/Y
1
0
TIME (20ns/DIV)
FIGURE 16. DRIVER AND RECEIVER WAVEFORMS,
LOW TO HIGH (ISL81487)
5
0
5
RO
0
4
3
2
A/Y
B/Z
1
0
TIME (400ns/DIV)
FIGURE 15. DRIVER AND RECEIVER WAVEFORMS,
HIGH TO LOW (ISL8487, ISL81483)
DRIVER OUTPUT (V)
DRIVER OUTPUT (V)
RECEIVER OUTPUT (V)
FIGURE 14. DRIVER AND RECEIVER WAVEFORMS,
LOW TO HIGH (ISL8487, ISL81483)
DI
DRIVER INPUT (V)
0
RDIFF = 54, CL = 100pF
RDIFF = 54, CL = 100pF
DI
5
0
5
RO
0
DRIVER INPUT (V)
DI
5
RECEIVER OUTPUT (V)
RDIFF = 54, CL = 100pF
DRIVER INPUT (V)
VCC = 5V, TA = 25°C, ISL8487, ISL81483 and ISL81487; Unless Otherwise Specified (Continued)
RECEIVER OUTPUT (V)
DRIVER OUTPUT (V)
RECEIVER OUTPUT (V)
Typical Performance Curves
4
3
2
A/Y
B/Z
1
0
TIME (20ns/DIV)
FIGURE 17. DRIVER AND RECEIVER WAVEFORMS,
HIGH TO LOW (ISL81487)
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
GND
TRANSISTOR COUNT:
518
PROCESS:
Si Gate CMOS
11
FN6050.8
March 14, 2016
ISL8487, ISL81483, ISL81487
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not
warranted. Please go to the web to make sure that you have the latest revision.
DATE
REVISION
CHANGE
March 14, 2016
FN6050.8
Added Rev History and About Intersil Verbiage.
Updated “Ordering Information” table on page 2.
Updated M8.15 to current revision. POD revision changes are as follows:
Note 1 "1982" to "1994
Changed in Typical Recommended Land Pattern the following:
2.41(0.095) to 2.20(0.087)
0.76 (0.030) to 0.60(0.023)
0.200 to 5.20(0.205)
Updated to new POD format by removing table and moving dimensions onto drawing and adding land
pattern.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
12
FN6050.8
March 14, 2016
ISL8487, ISL81483, ISL81487
Dual-In-Line Plastic Packages (PDIP)
E8.3 (JEDEC MS-001-BA ISSUE D)
N
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
1 2 3
INCHES
N/2
-B-
-AD
E
BASE
PLANE
-C-
SEATING
PLANE
A2
A
L
D1
e
B1
D1
A1
eC
B
0.010 (0.25) M
C A B S
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.210
-
5.33
4
A1
0.015
-
0.39
-
4
A2
0.115
0.195
2.93
4.95
-
B
0.014
0.022
0.356
0.558
-
C
L
B1
0.045
0.070
1.15
1.77
8, 10
eA
C
0.008
0.014
0.204
C
D
0.355
0.400
9.01
eB
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between
English and Metric dimensions, the inch dimensions control.
0.005
-
0.13
-
5
E
0.300
0.325
7.62
8.25
6
E1
0.240
0.280
6.10
7.11
5
e
0.100 BSC
eA
0.300 BSC
3. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication No. 95.
eB
-
L
0.115
5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).
6. E and eA are measured with the leads constrained to be perpendicular to datum -C- .
5
D1
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
4. Dimensions A, A1 and L are measured with the package seated
in JEDEC seating plane gauge GS-3.
0.355
10.16
N
8
2.54 BSC
7.62 BSC
0.430
-
0.150
2.93
8
6
10.92
7
3.81
4
9
Rev. 0 12/93
7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).
13
FN6050.8
March 14, 2016
ISL8487, ISL81483, ISL81487
Package Outline Drawing
M8.15
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 1/12
DETAIL "A"
1.27 (0.050)
0.40 (0.016)
INDEX
6.20 (0.244)
5.80 (0.228)
AREA
0.50 (0.20)
x 45°
0.25 (0.01)
4.00 (0.157)
3.80 (0.150)
1
2
8°
0°
3
0.25 (0.010)
0.19 (0.008)
SIDE VIEW “B”
TOP VIEW
2.20 (0.087)
SEATING PLANE
5.00 (0.197)
4.80 (0.189)
1.75 (0.069)
1.35 (0.053)
1
8
2
7
0.60 (0.023)
1.27 (0.050)
3
6
4
5
-C-
1.27 (0.050)
0.51(0.020)
0.33(0.013)
SIDE VIEW “A
0.25(0.010)
0.10(0.004)
5.20(0.205)
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensioning and tolerancing per ANSI Y14.5M-1994.
2. Package length does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
3. Package width does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
4. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
5. Terminal numbers are shown for reference only.
6. The lead width as measured 0.36mm (0.014 inch) or greater above the
seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch).
7. Controlling dimension: MILLIMETER. Converted inch dimensions are not
necessarily exact.
8. This outline conforms to JEDEC publication MS-012-AA ISSUE C.
14
FN6050.8
March 14, 2016
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