THCV213 -214_Rev2.30_E ® THCV213 and 214 LVDS SerDes transmitter and receiver General Description tern which expedites the link establishment. 214 has an indicator of its PLL status. THCV213 and 214 are designed to support pixel data transmission between the Host and Display. The chipset can transmit 18bit data and 4bit control data through only a single differential cable at a pixel clock frequency from 5MHz to 40MHz. By V-by-One® technologies, unique encoding scheme and proprietary CDR technique, a link synchronization is achieved without any external frequency reference such as a crystal oscillator. It drastically improves the cost and space of PCBs of a display system. THCV213 transmitter converts input data into a single LVDS serial data stream with the embedded clock. It supports pre-emphasis for a long cable transmission. 214 receiver extracts the clock from the embedded clock and transforms the serial data stream back into the parallel data. To confirm the reliability of the link, several functions are supported. THCV213 can transmit the SYNC pat- Features • Transmit 18bit data and 4bit control data via a single differential cable • • • • • • • • • Wide frequency range: 5MHz to 40MHz Support SYNC pattern and LOCK indicator Pre Emphasis mode Clock edge selectable Dual Display mode Power Down mode Low power single 3.3V CMOS design 48pin TQFP AEC-Q100 ESD Protection Block Diagram THCV213 RXIN- TXOUT2+ Output Buffer TXOUT1- D[17:0] Deserialize INIT PRBS Serializer DE SYNC[2:0] TXOUT1+ RXIN+ Input Buffer D[17:0] THCV214 DE SYNC[2:0] OE TXOUT2- PLL PLL & CDR CLKIN EDGE CLKOUT EDGE MOD[1:0] PRE[1:0] LOCKN DUAL PDWN PDWN Copyright©2013 THine Electronics, Inc. 1/18 THine Electronics, Inc. THCV213-214_Rev2.30_E Package Information PART TEMP. RANGE PACKAGE THCV213-1TTN 0 °C to 70 °C 48pin TQFP THCV214-1TTN 0 °C to 70 °C 48pin TQFP THCV213-5TTN -40 °C to 85 °C 48pin TQFP THCV214-5TTN -40 °C to 85 °C 48pin TQFP Pin Out 36 35 34 33 32 31 30 29 28 27 26 25 VDD D3 D2 D1 D0 GND DE SYNC0 SYNC1 SYNC2 VDD INIT 48Pin TQFP 37 38 39 40 41 42 43 44 45 46 47 48 24 23 22 21 20 19 18 17 16 15 14 13 THCV213 GND EDGE GND LVDSGND TXOUT1TXOUT1+ LVDSGND LVDSVDD TXOUT2TXOUT2+ PLLGND PLLVDD 36 35 34 33 32 31 30 29 28 27 26 25 LOCKN VDD SYNC2 SYNC1 SYNC0 DE GND GNDO D0 D1 D2 D3 D14 D15 D16 D17 GND CLKIN VDD PRBS DUAL PDWN PRE0 PRE1 1 2 3 4 5 6 7 8 9 10 11 12 D4 D5 D6 D7 D8 GND D9 D10 D11 D12 D13 VDD 37 38 39 40 41 42 43 44 45 46 47 48 24 23 22 21 20 19 18 17 16 15 14 13 THCV214 VDDO D4 D5 D6 D7 D8 GNDO D9 D10 D11 D12 D13 MOD1 MOD0 PDWN RESERVED0 VDDO CLKOUT GNDO D17 D16 D15 D14 VDDO 1 2 3 4 5 6 7 8 9 10 11 12 GND EDGE OE LVDSGND RXINRXIN+ LVDSGND LVDSVDD RESERVED1 RESERVED2 PLLGND PLLVDD Copyright©2013 THine Electronics, Inc. 2/18 THine Electronics, Inc. THCV213-214_Rev2.30_E Pin Description THCV213 Pin Description Pin Name Pin # type TXOUT1-, TXOUT1+ 20, 19 LVDSOUT Description LVDS output. LVDS output for Dual Display mode. TXOUT2-, TXOUT2+ 16, 15 LVDSOUT Identical to TXOUT1+/-. Hi-Z when Normal operation. 32~35, D0~D17 37~41, 43~47, IN Data input. Active if input DE=High 1~4 Sync input. SYNC2~SYNC0 27~29 IN Active if input DE =Low. Input sync data pulse must be wider than or equal to two input clock periods. DE 30 IN CLKIN 6 IN PDWN 10 IN EDGE 23 IN Data Enable (DE) input. Refer to Table2 for requirements. Clock input. 5 MHz to 40MHz. H: Normal operation. L: Power Down, TXOUT1+/-, (TXOUT2+/-) are Hi-Z. Input clock triggering edge select. H: Rise edge, L: Fall edge. Select the level of pre-emphasis. PRE0,PRE1 11, 12 IN PRE1 PRE0 Description L L w/o Pre-Emphasis L H w/ 25% Pre Emphasis H L w/ 50% Pre Emphasis H H w/ 100% Pre Emphasis H: Triggers SYNC pattern output fromTXOUT1+/- and INIT 25 IN (TXOUT2+/-), normally used in Shake Hand mode. L: Normal operation. H: Dual Display mode DUAL 9 IN Both TXOUT1-/+ and TXOUT2-/+ enabled. L: Normal operation Only TXOUT1-/+ enabled. Copyright©2013 THine Electronics, Inc. 3/18 THine Electronics, Inc. THCV213-214_Rev2.30_E Pin Name Pin # type Description H: Internal test pattern generator is enabled. Pseud-Random Bit Sequence (PRBS) is generated PRBS 8 IN and is fed into input data latches. Normally used for debug. L: Normal operation. VDD GND 7,26,36,48 5,22,24, 31,42, Power Power supply pins for digital circuitry. Power Ground pins for digital circuitry. LVDSVDD 17 Power Power supply pin for LVDS input. LVDSGND 18, 21 Power Ground pins for LVDS input. PLLVDD 13 Power Power supply pin for PLL circuitry. PLLGND 14 Power Ground pin for PLL circuitry. Copyright©2013 THine Electronics, Inc. 4/18 THine Electronics, Inc. THCV213-214_Rev2.30_E 214 Pin Description Pin Name Pin # type Description RXIN-, RXIN+ 41, 42 LVDSIN LVDS input. OUT Data outputs. 8~11, D17~D0 13~17, 19~23, 25~28 SYNC0~SYNC2 32~34 OUT Sync output. DE 31 OUT Data Enable (DE) output. CLKOUT 6 OUT Clock output. Lock detect output. LOCKN 36 OUT H: Unlock, L: Lock. Can be used as an input signal detector, too. H: Normal operation. PDWN 3 IN EDGE 38 IN L: Power Down, all outputs except LOCKN and CLKOUT are held low. Refer to Fig9 for details(Note1.) Output clock triggering edge select. H: Rise edge, L: Fall edge. Output Enable. OE 39 IN (DE, SYNC0~SYNC2, D0~D17,CLKOUT) H: Output disabled, all outputs are Hi-Z. L: Output enabled. (Note1) Select operation mode Both must be tied to GND. MOD1, MOD0 1, 2 IN MOD0 MOD1 L L Normal Mode Shake Hand Mode Others Not Available RESERVED0 4 IN Must be tied to GND. RESERVED1 45 IN Must be tied to LVDSGND. RESERVED2 46 IN Must be tied to LVDSGND. VDD 35 Power Power supply pin for digital circuitry. GND 30,37 Power Ground pins for digital circuitry. LVDSVDD 44 Power Power supply pin for LVDS input. LVDSGND 40,43 Power Ground pins for LVDS input. PLLVDD 48 Power Power supply pin for PLL circuitry. PLLGND 47 Power Ground pin for PLL circuitry. VDDO 5,12,24 Power Power supply pins for TTL output. GNDO 7,18,29 Power Ground pins for TTL output. Note1: The state of outputs determined by the combination of OE and PDWN is as follow Copyright©2013 THine Electronics, Inc. 5/18 THine Electronics, Inc. THCV213-214_Rev2.30_E Table 1 Output State determined by OE and PDWN OE PDWN L H Output State Normal Operation. All outputs except LOCKN and CLKOUT are held low. L L LOCKN is held high while CLKOUT is driven high when EDGE input is high and is driven low when EDGE input is low. H H All outputs are Hi-Z. H L All outputs are Hi-Z. Table 2 Requirements for DE input Operation Mode DE = High DE = Low Min. 2tTCIP (See Fig5 for tTCIP) Normal Max. ShakeHand Min. 50 tTCIP (See Fig5 for tTCIP) 80 μsec Min. 2tTCIP (See Fig5 for tTCIP) Min. 2tTCIP (See Fig5 for tTCIP) Absolute Maximum Ratings Supply Voltage (VDD) -0.3V ~ +4.0V CMOS/TTL Input Voltage -0.3V ~ (VDD + 0.3V) CMOS/TTL Output Voltage -0.3V ~ (VDD + 0.3V) LVDS Receiver Input Voltage -0.3V ~ (VDD + 0.3V) Output Current -30mA ~ 30mA Junction Temperature +125 °C Storage Temperature Range -55 °C ~ +125 °C Reflow Peak Temperature / Time +260 °C / 10sec. Maximum Power Dissipation @+25 °C 1.9W ESD Protection AEC-Q100-002(HBM) +/-2kV ESD Protection AEC-Q100-003(MM) +/-200V ESD Protection AEC-Q100-011(CDM) +/-500V(Corner.750) Operation Condition Parameter All Supply Voltage Operating Ambient Temperature Copyright©2013 THine Electronics, Inc. Consumer Industrial Min. Typ. Max. Min. Typ. Max. Units 3.0 3.3 3.6 3.0 3.3 3.6 V 70 -40 85 °C 0 6/18 THine Electronics, Inc. THCV213-214_Rev2.30_E Electrical Characteristics CMOS/TTL DC Specifications Transmitter: VDD=VDD=LVDSVDD=PLLVDD, Receiver: VDD=VDD=VDDO=LVDSVDD=PLLVDD Symbol Parameter Conditions Min. Typ. Max. Units VIH High Level Input Voltage 2.0 VDD V VIL Low Level Input Voltage GND 0.8 V VOH High Level Output Voltage VOL Low Level Output Voltage IIIL Input Leak Current VDD= 3.0V ~ 3.6V 2.4 IOH = -4mA V VDD = 3.0V ~ 3.6V IOL = 4mA 0V ≤ V IN ≤ V CC 0.4 V ± 10 μΑ THCV213 DC Specifications VDD=VDD=LVDSVDD=PLLVDD Symbol Parameter Conditions Min. Typ. Max. Units 250 350 450 mV 35 mV 1.375 V VOD Differential Output Voltage RL=100Ω, PRE<1:0>=L,L ΔVOD Change in VOD between complementary output states RL=100Ω, PRE<1:0>=L,L Common Mode Voltage RL=100Ω, PRE<1:0>=L,L ΔVOC Change in VOC between complementary output states RL=100Ω, PRE<1:0>=L,L 35 mV IOS Output Short Circuit Current VOUT=0V,RL=100Ω 24 mA IOZ Output TRI-STATE Current ± 10 μΑ VOC 1.125 1.25 PDWN=L, VOUT=0V to VDD 214 DC Specifications VDD=VDD=VDDO=LVDSVDD=PLLVDD Symbol Parameter VTH Differential Input High Threshold VTL Differential Input Low Threshold IILD Differential Input Leakage Current Copyright©2013 THine Electronics, Inc. Conditions VIC = +1.2V VIN = +2.4V/0V VDD = 3.6V 7/18 Min. Typ. Max. Units 100 mV -100 mV ± 10 μΑ THine Electronics, Inc. THCV213-214_Rev2.30_E THCV213 Supply Current VDD=VDD=LVDSVDD=PLLVDD Symbol ITCCW1 ITCCW2 ITCCS Parameter Condition Transmitter Supply Current Normal Operation (Worst Case Pattern) fCLKIN =40MHz (Fig. 1) VDD=3.3V Transmitter Supply Current Dual Display Mode (Worst Case Pattern) fCLKIN =40MHz (Fig. 1) VDD=3.3V Transmitter Power Down Supply Current PDWN = L Typ. Max. Units 60 mA 90 mA 10 μΑ 214 Supply Current VDD=VDD=VDDO=LVDSVDD=PLLVDD Symbol IRCCW IRCCS Parameter Condition Receiver Supply Current fCLKOUT = 40MHz (Worst Case Pattern) VDD=3.3V (Fig. 1) CL=8pF (Fig. 4) Receiver Power Down Typ. Max. Units 70 mA 10 μA PDWN = L Supply Current Worst Case Pattern Stop LVDS Start Stop Even Even Even Start Even Even Even Stop Start Vdiff Odd Odd Odd Odd Odd Odd TTL CLKIN,CLKOUT Solid line: EDGE=”HIGH” Dashed line: EDGE=”LOW” D<even> D<odd> Fig. 1 Test Pattern Copyright©2013 THine Electronics, Inc. 8/18 THine Electronics, Inc. THCV213-214_Rev2.30_E Switching Characteristics THCV213 Switching Characteristics VDD=VDD=LVDSVDD=PLLVDD Symbol Parameter Min. Typ. Max. Units 200 ns tTCIP CLKIN Period (Fig. 5) tTCP TXOUT Period (Fig. 5) tTCH CLKIN High Time (Fig. 5) 0.35tTCIP 0.5tTCIP 0.65tTCIP ns tTCL CLKIN Low Time (Fig. 5) 0.35tTCIP 0.5tTCIP 0.65tTCIP ns tTS TTL Data Setup to CLKIN (Fig. 5) 5 ns tTH TTL Data Hold from CKLIN (Fig. 5) 0 ns tTO CLK IN to TXOUT+/- Delay (Fig. 5) tTLH 25 tTCIP . 3 17 ------ t TCIP + 7 21 ns TTL Input Low to High Transition Time (Fig. 2) 3.0 5.0 ns tTHL TTL Input High to Low Transition Time (Fig. 2) 3.0 5.0 ns tTLVT LVDS Differential Output Transition Time (Fig. 3) 0.6 1.5 ns tTPLL Phase Lock Loop Set Time (Fig. 7) 10.0 ms tTHZ PDWN Low to Output Hi-Z Set Delay (Fig. 7) tTSYNC1 INIT High to Sync Pattern Output Delay (Fig. 8) tTSYNC2 INIT Low to Normal Pattern Output Delay (Fig. 8) Copyright©2013 THine Electronics, Inc. 3 17 ------ t TCIP 21 ns 3.6 ns 17 ------ t TCIP + 3 21 ns 17 1026 ------ t TCIP + 3 21 9/18 ns THine Electronics, Inc. THCV213-214_Rev2.30_E 214 Switching Characteristics VDD=VDD=VDDO=LVDSVDD=PLLVDD Symbol Parameter Min. Typ. Max. Units 200 ns tRCIP RXIN Period (Fig. 6) tRCP CLKOUT Period (Fig. 6) tRCIP ns tRCH CLKOUT High Time (Fig. 6) t RCP ---------2 ns tRCL CKLOUT Low Time (Fig. 6) t RCP ----------2 ns tRS TTL Data Setup to CLKOUT (Fig. 6) 0.3tRCP ns tRH TTL Data Hold from CKLOUT (Fig. 6) 0.3tRCP ns tRO RXIN+/- to CLKOUT Delay (Fig. 6) tRLH TTL Output Low to High Transition Time (Fig. 4) 3.0 5.0 ns tRHL TTL Output High to Low Transition Time (Fig. 4) 3.0 5.0 ns 10.0 ms 25 4 13.5 ---------- t RCP 21 4 13.5 ---------- t RCP + 7 21 ns tRPLL1 Phase Lock Loop Set (Fig. 9) tRPDD Power-Down Delay (Fig. 9) 9 ns tRDO LOCKN transition to TTL Data Output Delay (Fig. 9) 2 clock cycles tRCOL Beginning of Clock Output to LOCKN transition Time(Fig. 9) 10 clock cycles tRLCS LOCKN transition to Stop of Clock Output Time(Fig. 9) 3 clock cycles tRPLL2 Phase Lock Loop Set (Fig. 10) tRLN 10.0 Data Stop to LOCKN Transition Delay (Fig. 10) Copyright©2013 THine Electronics, Inc. 7 10/18 ms ns THine Electronics, Inc. THCV213-214_Rev2.30_E AC Timing Diagram and Test Circuits Transmitter Input/Output Switching Characteristics 90% CLKIN D<17:0> SYNC<2:0> 10% DE 90% 10% tTLH tTHL Fig. 2 CMOS/TTL Inputs Transition Time Vdiff=(TXOUT+)-(TXOUT-) 80% 80% Vdiff TA+ 20% 20% 5pF 100Ω TAtTLVT LVDS Output Load tTLVT Fig. 3 LVDS Outputs Transition Time Receiver Output Switching Characteristics TTL Output CL=8pF 90% CLKOUT D<17:0> SYNC<2:0> 10% DE 90% 10% TTL Output Load tRLH tRHL Fig. 4 CMOS/TTL Outputs Load and Transition Time Copyright©2013 THine Electronics, Inc. 11/18 THine Electronics, Inc. THCV213-214_Rev2.30_E AC Timing Diagram and Test Circuits (Continued) Transmitter Output timing D<17:0> SYNC<2:0> DE VDD/2 VDD/2 tTH tTS VDD/2 CLKIN tTCL tTCH Solid line: EDGE=”HIGH” Dashed line: EDGE=”LOW” tTCIP tTO Stop TXOUT1+/- #18 Start Stop #1 #19 #2 #3 #18 Start Stop #1 #19 #2 #3 #18 Start #1 #19 tTCP Fig. 5 Transmitter Output Timing Receiver Output timing tRCIP Stop RXIN+/- Start Stop #1 #3 #2 #18 #19 Start Stop #1 #2 #3 #18 #19 Start #1 #2 #3 tRO CLKOUT VDD/2 Solid line: EDGE=”HIGH” Dashed line: EDGE=”LOW” tRCL tRCH tRCP D<17:0> DE SYNC<2:0> VDD/2 tRS VDD/2 tRH Fig. 6 Receiver Output Timing Copyright©2013 THine Electronics, Inc. 12/18 THine Electronics, Inc. THCV213-214_Rev2.30_E AC Timing Diagram and Test Circuits (Continued) Transmitter Start-up and Power-down Sequence VDD CLKIN PDWN INIT VDD/2 VDD/2 tTPLL Low INVALID DATA TXOUT1+/- Hi-Z VALID DATA Normal Pattern tTHZ Hi-Z Fig. 7 Transmitter Start-up and Power-down Sequence Transmitter Lock Recovery Sequence VDD EDGE=”LOW” CLKIN PDWN tTSYNC1 tTSYNC2 INIT TXOUT1+/- Normal Pattern SYNC Pattern Normal Pattern Fig. 8 Transmitter Lock Recovery Sequence Copyright©2013 THine Electronics, Inc. 13/18 THine Electronics, Inc. THCV213-214_Rev2.30_E AC Timing Diagram and Test Circuits (Continued) Receiver Start-up and Power-down Sequence VDD PDWN VDD/2 VDD/2 tRPDD tRPLL1 RXIN+/- Don’t care LOCKN VDD/2 High FIX High FIX tRDO D<17:0> DE SYNC<2:0> Low FIX Low FIX tRCOL Solid line: EDGE=”HIGH” Dashed line: EDGE=”LOW” CLKOUT Fig. 9 Receiver Start-up and Power-down Sequence Receiver Lock Recovery Sequence VDD PDWN High tRPLL2 RXIN+/- Data Stop tRLN LOCKN D<17:0> DE SYNC<2:0> Low FIX tRLCS CLKOUT Solid line: EDGE=”HIGH” Dashed line: EDGE=”LOW” Fig. 10 Receiver Lock Recovery Sequence Copyright©2013 THine Electronics, Inc. 14/18 THine Electronics, Inc. THCV213 -214_Rev2.30_E Detailed Description DE Requirement With V-by-One®’s proprietary encoding scheme and CDR (Clock and Data Recovery) architecture, THCV213 and THCV214 enable transmission of 18bit video signals (D17 to D0) and 4 bit control signals (SYNC2 to SYNC0, and DE) by a single differential pair cable with minimal external components. THCV214, the receiver, can seamlessly operate for a wide range of a parallel clock frequency of 5MHz to 40MHz, detecting the frequency of an incoming data stream, and recovering both the clock and data by itself. It does not need any external frequency reference, such as a crystal oscillator. THCV213 serializes video signals and control signals separately, depending on the polarity of Data Enable (DE) input. DE is a signal which indicates whether video or control signals are active. When DE input is high, it serializes D17 to D0 inputs into a single differential data stream. And it transmits serialized control signals (SYNC2 to SYNC0) when DE input is low. THCV214 automatically extracts the clock from the incoming data stream and converts the serial data into 18 bit parallel data with DE being high or three control signals with DE being low, recognizing which type of serial data is being sent by the transmitter. There are some requirements for DE signal if the chipset is to be used in the Normal mode as described in Table 2. Operation Mode In order to accommodate various types of data format or to expedite the link establishment between the transmitter and receiver, THCV214 has two modes of operation, namely Normal mode and Shake Hand mode. Normal Mode The Normal mode operation is the one described above in “Detailed Description.” This mode fully utilizes the chipset’s capability, enabling the transmission of 18 video and 4bit control signals. It is required to have DE signal which indicates whether video or control signals are active. Shake Hand Mode Th is m ode requ ires a n extra wire connecting THCV214’s LOCKN and THCV213’s INIT pin. This wire does not need to be impedance controlled one. While the link is not being established between the transmitter and receiver, the receiver’s LOCKN is driven high, telling the transmitter to send a special set of data pattern which eases connection between the two. The chipset automatically enters the Shake Hand mode, once THCV214’s LOCKN pin and THCV213’s INIT pin are connected together. If there is no DE signal, THCV213/214 can still work in the Shake Hand mode with the transmitter’s DE input tied high. In this case, the amount of data transmission reduces to 18 bit digital signals (D17 to D0.) Copyright©2013 THine Electronics, Inc. DE Requirements for Normal Mode The length of DE being low is at least 50 clock cycle long. The maximum time of DE being high is 80us, the minimum of DE=L is 2 clock cycles. THCV213 Power Down (PDWN) Setting the PDWN pin low results in THCV213 in the Power Down mode. All the internal circuitry turns off and the TXOUT+/- outputs turn to Hi-Z. Refer to Fig. 7 THCV213 EDGE The polarity of the EDGE pin selects which edge (rising or falling) of the input clock by which the input data are latched in. When EDGE is set high, the transmitter uses the rising edge of the input clock to take in the input data. When EDGE is low, it takes in the data at the falling edge of the clock. Select its polarity so that the transmitter latches in the data with better setup/hold time margin. THCV213 Pre-Emphasis (PRE1,0) Pre-emphasis can equalize severe signal degradation caused by long distance or high-speed transmission. Two pins, PRE1 and PRE0, select the strength of preemphasis. PRE1 PRE0 Description L L w/o Pre-Emphasis L H w/ 25% Pre Emphasis H L w/ 50% Pre Emphasis H H w/ 100% Pre Emphasis THCV213 INIT Driving the INIT pin high forces the transmitter to send a special set of pattern called SYNC pattern, which makes it easier for the receiver to recover the clock and data. This function is normally used in the Shake Hand mode with a wire connecting the transmitter INIT pin and the receiver LOCKN pin. It can also be used to expedite the link establishment in the Normal mode by driving the INIT pin high at power up, forcing the transmitter to output the SYNC pattern for a certain amount of time in order to train the receiver. 15/18 THine Electronics, Inc. THCV213 -214_Rev2.30_E THCV213 Dual Display Mode (DUAL) THCV213 has two high speed output buffers so that it can be used in an application where a video source wants to send the same data to two displays. The DUAL pin activates the Dual Display mode. application where there are multiple video sources and one display. THCV214 MOD1,0 Both MOD1 and MOD0 must be tied to GND. The receiver enters into an appropriate operation mode by itself. THCV213 PRBS Setting the PRBS pin high enables the internal test pattern generator. It generates Pseudo-Random Bit Sequence of 223-1. The generated PRBS is fed into input data latches, formatted as VGA video like data, encoded and serialized into TXOUT output. This function is normally to be used for analyzing the signal integrity of the transmission channel including PCB traces, connectors, and cables. THCV214 Lock/Input Detect (LOCKN) When the PLL of THCV214 has locked to the incoming data stream, it drives LOCKN low. And then TTL/ CMOS outputs become valid. This LOCKN signal can also be used as an indicator of whether the incoming data is valid or not. This pin is to be connected to the transmitter INIT pin with a cable in the Shake Hand mode. THCV214 Power Down (PDWN) Setting the PDWN pin low results in THCV214 in the Power Down mode. All the internal circuitry and input buffers turn off, and all outputs except LOCKN and CLKOUT are held low. The LOCKN pin is driven high when in the Power Down mode. The CLKOUT is fixed one way or the other depending on the EDGE input. Refer to Fig. 9. THCV214 EDGE The polarity of the EDGE pin selects which edge (rising or falling) of the output clock by which the output data are latched out. When EDGE is set high, the receiver uses the falling edge of the output clock to put out the data so that the next-stage chip can use the rising edge of the clock to latch in the data with the maximum setup/hold time margin, and vice versa. Select its polarity according to the next-stage chip input characteristics. Cables and Connectors In a system with high speed digital signals, a special care must be taken to avoid loss and degradation of the signals due to limited bandwidth and impedance mismatch along the transmission line. Characteristic impedance of PCB traces, cables, and connectors must be tightly controlled. Use cables that have a differential characteristic impedance of 100Ω. Shielded twisted pair cables are recommended for increasing noise immunity and lowering EMI. Connectors are recommended that cause minimum discontinuities in terms of characteristic impedance and geometry of the transmission path. PCB Layout Considerations Use a four-layer PCB with signal, ground, power, and signal assigned for each layer. PCB traces for highspeed signals (TXOUT, RXIN) must be microstrip lines with a differential impedance of 100Ω. Route differential signal traces symmetrically. Avoid right angle turns of the high speed traces because they usually cause impedance discontinuity. Place a 100 Ω termination resistor between RXIN+ and RXIN- as close to the receiver as possible to reduce reflection. Separate all the power domains in order to avoid unwanted noise coupling between noisy digital and sensitive analog domains. Use high frequency ceramic capacitors of 10nF or 0.1μF as bypass capacitors between power and ground pins. Place them as close to each power pin as possible. A 4.7μF capacitor in parallel with the smaller capacitor to PLLVDD is recommended for the receiver. THCV214 Output Enable (OE) The OE pin can disable TTL/CMOS outputs and place them in Hi-Z. Thus THCV214’s TTL/CMOS outputs can be bused so that the receiver can be used in an Copyright©2013 THine Electronics, Inc. 16/18 THine Electronics, Inc. THCV213-214_Rev2.30_E Package 9 .0 + /- 0 .2 7 .0 + /- 0 .2 1 .2 M a x 1 .0 0 + /- 0 .0 5 0 .1 0 + /- 0 .0 5 2 .3 2 .3 7 .0 + /- 0 .2 9 .0 + /- 0 .2 2 .3 ø 1 .0 ø 0 .8 ø 0 .4 48 2 .3 0 .5 0 0 .7 5 0 .2 2 + /- 0 .0 5 0 .0 9 ~ 0 .2 0 0 .0 8 M 1 0° ~ 8° S S E A T IN G P L A N E 0 .1 0 S 0 .5 0 0 .2 5 0 .6 0 + /-0 .1 5 1 .0 0 U n it : m m Copyright©2013 THine Electronics, Inc. 17/18 THine Electronics, Inc. THCV213-214_Rev2.30_E Notices and Requests 1. The product specifications described in this material are subject to change without prior notice. 2. The circuit diagrams described in this material are examples of the application which may not always apply to the customer's design. We are not responsible for possible errors and omissions in this material. Please note if errors or omissions should be found in this material, we may not be able to correct them immediately. 3. This material contains our copyright, know-how or other proprietary. Copying or disclosing to third parties the contents of this material without our prior permission is prohibited. 4. Note that if infringement of any third party's industrial ownership should occur by using this product, we will be exempted from the responsibility unless it directly relates to the production process or functions of the product. 5. This product is presumed to be used for general electric equipment, not for the applications which require very high reliability (including medical equipment directly concerning people's life, aerospace equipment, or nuclear control equipment). Also, when using this product for the equipment concerned with the control and safety of the transportation means, the traffic signal equipment, or various Types of safety equipment, please do it after applying appropriate measures to the product. 6. Despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a certain small probability, which is inevitable to a semi-conductor product. Therefore, you are encouraged to have sufficiently redundant or error preventive design applied to the use of the product so as not to have our product cause any social or public damage. 7. Please note that this product is not designed to be radiation-proof. 8. Customers are asked, if required, to judge by themselves if this product falls under the category of strategic goods under the Foreign Exchange and Foreign Trade Control Law. THine Electronics, Inc. E-mail: [email protected] Copyright©2013 THine Electronics, Inc. 18/18 THine Electronics, Inc.