DATASHEET

ISL8483E, ISL8485E
Data Sheet
September 3, 2015
ESD Protected to ±15kV, 5V, Low Power,
High Speed or Slew Rate Limited,
RS-485/RS-422 Transceivers
FN6048.10
Features
• Pb-Free Available (RoHS Compliant)
• Military and Extended Industrial Temperature Options
(+125°C)
These Intersil RS-485, RS-422 devices are ESD protected,
BiCMOS 5V powered, single transceivers that meet both the
RS-485 and RS-422 standards for balanced communication.
Each driver output/receiver input is protected against ±15kV
ESD strikes, without latch-up. Unlike competitive devices,
this Intersil family is specified for 10% tolerance supplies
(4.5V to 5.5V).
• RS-485 I/O Pin ESD Protection  15kV HBM
- Class 3 ESD Level on all Other Pins . . . . . . >7kV HBM
• Specified for 10% Tolerance Supplies
• High Data Rate Version (ISL8485E) . . . . . up to 10Mbps
• Slew Rate Limited Version for Error Free Data
Transmission (ISL8483E) . . . . . . . . . . . . . up to 250kbps
The ISL8483E utilizes slew rate limited drivers which reduce
EMI, and minimize reflections from improperly terminated
transmission lines, or un-terminated stubs in multidrop and
multipoint applications.
• Single Unit Load Allows up to 32 Devices on the Bus
• 1nA Low Current Shutdown Mode (ISL8483E)
Data rates up to 10Mbps are achievable by using the
ISL8485E which features higher slew rates.
• Low Quiescent Current:
- 160µA (ISL8483E)
- 500µA (ISL8485E)
Both devices present a “single unit load” to the RS-485 bus,
which allows up to 32 transceivers on the network.
• -7V to +12V Common Mode Input Voltage Range
Receiver (Rx) inputs feature a “fail-safe if open” design,
which ensures a logic high Rx output, if Rx inputs are
floating.
• Three State Rx and Tx Outputs
• 30ns Propagation Delays, 5ns Skew (ISL8485E)
• Operate from a Single +5V Supply (10% Tolerance)
Driver (Tx) outputs are short circuit protected, even for
voltages exceeding the power supply voltage. Additionally,
on-chip thermal shutdown circuitry disables the Tx outputs to
prevent damage if power dissipation becomes excessive.
• Current Limiting and Thermal Shutdown for driver
Overload Protection
Applications
These half duplex configurations multiplex the Rx inputs and
Tx outputs to allow transceivers with Rx and Tx disable
functions in 8 lead packages.
• Factory Automation
• Security Networks
• Building Environmental Control Systems
• Industrial/Process Control Networks
• Level Translators (e.g., RS-232 to RS-422)
• RS-232 “Extension Cords”
TABLE 1. SUMMARY OF FEATURES
NO. OF
DEVICES
ALLOWED DATA RATE
PART
HALF/FULL
MIL
(Mbps)
NUMBER
DUPLEX TEMP? ON BUS
SLEW-RATE
LIMITED?
RECEIVER/DRIVER QUIESCENT LOW POWER
PIN
ENABLE?
ICC (µA)
SHUTDOWN? COUNT
ISL8483E
Half
No
32
0.25
Yes
Yes
160
Yes
8
ISL8485E
Half
Yes
32
10
No
Yes
500
No
8
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas LLC 2003, 2004, 2005, 2008, 2015. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
ISL8483E, ISL8485E
Ordering Information
Pinout
ISL8483E, ISL8485E
(8 LD PDIP, SOIC)
TOP VIEW
RO 1
PART NUMBER
8
VCC
RE 2
7
B/Z
DE 3
6
A/Y
5
GND
R
D
DI 4
Truth Tables
TRANSMITTING
INPUTS
OUTPUTS
RE
DE
DI
Z
Y
X
1
1
0
1
X
1
0
1
0
0
0
X
High-Z
High-Z
1
0
X
High-Z *
High-Z *
*Shutdown Mode for ISL8483E (see Note 7)
PART
MARKING
TEMP.
RANGE
(°C)
PKG.
PACKAGE DWG. #
ISL8483EIBZ**
(Note)
8483EIBZ
-40 to +85 8 Ld SOIC M8.15
(Pb-free)
ISL8483EIPZ
(Note) (No
longer
available,
recommended
replacement:
ISL8487EIPZ)
ISL8483EIPZ
-40 to +85 8 Ld PDIP* E8.3
(Pb-free)
ISL8485EABZ**
(Note)
8485EABZ
-40 to +125 8 Ld SOIC M8.15
(Pb-free)
ISL8485ECBZ** 8485ECBZ
(Note)
0 to +70
8 Ld SOIC M8.15
(Pb-free)
ISL8485EIBZ**
(Note)
8485EIBZ
-40 to +85 8 Ld SOIC M8.15
(Pb-free)
ISL8485EIPZ
(Note)
ISL8485EIPZ
-40 to +85 8 Ld PDIP* E8.3
(Pb-free)
*Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.
**Add “-T” suffix for tape and reel. Please refer to TB347 for details
on reel specifications
RECEIVING
INPUTS
OUTPUT
RE
DE
A-B
RO
0
0
 +0.2V
1
0
0
 -0.2V
0
0
0
Inputs Open
1
1
0
X
High-Z*
1
1
X
High-Z
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets; molding compounds/die attach
materials and 100% matte tin plate plus anneal- (e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
*Shutdown Mode for ISL8483E (see Note 7)
2
FN6048.10
September 3, 2015
ISL8483E, ISL8485E
Pin Descriptions
PIN
FUNCTION
RO
Receiver output: If A > B by at least 0.2V, RO is high; If A < B by 0.2V or more, RO is low; RO = High if A and B are unconnected (floating).
RE
Receiver output enable. RO is enabled when RE is low; RO is high impedance when RE is high.
DE
Driver output enable. The driver outputs, Y and Z, are enabled by bringing DE high. They are high impedance when DE is low.
DI
Driver input. A low on DI forces output Y low and output Z high. Similarly, a high on DI forces output Y high and output Z low.
GND
Ground connection.
A/Y
±15kV HBM ESD Protected, RS485, RS4-422 level noninverting receiver input and noninverting driver output. Pin is an input (A) if
DE = 0; pin is an output (Y) if DE = 1.
B/Z
±15kV HBM ESD Protected, RS485, RS4-422 level inverting receiver input and inverting driver output. Pin is an input (B) if DE = 0;
pin is an output (Z) if DE = 1.
VCC
System power supply input (4.5V to 5.5V).
Typical Operating Circuits
ISL8483E, ISL8485E
+5V
+5V
+
8
0.1μF
0.1μF
+
8
VCC
1
RO
2
RE
3
DE
4
DI
VCC
R
D
B/Z
7
A/Y
6
RT
RT
4
7
B/Z
DE
3
6
A/Y
RE
2
RO
1
R
D
GND
DI
GND
5
5
3
FN6048.10
September 3, 2015
ISL8483E, ISL8485E
Absolute Maximum Ratings
Thermal Information
VCC to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V
Input Voltages
DI, DE, RE . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to (VCC +0.5V)
Input/Output Voltages
A/Y, B/Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -8V to +12.5V
RO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to (VCC +0.5V)
Short Circuit Duration
Y, Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . See Specification Table
Thermal Resistance (Typical, Note 1)
Operating Conditions
JA (°C/W)
8 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . .
170
8 Ld PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . .
140
Maximum Junction Temperature (Plastic Package) . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
*Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in reflow solder processing
applications.
Temperature Range
ISL8485ECx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
ISL848xEIx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
ISL8485EAx . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +125°C
ISL8485EMx. . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
Test Conditions: VCC = 4.5V to 5.5V; Unless Otherwise Specified.
Typicals are at VCC = 5V, TA = +25°C, (Note 2)
PARAMETER
SYMBOL
TEST CONDITIONS
TEMP
MIN
(°C) (Note 12)
TYP
MAX
(Note 12) UNITS
DC CHARACTERISTICS
Driver Differential VOUT (no load)
VOD1
Driver Differential VOUT (with load)
VOD2
Change in Magnitude of Driver
Differential VOUT for
Complementary Output States
Driver Common-Mode VOUT
Change in Magnitude of Driver
Common-Mode VOUT for
Complementary Output States
Full
-
-
VCC
V
R = 50 (RS-422), (Figure1)
Full
2
3
-
V
R = 27 (RS-485), (Figure 1)
Full
1.5
2.3
5
V
VOD
R = 27 or 50, (Figure 1)
Full
-
0.01
0.2
V
VOC
R = 27 or 50, (Figure 1)
Full
-
-
3
V
VOC
R = 27 or 50, (Figure 1)
Full
-
0.01
0.2
V
Logic Input High Voltage
VIH
DE, DI, RE
Full
2
-
-
V
Logic Input Low Voltage
VIL
DE, DI, RE
Full
-
-
0.8
V
Logic Input Current
IIN1
DE, DI, RE (ISL8483E)
Full
-2
-
2
µA
IIN1
DI (ISL8485E)
Full
-2
-
2
µA
IIN1
DE, RE (ISL8485E)
Full
-25
-
25
µA
Input Current (A, B), (Note 10)
IIN2
DE = 0V, VCC = 0V or 4.5 to
5.5V
Full
-
-
1
mA
Receiver Differential Threshold
Voltage
VTH
-7V  VCM  12V
VIN = 12V
VIN = -7V
Full
-
-
-0.8
mA
Full
-0.2
-
0.2
V
Receiver Input Hysteresis
VTH
VCM = 0V
25
-
70
-
mV
Receiver Output High Voltage
VOH
IO = -4mA, VID = 200mV
Full
3.5
-
-
V
Receiver Output Low Voltage
VOL
IO = -4mA, VID = 200mV
Full
-
-
0.4
V
Three-State (high impedance)
Receiver Output Current
IOZR
0.4V  VO  2.4V
Full
-
-
1
µA
Receiver Input Resistance
RIN
-7V  VCM  12V
Full
12
-
-
k
4
FN6048.10
September 3, 2015
ISL8483E, ISL8485E
Electrical Specifications
Test Conditions: VCC = 4.5V to 5.5V; Unless Otherwise Specified.
Typicals are at VCC = 5V, TA = +25°C, (Note 2) (Continued)
PARAMETER
SYMBOL
No-Load Supply Current, (Note 3)
ICC
TEST CONDITIONS
ISL8485E, DI, RE = 0V or VCC
ISL8483E, DI, RE = 0V or VCC
TEMP
MIN
(°C) (Note 12)
TYP
MAX
(Note 12) UNITS
DE = VCC
Full
-
700
900
µA
DE = 0V
Full
-
500
565
µA
DE = VCC
Full
-
470
650
µA
DE = 0V
Full
-
160
250
µA
Shutdown Supply Current
ISHDN
ISL8483E, DE = 0V, RE = VCC, DI = 0V or VCC
Full
-
1
50
nA
Driver Short-Circuit Current,
VO = High or Low
IOSD1
DE = VCC, -7V  VY or VZ  12V, (Note 4)
Full
35
-
250
mA
Receiver Short-Circuit Current
IOSR
0V  VO  VCC
Full
7
-
85
mA
Full
18
30
50
ns
SWITCHING CHARACTERISTICS (ISL8485E)
tPLH, tPHL RDIFF = 54, CL = 100pF, (Figure 2)
Driver Input to Output Delay
Driver Output Skew
tSKEW
RDIFF = 54, CL = 100pF, (Figure 2)
Full
-
2
10
ns
Driver Differential Rise or Fall Time
tR, tF
RDIFF = 54, CL = 100pF, (Figure 2)
Full
3
11
25
ns
Driver Enable to Output High
tZH
CL = 100pF, SW = GND, (Figure 3)
Full
-
17
70
ns
Driver Enable to Output Low
tZL
CL = 100pF, SW = VCC, (Figure 3)
Full
-
14
70
ns
Driver Disable from Output High
tHZ
CL = 15pF, SW = GND, (Figure 3)
Full
-
19
70
ns
Driver Disable from Output Low
tLZ
CL = 15pF, SW = VCC, (Figure 3)
Full
-
13
70
ns
Full
30
40
150
ns
(Figure 4)
25
-
5
-
ns
tPLH, tPHL (Figure 4)
Receiver Input to Output Delay
Receiver Skew | tPLH - tPHL |
tSKD
Receiver Enable to Output High
tZH
CL = 15pF, SW = GND, (Figure 5)
Full
-
9
50
ns
Receiver Enable to Output Low
tZL
CL = 15pF, SW = VCC, (Figure 5)
Full
-
9
50
ns
Receiver Disable from Output High
tHZ
CL = 15pF, SW = GND, (Figure 5)
Full
-
9
50
ns
Receiver Disable from Output Low
tLZ
CL = 15pF, SW = VCC, (Figure 5)
Full
-
9
50
ns
(Note 11)
Full
10
-
-
Mbps
tPLH, tPHL RDIFF = 54, CL = 100pF, (Figure 2)
Full
250
800
2000
ns
Maximum Data Rate
fMAX
SWITCHING CHARACTERISTICS (ISL8483E)
Driver Input to Output Delay
Driver Output Skew
tSKEW
RDIFF = 54, CL = 100pF, (Figure 2)
Full
-
160
800
ns
Driver Differential Rise or Fall Time
tR, tF
RDIFF = 54, CL = 100pF, (Figure 2)
Full
250
800
2000
ns
Driver Enable to Output High
tZH
CL = 100pF, SW = GND, (Figure 3), (Note 5)
Full
250
-
2000
ns
Driver Enable to Output Low
tZL
CL = 100pF, SW = VCC, (Figure 3), (Note 5)
Full
250
-
2000
ns
Driver Disable from Output High
tHZ
CL = 15pF, SW = GND, (Figure 3)
Full
300
-
3000
ns
tLZ
CL = 15pF, SW = VCC, (Figure 3)
Full
300
-
3000
ns
Full
250
350
2000
ns
(Figure 4)
25
-
25
-
ns
tZH
CL = 15pF, SW = GND, (Figure 5), (Note 6)
Full
-
10
50
ns
Receiver Enable to Output Low
tZL
CL = 15pF, SW = VCC, (Figure 5), (Note 6)
Full
-
10
50
ns
Receiver Disable from Output High
tHZ
CL = 15pF, SW = GND, (Figure 5)
Full
-
10
50
ns
Receiver Disable from Output Low
tLZ
CL = 15pF, SW = VCC, (Figure 5)
Full
-
10
50
ns
fMAX
(Note 11)
Full
250
-
-
kbps
tSHDN
(Note 7)
Full
50
200
600
ns
Full
-
-
2000
ns
Driver Disable from Output Low
tPLH, tPHL (Figure 4)
Receiver Input to Output Delay
Receiver Skew | tPLH - tPHL |
tSKD
Receiver Enable to Output High
Maximum Data Rate
Time to Shutdown
tZH(SHDN) CL = 100pF, SW = GND, (Figure 3), (Notes 7, 8)
Driver Enable from Shutdown to
Output High
5
FN6048.10
September 3, 2015
ISL8483E, ISL8485E
Electrical Specifications
Test Conditions: VCC = 4.5V to 5.5V; Unless Otherwise Specified.
Typicals are at VCC = 5V, TA = +25°C, (Note 2) (Continued)
PARAMETER
SYMBOL
TEMP
MIN
(°C) (Note 12)
TEST CONDITIONS
TYP
MAX
(Note 12) UNITS
Driver Enable from Shutdown to
Output Low
tZL(SHDN) CL = 100pF, SW = VCC, (Figure 5), (Notes 7, 8)
Full
-
-
2000
ns
Receiver Enable from Shutdown to
Output High
tZH(SHDN) CL = 15pF, SW = GND, (Figure 5), (Notes 7, 9)
Full
-
-
2500
ns
Receiver Enable from Shutdown to
Output Low
tZL(SHDN) CL = 15pF, SW = VCC, (Figure 5), (Notes 7, 9)
Full
-
-
2500
ns
25
-
15
-
kV
25
-
>7
-
kV
ESD PERFORMANCE
RS-485 Pins (A/Y, B/Z)
Human Body Model
All Other Pins
NOTES:
2. All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless
otherwise specified.
3. Supply current specification is valid for loaded drivers when DE = 0V.
4. Applies to peak current. See “Typical Performance Curves” on page 10 for more information.
5. When testing the ISL8483E, keep RE = 0 to prevent the device from entering SHDN.
6. When testing the ISL8483E, the RE signal high time must be short enough (typically <200ns) to prevent the device from entering SHDN.
7. The ISL8483E is put into shutdown by bringing RE high and DE low. If the inputs are in this state for less than 50ns, the parts are guaranteed
not to enter shutdown. If the inputs are in this state for at least 600ns, the parts are guaranteed to have entered shutdown. See “Low Power
Shutdown Mode (ISL8483E Only)” on page 9.
8. Keep RE = VCC, and set the DE signal low time >600ns to ensure that the device enters SHDN.
9. Set the RE signal high time >600ns to ensure that the device enters SHDN.
10. Devices meeting these limits are denoted as “single unit load (1 UL)” transceivers. The RS-485 standard allows up to 32 Unit Loads on the bus.
11. Limits established by characterization and are not production tested.
12. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested.
Test Circuits and Waveforms
VCC
R
DE
DI
Z
VOD
D
Y
R
VOC
FIGURE 1. DRIVER VOD AND VOC
6
FN6048.10
September 3, 2015
ISL8483E, ISL8485E
Test Circuits and Waveforms (Continued)
3V
DI
1.5V
1.5V
0V
tPLH
tPHL
VOH
VCC
CL = 100pF
DE
50%
OUT (Y)
50%
VOL
Z
DI
tPHL
RDIFF
D
Y
CL = 100pF
tPLH
VOH
OUT (Z)
50%
SIGNAL
GENERATOR
50%
VOL
90%
DIFF OUT (Y - Z)
+VOD
90%
10%
10%
tR
-VOD
tF
SKEW = |tPLH (Y or Z) - tPHL (Z or Y)|
FIGURE 2B. MEASUREMENT POINTS
FIGURE 2A. TEST CIRCUIT
FIGURE 2. DRIVER PROPAGATION DELAY AND DIFFERENTIAL TRANSITION TIMES
DE
Z
DI
500
VCC
D
SIGNAL
GENERATOR
SW
Y
GND
CL
3V
DE
(SHDN) FOR ISL8483E ONLY
PARAMETER OUTPUT
RE
DI
SW
CL (pF)
tHZ
Y/Z
X
1/0
GND
15
tLZ
Y/Z
X
0/1
VCC
15
tZH
Y/Z
0 (Note 5)
1/0
GND
100
tZL
Y/Z
tZH(SHDN)
Y/Z
1 (Note 8)
tZL(SHDN)
Y/Z
1 (Note 8)
0 (Note 5)
0/1
VCC
100
1/0
GND
100
0/1
VCC
100
1.5V
NOTE 7
1.5V
0V
tZH, tZH(SHDN)
OUTPUT HIGH
NOTE 7
tHZ
VOH - 0.5V
OUT (Y, Z)
VOH
2.3V
0V
tZL, tZL(SHDN)
tLZ
NOTE 7
VCC
OUT (Y, Z)
2.3V
OUTPUT LOW
VOL + 0.5V V
OL
FIGURE 3B. MEASUREMENT POINTS
FIGURE 3A. TEST CIRCUIT
FIGURE 3. DRIVER ENABLE AND DISABLE TIMES
3V
RE
+1.5V
15pF
B
R
A
A
1.5V
1.5V
RO
0V
tPLH
tPHL
VCC
SIGNAL
GENERATOR
50%
RO
50%
0V
FIGURE 4A. TEST CIRCUIT
FIGURE 4B. MEASUREMENT POINTS
FIGURE 4. RECEIVER PROPAGATION DELAY
7
FN6048.10
September 3, 2015
ISL8483E, ISL8485E
Test Circuits and Waveforms (Continued)
RE
B
SIGNAL
GENERATOR
1k
RO
R
VCC
SW
A
GND
15pF
NOTE 7
RE
3V
1.5V
1.5V
0V
(SHDN) FOR ISL8483E ONLY
tZH, tZH(SHDN)
PARAMETER
DE
A
SW
tHZ
0
+1.5V
GND
tLZ
0
-1.5V
VCC
tZH (Note 6)
0
+1.5V
GND
tZL (Note 6)
0
-1.5V
VCC
tZH(SHDN) (Note 9)
0
tZL(SHDN) (Note 9)
0
+1.5V
-1.5V
OUTPUT HIGH
NOTE 7
RO
VOH - 0.5V
VOH
1.5V
0V
tZL, tZL(SHDN)
tLZ
VCC
NOTE 7
RO
1.5V
GND
OUTPUT LOW
VCC
FIGURE 5A. TEST CIRCUIT
tHZ
VOL + 0.5V V
OL
FIGURE 5B. MEASUREMENT POINTS
FIGURE 5. RECEIVER ENABLE AND DISABLE TIMES
Application Information
RS-485 and RS-422 are differential (balanced) data
transmission standards for use in long haul or noisy
environments. RS-422 is a subset of RS-485, so RS-485
transceivers are also RS-422 compliant. RS-422 is a
point-to-multipoint (multidrop) standard, which allows only
one driver and up to 10 (assuming one unit load devices)
receivers on each bus. RS-485 is a true multipoint standard,
which allows up to 32 one unit load devices (any
combination of drivers and receivers) on each bus. To allow
for multipoint operation, the RS-485 specification requires
that drivers must handle bus contention without sustaining
any damage.
Another important advantage of RS-485 is the extended
common mode range (CMR), which specifies that the driver
outputs and receiver inputs withstand signals that range from
+12V to -7V. RS-422 and RS-485 are intended for runs as
long as 4000 feet, so the wide CMR is necessary to handle
ground potential differences, as well as voltages induced in
the cable by external fields.
Receiver Features
These devices utilize a differential input receiver for maximum
noise immunity and common mode rejection. Input sensitivity
is 200mV, as required by the RS422 and RS-485
specifications.
Receiver input impedance surpasses the RS-422 spec of
4k, and meets the RS-485 “Unit Load” requirement of 12k
minimum.
8
Receiver inputs function with common mode voltages as
great as 7V outside the power supplies (i.e., +12V and
-7V), making them ideal for long networks where induced
voltages are a realistic concern.
All the receivers include a “fail-safe if open” function that
guarantees a high level receiver output if the receiver inputs
are unconnected (floating).
Receivers easily meet the data rates supported by the
corresponding driver.
ISL8483E, ISL8485E receiver outputs are three-stat-able via
the active low RE input.
Driver Features
The RS485, RS-422 driver is a differential output device that
delivers at least 1.5V across a 54 load (RS-485), and at
least 2V across a 100 load (RS-422). The drivers feature
low propagation delay skew to maximize bit width, and to
minimize EMI.
Drivers of the ISL8483E, ISL8485E are tri-stateable via the
active high DE input.
The ISL8483E driver outputs are slew rate limited to
minimize EMI, and to minimize reflections in un-terminated
or improperly terminated networks. Data rate on these slew
rate limited versions is a maximum of 250kbps. Outputs of
the ISL8485E driver are not limited, so faster output
transition times allow data rates of at least 10Mbps.
FN6048.10
September 3, 2015
ISL8483E, ISL8485E
Data Rate, Cables, and Terminations
Low Power Shutdown Mode (ISL8483E Only)
RS485, RS-422 are intended for network lengths up to 4000
feet, but the maximum system data rate decreases as the
transmission length increases. Devices operating at 10Mbps
are limited to lengths less than 100 feet, while the 250kbps
versions can operate at full data rates with lengths in excess
of 1000 feet.
These CMOS transceivers all use a fraction of the power
required by their bipolar counterparts, but the ISL8483E
includes a shutdown feature that reduces the already low
quiescent ICC to a 1nA trickle. The ISL8483E enters
shutdown whenever the receiver and driver are
simultaneously disabled (RE = VCC and DE = GND) for a
period of at least 600ns. Disabling both the driver and the
receiver for less than 50ns guarantees that the ISL8483E
will not enter shutdown.
Twisted pair is the cable of choice for RS485, RS-422
networks. Twisted pair cables tend to pick up noise and
other electromagnetically induced voltages as common
mode signals, which are effectively rejected by the
differential receivers in these ICs.
Proper termination is imperative, when using the 10Mbps
devices, to minimize reflections. Short networks using the
250kbps versions need not be terminated, but, terminations
are recommended unless power dissipation is an overriding
concern.
In point-to-point, or point-to-multipoint (single driver on bus)
networks, the main cable should be terminated in its
characteristic impedance (typically 120) at the end farthest
from the driver. In multi-receiver applications, stubs
connecting receivers to the main cable should be kept as
short as possible. multipoint (multi-driver) systems require
that the main cable be terminated in its characteristic
impedance at both ends. Stubs connecting a transceiver to
the main cable should be kept as short as possible.
Built-In Driver Overload Protection
As stated previously, the RS-485 specification requires that
drivers survive worst case bus contentions undamaged. The
ISL848xE devices meet this requirement via driver output
short circuit current limits, and on-chip thermal shutdown
circuitry.
The driver output stages incorporate short circuit current
limiting circuitry which ensures that the output current never
exceeds the RS-485 specification, even at the common
mode voltage range extremes. Additionally, these devices
utilize a foldback circuit which reduces the short circuit
current, and thus the power dissipation, whenever the
contending voltage exceeds either supply.
In the event of a major short circuit condition, ISL848xE
devices also include a thermal shutdown feature that
disables the drivers whenever the die temperature becomes
excessive. This eliminates the power dissipation, allowing
the die to cool. The drivers automatically re-enable after the
die temperature drops about 15°. If the contention persists,
the thermal shutdown/re-enable cycle repeats until the fault
is cleared. Receivers stay operational during thermal
shutdown.
9
Note that receiver and driver enable times increase when
the ISL8483E enables from shutdown. Refer to Notes 5-8,
on page 6, at the end of the “Electrical Specifications” table,
for more information.
ESD Protection
All pins on these interface devices include class 3 Human
Body Model (HBM) ESD protection structures, but the
RS-485 pins (driver outputs and receiver inputs) incorporate
advanced structures allowing them to survive ESD events in
excess of 15kV HBM. The RS-485 pins are particularly
vulnerable to ESD damage because they typically connect to
an exposed port on the exterior of the finished product.
Simply touching the port pins, or connecting a cable, can
cause an ESD event that might destroy unprotected ICs.
These new ESD structures protect the device whether or not
it is powered up, protect without allowing any latchup
mechanism to activate, and without degrading the RS-485
common mode range of -7V to +12V. This built-in ESD
protection eliminates the need for board level protection
structures (e.g., transient suppression diodes), and the
associated, undesirable capacitive load they present.
Human Body Model Testing
As the name implies, this test method emulates the ESD
event delivered to an IC during human handling. The tester
delivers the charge stored on a 100pF capacitor through a
1.5k current limiting resistor into the pin under test. The
HBM method determines an IC’s ability to withstand the ESD
events typically present during handling and manufacturing.
The RS-485 pin survivability on this high ESD family has
been characterized to be in excess of 15kV, for discharges
to GND.
FN6048.10
September 3, 2015
ISL8483E, ISL8485E
VCC = 5V, TA = +25°C, ISL8483E and ISL8485E; Unless Otherwise Specified.
90
3.6
80
3.4
DIFFERENTIAL OUTPUT VOLTAGE (V)
DRIVER OUTPUT CURRENT (mA)
Typical Performance Curves
70
60
50
40
30
20
10
0
0
1
2
3
4
3.2
RDIFF = 100
3.0
2.8
2.6
2.4
RDIFF = 54
2.2
2.0
-40
5
-25
DIFFERENTIAL OUTPUT VOLTAGE (V)
FIGURE 6. DRIVER OUTPUT CURRENT vs DIFFERENTIAL
OUTPUT VOLTAGE
700
140
650
Y OR Z = LOW
80
550
60
500
40
20
0
-20
75
85
ISL8485E, DE = VCC, RE = X
ISL8485E,
DE==GND,
GND,RE
RE==XX,
ISL8485, DE
450
ISL8483E, DE = VCC, RE = X
400
350
Y OR Z = HIGH
-40
300
-60
250
-80
-100
-120
50
600
ICC (µA)
OUTPUT CURRENT (mA)
100
25
FIGURE 7. DRIVER DIFFERENTIAL OUTPUT VOLTAGE vs
TEMPERATURE
160
120
0
TEMPERATURE (°C)
200
-7 -6
-4
-2
0
2
4
6
OUTPUT VOLTAGE (V)
8
10
150
-40
12
ISL8483E, DE = GND, RE = GND
-25
0
25
TEMPERATURE (oC)
50
75
85
FIGURE 9. SUPPLY CURRENT vs TEMPERATURE
FIGURE 8. DRIVER OUTPUT CURRENT vs SHORT CIRCUIT
VOLTAGE
400
1200
tPLHY
1000
tPLHZ
300
SKEW (ns)
PROPAGATION DELAY (ns)
1100
900
tPHLY
800
tPHLZ
700
|tPHLY - tPLHZ|
200
100
600
500
-40
|tPLHY - tPHLZ|
|CROSS PT. OF Y AND Z - CROSS PT. OF YAND Z|
-25
0
25
50
TEMPERATURE (°C)
FIGURE 10. DRIVER PROPAGATION DELAY vs
TEMPERATURE (ISL8483E)
10
75
85
0
-40
-25
0
25
50
75
85
TEMPERATURE (°C)
FIGURE 11. DRIVER SKEW vs TEMPERATURE (ISL8483E)
FN6048.10
September 3, 2015
ISL8483E, ISL8485E
Typical Performance Curves
VCC = 5V, TA = +25°C, ISL8483E and ISL8485E; Unless Otherwise Specified. (Continued)
3.0
35
2.5
tPHLY
tPHLZ
30
SKEW (ns)
PROPAGATION DELAY (ns)
40
tPLHZ
|tPHLY - tPLHZ|
|tPLHY - tPHLZ|
2.0
tPLHY
25
1.5
|CROSSING PT. OF Y AND Z - CROSSING PT. OF Y AND Z|
0
25
50
1
-40
85
75
-25
TEMPERATURE (°C)
0
5
RO
0
4
3
2
RECEIVER OUTPUT (V)
5
DRIVER INPUT (V)
DI
B/Z
A/Y
1
0
DI
3
2
DRIVER OUTPUT (V)
4
RECEIVER OUTPUT (V)
5
DRIVER INPUT (V)
RECEIVER OUTPUT (V)
DRIVER OUTPUT (V)
RO
0
B/Z
A/Y
1
0
TIME (10ns/DIV)
FIGURE 16. DRIVER AND RECEIVER WAVEFORMS,
LOW TO HIGH (ISL8485E)
11
5
0
5
RO
0
4
3
A/Y
2
B/Z
1
0
FIGURE 15. DRIVER AND RECEIVER WAVEFORMS,
HIGH TO LOW (ISL8483E)
0
5
85
75
TIME (400ns/DIV)
FIGURE 14. DRIVER AND RECEIVER WAVEFORMS,
LOW TO HIGH (ISL8483E)
DI
50
RDIFF = 54, CL = 100pF
TIME (400ns/DIV)
RDIFF = 54, CL = 100pF
25
FIGURE 13. DRIVER SKEW vs TEMPERATURE (ISL8485E)
DRIVER OUTPUT (V)
DRIVER OUTPUT (V)
RECEIVER OUTPUT (V)
FIGURE 12. DRIVER PROPAGATION DELAY vs
TEMPERATURE (ISL8485E)
RDIFF = 54, CL = 100pF
0
TEMPERATURE (°C)
DRIVER INPUT (V)
-25
RDIFF = 54, CL = 100pF
DI
5
5
0
RO
DRIVER INPUT (V)
20
-40
0
4
3
A/Y
2
B/Z
1
0
TIME (10ns/DIV)
FIGURE 17. DRIVER AND RECEIVER WAVEFORMS,
HIGH TO LOW (ISL8485E)
FN6048.10
September 3, 2015
ISL8483E, ISL8485E
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
GND
TRANSISTOR COUNT:
518
PROCESS:
Si Gate CMOS
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make
sure that you have the latest revision.
DATE
REVISION
September 3, 2015
FN6048.10
CHANGE
- Ordering Information Table on page 2.
- Added Revision History.
- Added About Intersil Verbiage.
-Updated POD M8.15 to most current revision with changes as follows:
-Revision 1 to Revision 2 Changes:
Updated to new POD format by removing table and moving dimensions onto drawing and adding land
pattern
-Revision 2 to Revision 3 Changes:
Changed Note 1 "1982" to "1994"
Changed in Typical Recommended Land Pattern the following:
2.41(0.095) to 2.20(0.087)
0.76 (0.030) to 0.60(0.023)
0.200 to 5.20(0.205)
-Revision 3 to Revision 4 Changes:
Changed Note 1 "1982" to "1994"
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
12
FN6048.10
September 3, 2015
ISL8483E, ISL8485E
Dual-In-Line Plastic Packages (PDIP)
E8.3 (JEDEC MS-001-BA ISSUE D)
N
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
1 2 3
INCHES
N/2
-B-
-AD
E
BASE
PLANE
-C-
SEATING
PLANE
A2
A
L
D1
e
B1
D1
A1
eC
B
0.010 (0.25) M
C A B S
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.210
-
5.33
4
A1
0.015
-
0.39
-
4
A2
0.115
0.195
2.93
4.95
-
B
0.014
0.022
0.356
0.558
-
C
L
B1
0.045
0.070
1.15
1.77
8, 10
eA
C
0.008
0.014
0.204
C
D
0.355
0.400
9.01
eB
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between
English and Metric dimensions, the inch dimensions control.
0.005
-
0.13
-
5
E
0.300
0.325
7.62
8.25
6
E1
0.240
0.280
6.10
7.11
5
e
0.100 BSC
eA
0.300 BSC
3. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication No. 95.
eB
-
L
0.115
5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).
6. E and eA are measured with the leads constrained to be perpendicular to datum -C- .
5
D1
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
4. Dimensions A, A1 and L are measured with the package seated
in JEDEC seating plane gauge GS-3.
0.355
10.16
N
8
2.54 BSC
-
7.62 BSC
0.430
-
0.150
2.93
8
6
10.92
7
3.81
4
9
Rev. 0 12/93
7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).
13
FN6048.10
September 3, 2015
ISL8483E, ISL8485E
Package Outline Drawing
M8.15
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 1/12
DETAIL "A"
1.27 (0.050)
0.40 (0.016)
INDEX
6.20 (0.244)
5.80 (0.228)
AREA
0.50 (0.20)
x 45°
0.25 (0.01)
4.00 (0.157)
3.80 (0.150)
1
2
8°
0°
3
0.25 (0.010)
0.19 (0.008)
SIDE VIEW “B”
TOP VIEW
2.20 (0.087)
SEATING PLANE
5.00 (0.197)
4.80 (0.189)
1.75 (0.069)
1.35 (0.053)
1
8
2
7
0.60 (0.023)
1.27 (0.050)
3
6
4
5
-C-
1.27 (0.050)
0.51(0.020)
0.33(0.013)
SIDE VIEW “A
0.25(0.010)
0.10(0.004)
5.20(0.205)
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensioning and tolerancing per ANSI Y14.5M-1994.
2. Package length does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
3. Package width does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
4. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
5. Terminal numbers are shown for reference only.
6. The lead width as measured 0.36mm (0.014 inch) or greater above the
seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch).
7. Controlling dimension: MILLIMETER. Converted inch dimensions are not
necessarily exact.
8. This outline conforms to JEDEC publication MS-012-AA ISSUE C.
14
FN6048.10
September 3, 2015
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