DATASHEET

11.1Gb/s Driver
ISL35111
Features
The ISL35111 is a de-emphasis driver with extended
functionality for advanced protocols operating with line rates
up to 11.1Gbps such as 10G Ethernet. The ISL35111 is a
high-speed driver/limiting amplifier with built-in de-emphasis
to drive twin-axial copper cables and compensate for the
frequency dependent attenuation of PCB traces, such as the
SFI channel in the 10G SFP+ specification (SFF-8431).
• Supports data rates up to 11.1Gbps
Used in conjunction with Intersil’s ISL36111 receive-side
equalizer, ISL35111 enables active copper cable assemblies
that support 10G serial data transmission over >15m of
twin-axial copper cables.
• Supports 64b/66b encoded data – long run lengths
Operating on a single 1.2V power supply, the ISL35111
enables channel throughputs of 10Gbps to 11.1Gbps while
supporting lower data rates including 8.5, 6.25, 5, 4.25, 3.125,
2.5 and 1Gb/s. The ISL35111 uses current mode logic (CML)
input/output and is packaged in a 3mmx3mm 16 lead QFN.
• TX_Disable and TX_LOS
• Low power (85mW typical)
• Low latency (<500ps)
• Adjustable output de-emphasis
• Single channel driver in a 3mmx3mm QFN package for
straight route-through architecture and simplified routing
• Line silence preservation
• 1.2V supply voltage
Applications
• Active copper cable modules (SFP+, QSFP, CXP, etc.)
• Optical transceiver modules (SFP+, QSFP, CXP, etc.)
• 10G Ethernet
• 40G/100G Ethernet
• Fibre Channel
• High-speed active cable assemblies
• High-speed printed circuit board (PCB) traces
Benefits
• Thinner gauge cable
• Extends cable reach greater than 3x
• Improved BER
1.2V
LOS
0.1mF
CP-A CP-B
Vdd
0.1mF
IN [P]
OUT [P]
0.1mF
1.2V
ISL36111
QLx111VRx
OUT [N]
IN [N]
GND
DT
LOS
0.1mF
Vdd
DE-A DE-B
IN [P]
0.1mF
0.1mF
OUT [P]
ISL35111
QLx111VTx
IN [N]
TDSBL GND
OUT [N]
DT
FIGURE 1. TYPICAL CABLE APPLICATION DIAGRAM
July 19, 2012
FN6975.2
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2009, 2010, 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL35111
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL35111DRZ-TS
5111
0 to +85
16 Ld QFN (7’’ 100 pcs.)
L16.3x3B
ISL35111DRZ-T7
5111
0 to +85
16 Ld QFN (7” 1k pcs.)
L16.3x3B
NOTES:
1. “-TS” and “-T7” suffix is for Tape and Reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL35111. For more information on MSL please see techbrief TB363.
Pin Configuration
GND
DT
LOS
GND
ISL35111
(16 LD QFN)
TOP VIEW
16
15
14
13
VDD 1
12 VDD
IN[P] 2
11 OUT[P]
EPAD
10 OUT[N]
IN[N] 3
TDSBL 4
5
6
7
8
GND
DEA
DEB
GND
9
VDD
Pin Descriptions
PIN NAME
PIN NUMBER
DESCRIPTION
VDD
1, 9, 12
IN[P,N]
2, 3
Driver differential input, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least 6GHz frequency response
is recommended.
TDSBL
4
Transmit Disable pin. Disables the IC and enters a low power mode when pulled HIGH. Must be externally pulled LOW
for normal operation.
GND
5, 8, 13, 16
DE[A,B]
6, 7
OUT[N,P]
10, 11
LOS
14
LOS indicator. High output when Input signal is below DT threshold.
DT
15
Detection Threshold. Reference DC voltage threshold for input signal power detection. Data output OUT[P,N] is muted
when the power of the input signal IN[P,N] falls below the threshold. Tie to ground to disable electrical idle
preservation and always enable the output driver.
Exposed Pad
-
Exposed pad. For proper electrical and thermal performance, this pad should be connected to the PCB ground plane.
Power supply. 1.2V supply voltage. The use of parallel 100pF and 47nF decoupling capacitors to ground is
recommended for each of these pins for broad high-frequency noise suppression.
These pins must be grounded.
Control pins for setting de-emphasis. CMOS logic inputs. Pins are read as a 2-digit number to set the de-emphasis
level. A is the MSB, and B is the LSB. Pins are internally pulled up and down through 23kΩ resistors.
Driver differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least 6GHz frequency
response is recommended.
2
FN6975.2
July 19, 2012
ISL35111
Absolute Maximum Ratings
Thermal Information
Supply Voltage (VDD to GND). . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 1.5V
Voltage at All Input Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 1.5V
ESD Rating
High-Speed Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5kV (HBM)
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV (HBM)
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
16 Ld QFN Package (Notes 4, 5) . . . . . . . .
56
10
Operating Ambient Temperature Range . . . . . . . . . . . . . . . . 0°C to +85°C
Storage Ambient Temperature Range . . . . . . . . . . . . . . . .-55°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+125°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTE:
4. θJA measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief
TB379.
5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Operating Conditions
PARAMETER
SYMBOL
Supply Voltage
MIN
TYP
MAX
UNITS
VDD
1.1
1.2
1.3
V
TA
0
25
85
°C
1
10
11.1
Gbps
Operating Ambient Temperature
Bit Rate
CONDITION
NRZ data applied to any channel
Control Pin Characteristics
PARAMETER
VDD = 1.2V, TA = +25°C, and VIN = 600mVP-P, unless otherwise noted.
SYMBOL
Input LOW Logic Level
MIN
MAX
(Note 12) TYP (Note 12) UNITS
CONDITION
VIL
TDSBL
0
Input HIGH Logic Level
VIH
TDSBL
750
Output LOW Logic Level
VOL
LOS
0
Output HIGH Logic Level
VOH
LOS
1000
Input Current
Current draw on DC control pin, i.e., DE[A,B]
Electrical Characteristics
PARAMETER
350
VDD
mV
0
250
mV
VDD
mV
100
µA
30
IDD
CONDITION
MIN
(Note 12)
TYP
MAX
(Note 12) UNITS NOTES
De-Emphasis Disabled
65
mA
De-Emphasis Enabled
75
mA
Transmit Disable Mode
1.4
mA
Measured differentially at data source
120
1600
mVP-P
DC Differential Input Resistance
Measured on input channel IN[P,N]
80
100
120
Ω
DC Single-Ended
Input Resistance
Measured on input channel IN[P] or IN[N], with respect
to VDD.
40
50
60
Ω
Input Amplitude Range
VIN
Input Return Loss Limit
(Differential)
SDD11
Input Return Loss Limit (Diff. to
Comm. Conversion)
SCD11
Output Amplitude Range
VOUT
Differential Output Impedance
3
mV
VDD = 1.2V, TA = +25°C, and VIN = 600mVP-P, unless otherwise noted.
SYMBOL
Supply Current
0
100MHz to 4.1GHz
See 6
dB
6
4.1GHz to 11.1GHz
See 7
dB
7
100MHz to 11.1GHz
-10
dB
8
Measured differentially at OUT[P] and OUT[N] with
50Ω load on both output pins; de-emphasis disabled
450
700
820
mVP-P
Measured on OUT[k]
80
105
120
Ω
FN6975.2
July 19, 2012
ISL35111
Electrical Characteristics
PARAMETER
VDD = 1.2V, TA = +25°C, and VIN = 600mVP-P, unless otherwise noted. (Continued)
SYMBOL
CONDITION
MIN
(Note 12)
TYP
MAX
(Note 12) UNITS NOTES
Output Return Loss Limit
(Differential)
SDD22
100MHz to 4.1GHz
See 6
dB
6
4.1GHz to 11.1GHz
See 7
dB
7
Output Return Loss Limit
(Common Mode)
SCC22
100MHz to 2.5GHz
See 9
dB
9
2.5GHz to 11.1GHz
-3
dB
8
11.1Gbps; no channel attenuation; de-emphasis
disabled
0.1
UI
10
0.7
psRMS
35
ps
Minimum De-Emphasis Level
0
dB
Maximum De-Emphasis Level
4
dB
0.5
dB
Residual Deterministic Jitter
Random Jitter
Output Transition Time
tr, tf
20% to 80%
De-Emphasis Resolution
11
NOTES:
6. Maximum Reflection Coefficient given by equation SDDXX(dB)= -12 + 2*√(f ), with f in GHz. Established by characterization and not production tested.
7. Maximum Reflection Coefficient given by equation SDDXX(dB)= -6.3 + 13Log10(f/5.5), with f in GHz. Established by characterization and not
production tested.
8. Limits established by characterization and are not production tested.
9. Reflection Coefficient given by equation SCCXX(dB) < -7 + 1.6*f, with f in GHz. Established by characterization and not production tested.
10. Measured using a PRBS 215-1 pattern.
11. Rise and fall times measured using a 2GHz clock with a 20ps edge rate and with de-emphasis disabled.
12. Compliance to limits is assured by characterization and design.
Typical Performance Characteristics
Performance is measured using the test setup illustrated in Figure 2. The signal from the pattern generator is launched into the chip
evaluation board. The ISL35111 output signal is then visualized on a scope to determine signal integrity parameters such as jitter.
P a tte r n
G e n e ra to r
IS L 3 5 1 1 1 E v a l
B o a rd
O s c illo s c o p e
FIGURE 2. DEVICE CHARACTERIZATION TEST SETUP
3A. DE-EMPHASIS 0
3B. DE-EMPHASIS 6
FIGURE 3. ISL35111 10.3125Gbps OUTPUT; NO CHANNEL; PRBS-31
4
FN6975.2
July 19, 2012
ISL35111
Typical Performance Characteristics (Continued)
DEB
DEA
FIGURE 4. ISL35111 10.3125 GBPS OUTPUT AFTER A 22-INCH FR-408 TRACE, PRBS-31; DE-EMPHASIS 6
TDSBL
Adjustable
De-Emphasis
Limiting
Amplifier
IN[P]
PreDriver
IN[N]
DT
Output
Driver
Signal
Detector
OUT[P]
OUT[N]
LOS
FIGURE 5. FUNCTIONAL BLOCK DIAGRAM OF THE ISL35111
Operation
The ISL35111 is an advanced driver for high-speed
interconnects. A functional diagram of ISL35111 is shown in
Figure 5. In addition to a de-emphasis circuit to compensate for
FR4 channel loss and restore signal fidelity, the ISL35111
contains unique integrated features to preserve special signaling
protocols typically broken by other drivers. The signal detect
function is used to mute the channel output when the input
signal falls below the level determined by the Detection
Threshold (DT) pin voltage. This function is intended to preserve
periods of line silence.
5
As illustrated in Figure 5, the core of the high-speed signal path
in the ISL35111 is a sophisticated driver followed by a
de-emphasis circuit. The device applies pre-distortion to
compensate for skin loss, dielectric loss, and impedance
discontinuities in the transmission channel.
CML Input and Output Buffers
The input and output buffers for the high-speed data channel in
the ISL35111 are implemented using CML. Equivalent input and
output circuits are shown in Figures 6 and 7.
FN6975.2
July 19, 2012
ISL35111
Adjustable De-Emphasis
V DD
ISL35111 features a settable de-emphasis driver for custom
signal restoration.
IN[P]
The connectivity of the DE pins are used to determine the boost
de-emphasis level of ISL35111. Table 1 defines the mapping
from the 2-bit non-binary DE word to the 7 available output
de-emphasis levels.
50O
Ω
2kO
Ω
TABLE 1. MAPPING BETWEEN DE-EMPHASIS LEVEL AND DE-PIN
CONNECTIVITY
10kO
Ω
50O
Ω
1st LA
Stage
IN[N]
FIGURE 6. CML INPUT EQUIVALENT CIRCUIT FOR THE ISL35111
VDD
Ω
50O
50O
Ω
DE PIN CONNECTION
DE[A]
DE[B]
NOMINAL DE-EMPHASIS
LEVEL; 10.3125Gbps TO
11.1Gbps (dB)
Open
Open
0
0
Open
GND
0.6
1
Open
VDD
1.1
2
GND
Open
1.6
3
GND
GND
2.3
4
GND
VDD
3
5
VDD
Open
4
6
DE-EMPHASIS
SETTING
Disable Pin
OUT[P]
OUT[N]
The disable (TDSBL) pin is used to disable the driver output in
order to implement TX_Disable functions of such industry
standards as SFP+ and QSFP. When this pin is pulled HIGH, the
ISL35111 will enter a low-power standby mode. For active data
transmission, this pin must be pulled LOW.
Line Silence/Quiescent Mode
FIGURE 7. CML OUTPUT EQUIVALENT CIRCUIT FOR THE ISL35111
6
The ISL35111 is capable of maintaining periods of line silence by
monitoring its input pins for loss of signal (LOS) conditions and
subsequently muting the output driver when such a condition is
detected. A reference voltage applied to the detection threshold
(DT) pin is used to set the LOS threshold of the internal signal
detection circuitry. For most applications, it is recommended to
leave the DT pin floating at its default internal bias. If the
sensitivity of the detection threshold needs to be adjusted, the DT
voltage can be adjusted with an external pull-up resistor. The
resistor values should be validated on an application-specific
basis. Connect the DT pin to ground in order to disable this
feature and prevent the outputs from muting during line silence.
FN6975.2
July 19, 2012
ISL35111
Application Information
The typical application schematic for ISL35111 is shown in Figure 8.
13
GND
14
DT
LOS
1
GND
1.2V
15
LOS (output)
16
DT
1.2V
VDD
VDD 12
IN_P
OUT_P 11
100nF
100nF
2
INPUT SIGNAL
3
IN_N
OUTPUT SIGNAL
ISL35111
OUT_N 10
1.2V
100nF
GND
8
DEB
7
DEA
GND
5
100nF
VDD 9
TDSBL
6
4
TDSBL
47nF
100pF
DEA
DEB
NOTES:
12. See “Adjustable De-Emphasis” on page 6 for information on how to connect the DE pins
13. See “Line Silence/Quiescent Mode” on page 6 for details on DT pin operation.
14. Although the filtering network is shown only for one VDD pin for simplicity, all the VDD pins need to be connected in this way.
FIGURE 8. TYPICAL APPLICATION REFERENCE SCHEMATIC FOR ISL35111
PCB Layout Considerations
Because of the high speed of the ISL35111 signals, careful PCB
layout is critical to maximize performance. The following
guidelines should be adhered to as closely as possible:
• All high speed differential pair traces should have a
characteristic impedance of 50Ω with respect to ground plane
and 100Ω with respect to each other.
• Avoid using vias for high speed traces as this will create
discontinuity in the traces characteristic impedance.
• Input and output traces need to have DC blocking capacitors
(100nF). Capacitors should be placed as close to the chip as
possible.
• For each differential pair, the positive trace and the negative
trace need to be of same length in order to avoid intra-pair
skew. Serpentine technique may be used to match trace
lengths.
• Maintain a constant solid ground plane underneath the
high-speed differential traces
and the bypass capacitors in order to maximize the power
supply noise rejection.
About Q:ACTIVE®
Intersil has long realized that to enable the complex server
clusters of next generation datacenters, it is critical to manage
the signal integrity issues of electrical interconnects. To address
this, Intersil has developed its groundbreaking Q:ACTIVE®
product line. By integrating its analog ICs inside cabling
interconnects, Intersil is able to achieve unsurpassed
improvements in reach, power consumption, latency, and cable
gauge size as well as increased airflow in tomorrow's
datacenters. This new technology transforms passive cabling into
intelligent "roadways" that yield lower operating expenses and
capital expenditures for the expanding datacenter.
Intersil Lane Extenders allow greater reach over existing cabling
while reducing the need for thicker cables. This significantly
reduces cable weight and clutter, increases airflow, and improves
power consumption.
• Each VDD pin should be connected to 1.2V and also bypassed
to ground through a 47nF and a 100pF capacitor in parallel.
Minimize the trace length and avoid vias between the VDD pin
7
FN6975.2
July 19, 2012
ISL35111
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest Rev.
DATE
REVISION
CHANGE
July 12, 2012
FN6975.2
On page 1, Column 1, changed the last paragraph from:
"Operating on a single 1.2V power supply, the ISL36111 enables channel throughputs of 10Gb/s to 11.1Gb/s
while supporting lower data rates including 8.5, 6.25, 5, 4.25, 3.125 and 2.5Gb/s. The QLX111VTX.."
to:
"Operating on a single 1.2V power supply, the ISL36111 enables channel throughputs of 10Gb/s to 11.1Gb/s
while supporting lower data rates including 8.5, 6.25, 5, 4.25, 3.125, 2.5 and 1 Gb/s. The ISL35111.."
“Operating Conditions” on page 3, added Min Entry of 1Gbps for “Bit Rate”.
Added Note 12 to MIN and MAX columns of spec tables.
January 27, 2010
FN6975.1
1. Updated pin description for DE[A,B].
2. Added Application Information, Figure 8, and PCB Layout section.
3. Changed VDD pin description to read “..and 47nF..”
4. Replaced Figure 5.
5. Corrected pin description for DE pin to read “..as a 2-digit number..”.
November 19, 2009
FN6975.0
Initial Release to web
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on
intersil.com: ISL35111
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
8
FN6975.2
July 19, 2012
ISL35111
Package Outline Drawing
L16.3x3B
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 4/07
4X 1.5
3.00
12X 0.50
A
B
6
PIN 1
INDEX AREA
6
PIN #1 INDEX AREA
16
13
12
3.00
1
1 .70
+ 0.10
- 0.15
4
9
0.15
(4X)
5
8
0.10 M C A B
+ 0.07
4 16X 0.23 - 0.05
TOP VIEW
16X 0.40 ± 0.10
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
C
0 . 90 ± 0.1
BASE PLANE
SEATING PLANE
0.08 C
( 2. 80 TYP )
SIDE VIEW
(
1. 70 )
( 12X 0 . 5 )
( 16X 0 . 23 )
C
0 . 2 REF
5
0 . 00 MIN.
0 . 05 MAX.
( 16X 0 . 60)
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
9
FN6975.2
July 19, 2012
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