DATASHEET

OD U C T
ETE PR EMENT PART
OB S OL
L AC
ED REP
D
N
E
M
1
RECOM
ISL3641
QLx411GRx
Features
The QLx411GRx is a settable quad receive-side equalizer
with extended functionality for advanced protocols
operating with line rates up to 11.3Gb/s such as
InfiniBand (SDR, DDR and QDR) and 40G Ethernet
(40GBase-CR4). The QLx411GRx compensates for the
frequency dependent attenuation of copper twin-axial
cables, extending the signal reach up to at least 10m on
28AWG cable.
• Supports data rates up to 11.3Gb/s
The small form factor, highly-integrated quad design is
ideal for high-density data transmission applications
including active copper cable assemblies. The four
equalizing filters within the QLx411GRx can each be set
to provide optimal signal fidelity for a given media and
length. The compensation level for each filter is set by
two external control pins.
• Supports 64b/66b encoded data – long run lengths
Operating on a single 1.2V power supply, the QLx411GRx
enables per channel throughputs of 10Gb/s to 11.3Gb/s
while supporting lower data rates including 8.5, 6.25, 5,
4.25, 3.125, and 2.5Gb/s. The QLx411GRx uses current
mode logic (CML) inputs/outputs and is packaged in a
4mmx7mm 46 lead QFN. Individual lane LOS support is
included for module applications.
• Low power (135mW per channel)
• Low latency (<500ps)
• Four equalizers in a 4mmx7mm QFN package for
straight route-through architecture and simplified
routing
• Each equalizer boost is independently pin selectable
• Line silence preservation
• 1.2V supply voltage
• Individual lane LOS support
Applications
• QSFP active copper cable modules
• InfiniBand SDR, DDR and QDR
• 40G Ethernet (40GBase-CR4)
• XAUI and RXAUI
• High-speed active cable assemblies
• High-speed printed circuit board (PCB) traces
Benefits
• Thinner gauge cable
• Extends cable reach greater than 3x
• Improved BER
Typical Application Circuit
Active Copper Cable Assembly
1.2V
Host Channel
Adapter
10nF
12
4
100pF
VDD EP CP LOS
1.2V
10nF
4
0.1μF
OUT1[P,N]
IN1[P,N]
OUT2[P,N]
IN2[P,N]
0.1μF
0.1μF
0.1μF
OUT4[P,N]
0.1μF
IN3[P,N]
IN4[P,N]
Fabric Switch
November 19, 2009
FN6989.1
100pF
DT
Connector Paddle Card
1
0.1μF
1.2V
0.1μF
1.2V
≤ 10m 28AWG
10nF
Rx4[P,N]
OUT3[P,N]
OUT2[P,N]
0.1μF
0.1μF
Rx1[P,N]
Rx2[P,N]
QLx411GRx
QLx411GRx
0.1μF
IN2[P,N]
OUT1[P,N]
0.1μF
0.1μF
Rx3[P,N]
IN1[P,N]
IN3[P,N]
IN4[P,N]
OUT3[P,N]
OUT4[P,N]
DT
0.1μF
0.1μF
Rx3[P,N]
Rx4[P,N]
Tx1[P,N]
Tx2[P,N]
Tx3[P,N]
Tx4[P,N]
10nF
SERDES or Switch
0.1μF
0.1μF
8-Pair Differential 100Ω
Twin-Axial Cable
SERDES or Switch
Rx2[P,N]
100pF
LOS CP EP VDD
Tx4[P,N]
Rx1[P,N]
12
100pF
Tx1[P,N]
Tx2[P,N]
Tx3[P,N]
Connector Paddle Card
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
QLx411GRx
Quad Lane Extender
QLx411GRx
Ordering Information
PART NUMBER
(Note)
TEMP. RANGE
(°C)
PART MARKING
PACKAGE
(Pb-Free)
PKG. DWG. #
QLX411RIQT7
QLX411RIQ
0 to +70
46 Ld QFN
7” Prod. Tape & Reel; Qty 1,000
L46.4x7
QLX411RIQSR
QLX411RIQ
0 to +70
46 Ld QFN
7” Sample Reel; Qty 100
L46.4x7
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach
materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering
operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
Pin Configuration
CP2[A]
CP2[B]
CP1[B]
NC
CP1[A]
NC
NC
NC
QLx411GRx
(46 LD 4x7 QFN)
TOP VIEW
46 45 44 43 42 41 40 39
DT
1
38 NC
IN1[P]
2
37 OUT1[P]
IN1[N]
3
36 OUT1[N]
VDD
4
35 VDD
IN2[P]
5
34 OUT2[P]
IN2[N] 6
33 OUT2[N]
VDD 7
32 VDD
EXPOSED PAD
(GND)
IN3[P] 8
31 OUT3[P]
IN3[N] 9
30 OUT3[N]
VDD 10
29 VDD
IN4[P] 11
28 OUT4[P]
IN4[N] 12
27 OUT4[N]
LOS1 13
26 LOS3
LOS2 14
25 LOS4
NC 15
24 GND
2
CP4[B]
CP4[A]
NC
CP3[B]
CP3[A]
NC
NC
NC
16 17 18 19 20 21 22 23
FN6989.1
November 19, 2009
QLx411GRx
Pin Descriptions
PIN NAME
PIN NUMBER
DT
1
IN1[P,N]
2, 3
VDD
DESCRIPTION
Detection Threshold. Reference DC voltage threshold for input signal power detection. Data
output OUT[k] is muted when the power of the equalized version of IN[k] falls below the
threshold. Tie to ground to disable electrical idle preservation and always enable the limiting
amplifier.
Equalizer 1 differential input, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
6GHz frequency response is recommended.
4, 7, 10, 29, 32, Power supply. 1.2V supply voltage. The use of parallel 100pF and 10nF decoupling capacitors to
35
ground is recommended for each of these pins for broad high-frequency noise suppression.
IN2[P,N]
5, 6
Equalizer 2 differential input, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
6GHz frequency response is recommended.
IN3[P,N]
8, 9
Equalizer 3 differential input, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
6GHz frequency response is recommended.
IN4[P,N]
11, 12
Equalizer 4 differential input, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
6GHz frequency response is recommended.
LOS1
13
LOS indicator 1. High output when equalized IN1 signal is below DT threshold.
LOS2
14
LOS indicator 2. High output when equalized IN2 signal is below DT threshold.
NC
15, 16, 18, 21,
38, 41, 44, 45,
46
CP3[A,B,]
19, 20
Control pins for setting equalizer 3. CMOS logic inputs. Pins are read as a 3-digit number to set
the boost level. A is the MSB, and B is the LSB. Pins are internally pulled down through a 25k
resistor.
CP4[A,B,]
22, 23
Control pins for setting equalizer 4. CMOS logic inputs. Pins are read as a 3-digit number to set
the boost level. A is the MSB, and B is the LSB. Pins are internally pulled down through a 25k
resistor.
GND
24
This pin should be grounded.
LOS4
25
LOS indicator 4. High output when equalized IN1 signal is below DT threshold.
LOS3
26
LOS indicator 3. High output when equalized IN2 signal is below DT threshold.
OUT4[N,P]
27, 28
Equalizer 4 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
6GHz frequency response is recommended.
OUT3[N,P]
30, 31
Equalizer 3 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
6GHz frequency response is recommended.
OUT2[N,P]
33, 34
Equalizer 2 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
6GHz frequency response is recommended.
OUT1[N,P]
36, 37
Equalizer 1 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
6GHz frequency response is recommended.
CP2[B,A]
39, 40
Control pins for setting equalizer 2. CMOS logic inputs. Pins are read as a 3-digit number to set
the boost level. A is the MSB, and B is the LSB. Pins are internally pulled down through a 25k
resistor.
CP1[B,A]
42, 43
Control pins for setting equalizer 1. CMOS logic inputs. Pins are read as a 3-digit number to set
the boost level. A is the MSB, and B is the LSB. Pins are internally pulled down through a 25k
resistor.
EXPOSED
PAD
-
Not connected: Do not make any connections to these pins.
Exposed ground pad. For proper electrical and thermal performance, this pad should be
connected to the PCB ground plane.
3
FN6989.1
November 19, 2009
QLx411GRx
Absolute Maximum Ratings
Thermal Information
Supply Voltage (VDD to GND) . . . . . . . . . . . . -0.3V to 1.3V
Voltage at All Input Pins . . . . . . . . . . . -0.3V to VDD + 0.3V
ESD Rating at All Pins . . . . . . . . . . . . . . . . . . . . 2kV (HBM)
Operating Ambient Temperature Range . . . . . . 0°C to +70°C
Storage Ambient Temperature Range . . . . -55°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . +125°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
Operating Conditions
PARAMETER
SYMBOL
Supply Voltage
Operating Ambient Temperature
MIN
TYP
MAX
UNITS
VDD
1.1
1.2
1.3
V
TA
0
25
70
°C
11.3
Gb/s
Bit Rate
CONDITION
NRZ data applied to any channel
2.5
Control Pin Characteristics Typical values are at VDD = 1.2V, TA = +25°C, and VIN = 600mVP-P, unless otherwise
noted. VDD = 1.1V to 1.3V, TA = 0°C to +70°C.
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
0
250
mV
VDD
mV
100
µA
Output LOW Logic Level
VOL
LOS[k]
0
Output HIGH Logic Level
VOH
LOS[k]
1000
Input Current
Current draw on digital pin, i.e., CP[k][A,B]
Electrical Specifications
PARAMETER
Typical values are at VDD = 1.2V, TA = +25°C, and VIN = 600mVP-P, unless otherwise noted.
VDD = 1.1V to 1.3V, TA = 0°C to +70°C.
SYMBOL
Supply Current
IDD
Cable Input
Amplitude Range
VIN
30
CONDITION
MIN
TYP
MAX
360
Measured differentially at data source before
encountering channel loss
UNITS
NOTES
mA
600
1200
1600
mVP-P
DC Differential
Input Resistance
Measured on input channel IN[k]
80
100
120

DC Single-Ended
Input Resistance
Measured on input channel IN[k]P or IN[k]N
40
50
60

1
Input Return Loss
(Differential)
SDD11
100MHz to 7.5GHz
8
dB
2
Input Return Loss
(Common Mode)
SCC11
100MHz to 7.5GHz
8
dB
2
Input Return Loss
(Com. to Diff.
Conversion)
SDC11
100MHz to 7.5GHz
20
dB
2
Output
Amplitude Range
VOUT
Differential
Output Impedance
Measured differentially at OUT[k]P and
OUT[k]N with 50 load on both output pins
Measured on OUT[k]
450
600
650
mVP-P
80
105
120

Output Return Loss
(Differential)
SDD22
100MHz to 7.5GHz
8
dB
2
Output Return Loss
(Common Mode)
SCC22
100MHz to 7.5GHz
8
dB
2
Output Return Loss
(Com. to Diff.
Conversion)
SDC22
100MHz to 7.5GHz
20
dB
2
4
FN6989.1
November 19, 2009
QLx411GRx
Electrical Specifications
PARAMETER
SYMBOL
Output Residual Jitter
Output Transition Time
Typical values are at VDD = 1.2V, TA = +25°C, and VIN = 600mVP-P, unless otherwise noted.
VDD = 1.1V to 1.3V, TA = 0°C to +70°C. (Continued)
CONDITION
10Gb/s; Up to 10m 28AWG standard
twin-axial cable (approx. -27dB @ 5GHz);
1200mVP-P  VIN  1600mVP-P
tr, tf
20% to 80%
Lane-to-Lane Skew
MIN
TYP
MAX
UNITS
NOTES
0.25
UI
1, 3, 4
35
ps
5
50
ps
500
ps
Propagation Delay
From IN[k] to OUT[k]
LOS Assert Time
Time to assert Loss-of-Signal (LOS) indicator
when transitioning from active data mode to
line silence mode
50
µs
6
LOS De-Assert Time
Time to de-assert Loss-of-Signal (LOS)
indicator when transitioning from line silence
mode to active data mode
50
µs
6
Data-to-Line Silence
Response Time
Time to transition from active data to line
silence (muted output) on 20m 28AWG
standard twin-axial cable at 5Gb/s
50
µs
6
Line Silence-to-Data
Response Time
Time to transition from line silence mode
(muted output) to active data on 20m 28AWG
standard twin-axial cable at 5Gb/s
50
µs
6
NOTES:
1. After channel loss, differential amplitudes at QLx411GRx inputs must meet the input voltage range specified in “Absolute
Maximum Ratings” on page 4.
2. Temperature = +25°C, VDD = 1.2V.
3. Output residual jitter is the difference between the total jitter at the lane extender output and the total jitter of the transmitted
signal (as measured at the input to the channel). Total jitter (TJ) is DJpp + 14.1 x RJRMS.
4. Measured using a PRBS 27-1 pattern. Deterministic jitter at the input to the lane extender is due to frequency-dependent,
media-induced loss only.
5. Rise and fall times measured using a 1GHz clock with a 20ps edge rate.
6. For active data mode, cable input amplitude is 300mVP-P (differential) or greater. For line silence mode, cable input amplitude
is 20mVP-P (differential) or less.
5
FN6989.1
November 19, 2009
QLx411GRx
Typical Performance Characteristics
Performance is measured using the test setup illustrated in Figure 1. The signal from the pattern generator is launched
into the twin-ax cable using an SMA/CX4 adapter card. The chip evaluation board is connected to the output of the
cable through another adapter card. The QLx411GRx output signal is then visualized on a scope to determine signal
integrity parameters such as jitter (Note 7).
Pattern
Generator
SMA
Adapter
Card
100Ω Twin-Axial
Cable
SMA
Adapter
Card
QLx411GRx
Eval Board
Oscilloscope
FIGURE 1. DEVICE CHARACTERIZATION SET UP
FIGURE 2. JITTER vs CABLE LENGTH AT 10Gb/s
(BOOST LEVELS 0-3)
FIGURE 3. QLx411GRx 10Gb/s OUTPUT FOR A 10M
28AWG CABLE
NOTE:
7. Prior to the tapeout, the data in Figures 2 and 3 represents simulations approximating the conditions of setup in Figure 1, not
measured data.
6
FN6989.1
November 19, 2009
QLx411GRx
FIGURE 4. FUNCTIONAL DIAGRAM OF A SINGLE CHANNEL WITHIN THE QLx411GRx
Operation
The QLx411GRx is an advanced quad lane-extender for
high-speed interconnects. A functional diagram of one of
the four channels in the QLx411GRx is shown in Figure 4.
In addition to a robust equalization filter to compensate
for channel loss and restore signal fidelity, the
QLx411GRx contains unique integrated features to
preserve special signaling protocols typically broken by
other equalizers. The signal detect function is used to
mute the channel output when the equalized signal falls
below the level determined by the Detection Threshold
(DT) pin voltage. This function is intended to preserve
periods of line silence (“quiescent state” in InfiniBand
contexts). Furthermore, the output of the signal
detect/DT comparator is used as a loss of signal (LOS)
indicator to indicate the absence of a received signal.
As illustrated in Figure 4, the core of each high-speed
signal path in the QLx411GRx is a sophisticated equalizer
followed by a limiting amplifier. The equalizer
compensates for skin loss, dielectric loss, and impedance
discontinuities in the transmission channel. Each
equalizer is followed by a limiting amplification stage that
provides a clean output signal with full amplitude swing
and fast rise-fall times for reliable signal decoding in a
subsequent receiver.
Individually Adjustable Equalization Boost
Each channel in the QLx411GRx features an
independently settable equalizer for custom signal
restoration. The flexibility of this adjustable
compensation architecture enables signal fidelity to be
optimized on a channel-by-channel basis, providing
support for a wide variety of channel characteristics and
data rates ranging from 2.5Gb/s to 11.3Gb/s. Because
the boost level is externally set rather than internally
adapted, the QLx411GRx provides reliable
communication from the very first bit transmitted. There
is no time needed for adaptation and control loop
convergence. Furthermore, there are no pathological
data patterns that will cause the QLx411GRx to move to
an incorrect boost level.
7
FIGURE 5. GAIN PROFILE FOR VARIOUS BOOST
SETTINGS IN QLx411GRx
Control Pin Boost Setting
The connectivity of the CP pins is used to determine the
boost level of each channel. Table 1 defines the mapping
from the 2-bit CP word to the 5 possible boost levels.
TABLE 1. MAPPING BETWEEN BOOST LEVEL AND CPPIN CONNECTIVITY
CP[A]
CP[B]
BOOST LEVEL
25k
25k
0
25k
Open
1
25k
0
2
Open
25k
3
Open
Open
4
FN6989.1
November 19, 2009
QLx411GRx
CML Input and Output Buffers
Line Silence/Quiescent Mode
The input and output buffers for the high-speed data
channels in the QLx411GRx are implemented using CML.
Equivalent input and output circuits are shown in
Figures 6 and 7.
Line silence is commonly broken by the limiting
amplification in other equalizers. This disruption can be
detrimental in many systems that rely on line silence as
part of the protocol. The QLx411GRx contains special
lane management capabilities to detect and preserve
periods of line silence while still providing the fidelityenhancing benefits of limiting amplification during active
data transmission. Line silence is detected by measuring
the amplitude of the equalized signal and comparing that
to a threshold set by the voltage at the DT pin. When the
amplitude falls below the threshold, the output driver
stages are muted and held at their nominal common
mode voltage1.
VDD
IN[k] P
50Ω
Buffer
50Ω
IN[k] N
FIGURE 6. CML INPUT EQUIVALENT CIRCUIT FOR
THE QLx411GRx
LOS Indicator
Pins LOS[k] are used to output the state of the muting
circuitry to serve as a loss of signal indicator for channel
k. This signal is directly derived from the muting signal
off the DT-threshold signal detector output. The LOS
signal goes HIGH when the power signal is below the DT
threshold and LOW when the power goes above the DT
threshold. This feature is meant to be used in optical
systems (e.g. QSFP) where there are no quiescent or
electrical-idle states. In these cases, the DT threshold is
used to determine the sensitivity of the LOS indicator.
VDD
50Ω
50Ω
OUT[k] P
OUT[k] N
FIGURE 7. CML OUTPUT EQUIVALENT CIRCUIT FOR
THE QLx411GRx
1. The output common mode voltage remains constant during both active data transmission and output muting modes
8
FN6989.1
November 19, 2009
QLx411GRx
Typical Application Reference Design
Figure 8 shows reference design schematics for a QLx411GRx evaluation board with an SMA connector interface.
100pF*
10nF
1.2V
CP2[B]
CP2[A]
CP1[B]
43
40
NC
44
39
34
7
32
8
31
9
30
10
29
11
28
12
27
13
26
14
25
15
24
OUT1[P]
OUT1[N]
1.2V
OUT2[P]
OUT2[N]
1.2V
OUT3[P]
OUT3[N]
1.2V
OUT4[P]
OUT4[N]
LOS3
LOS4
GND
CP4[B]
EQ Boost Control
for Channels 3 and 4
= SMA Connector
Bypass circuit for each VDD pin: 4, 7, 10, 29, 32, 35
(*100pF capacitor should be positioned closest to the pin)
Loss of signal indicator (Channels 3 and 4)
23
33
22
6
CP3[A]
Loss of signal indicator (Channels 1 and 2)
QLx411GRx
5
21
LOS2
35
CP4[A]
LOS1
4
20
IN4[N]
36
CP3[B]
1.2V
IN4[P]
41
NC
45
CP1[A]
IN3[P]
IN3[N]
3
19
1.2V
37
18
IN2[P]
IN2[N]
2
17
1.2V
A
38
NC
IN1[N]
42
NC
EQ Boost Control
for Channels 1 and 2
1
NC
IN1[P]
16
DT
NC
10nF
100pF
Detection threshold
reference voltage
46
1.2V
A) DC Blocking Capacitors = X7R or COG
0.1µF (>6GHz bandwidth)
QLx411GRx
LANE EXTENDER
Reference
Control Pin Mode
Quellan, Inc.
FIGURE 8. APPLICATION CIRCUIT FOR THE QLx411GRx EVALUATION BOARD SHOWING THE USE OF THE CONTROL
PINS FOR SETTING THE EQUALIZER COMPENSATION LEVEL
9
FN6989.1
November 19, 2009
QLx411GRx
About Q:ACTIVE®
Intersil has long realized that to enable the complex
server clusters of next generation datacenters, it is
critical to manage the signal integrity issues of electrical
interconnects. To address this, Intersil has developed its
groundbreaking Q:ACTIVE® product line. By integrating
its analog ICs inside cabling interconnects, Intersil is able
to achieve unsurpassed improvements in reach, power
consumption, latency, and cable gauge size as well as
increased airflow in tomorrow’s datacenters. This new
technology transforms passive cabling into intelligent
“roadways” that yield lower operating expenses and
capital expenditures for the expanding datacenter.
Intersil Lane Extenders allow greater reach over existing
cabling while reducing the need for thicker cables. This
significantly reduces cable weight and clutter, increases
airflow, and improves power consumption.
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications
at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by
Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any
patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
10
FN6989.1
November 19, 2009
QLx411GRx
Package Outline Drawing
L46.4x7
46 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE (TQFN)
Rev 0, 9/09
2.80
4.00
42X 0.40
A
B
6
PIN 1
INDEX AREA
38
7.00
(4X)
46
39
6
PIN 1
INDEX AREA
1
5.50 ±0.1
Exp. DAP
5.60
15
24
0.05
46X 0.20 4
0.10 M C A B
SIDE VIEW
TOP VIEW
16
23
2.50 ±0.1
Exp. DAP
46X 0.40
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
0.70 ±0.05
C
SEATING PLANE
0.05 C
SIDE VIEW
C
0.152 REF
5
0 . 00 MIN.
0 . 05 MAX.
DETAIL "X"
( 3.80 )
( 2.50)
NOTES:
( 6.80 )
( 42X 0.40)
( 5.50 )
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
(46X 0.20)
5.
Tiebar shown (if present) is a non-functional feature.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
( 46 X 0.60)
TYPICAL RECOMMENDED LAND PATTERN
11
FN6989.1
November 19, 2009
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