DATASHEET

QLx4300-S45
Features
The QLx4300-S45 is a settable quad receive-side
equalizer with extended functionality for advanced
protocols operating with line rates up to 3.125Gb/s such
as InfiniBand (SDR) and 10GBase-CX4. The
QLx4300-S45 compensates for the frequency dependent
attenuation of copper twin-axial cables, extending the
signal reach up to 40m on 24AWG cable.
The small form factor, highly-integrated quad design is
ideal for high-density data transmission applications
including active copper cable assemblies. The four
equalizing filters within the QLx4300-S45 can each be set
to one of 32 compensation levels, providing optimal
signal fidelity for a given media and length. The
compensation level for each filter can be set by either (a)
three external control pins or (b) a serial bus interface.
When the external control pins are used, 18 of the 32
boost levels are available for each channel. If the serial
bus is used, all 32 compensation levels are available.
Operating on a single 1.2V power supply, the
QLx4300-S45 enables per channel throughputs of up to
3.125Gb/s while supporting the lower data rates of
2.5Gb/s and 1.5Gb/s. The QLx4300-S45 uses current
mode logic (CML) inputs/outputs and is packaged in a
4mmx7mm 46 lead QFN. Individual lane impedance
select support is included for module applications.
• Supports data rates up to 3.125Gb/s
• Low power (78mW per channel)
• Low latency (<500ps)
• Four equalizers in a 4mmx7mm QFN package for
straight route-through architecture and simplified
routing
• Each equalizer boost is independently pin selectable
and programmable
• Beacon signal support and line silence preservation
• 1.2V supply voltage
• Individual channel power-down (impedance select)
Applications
• InfiniBand (SDR)
• 10GBase-CX4
• PCI Express (Gen 1)
• DisplayPort
• XAUI
• SAS (1.0)
• High-speed active cable assemblies
• High-speed printed circuit board (PCB) traces
Benefits
• Thinner gauge cable
• Extends cable reach greater than 3x
• Improved BER
Typical Application Circuit
QLX4300-S45
QLX4300-S45
<40M 24AWG
November 19, 2009
FN6982.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
QLx4300-S45
Quad Lane Extender
QLx4300-S45
Ordering Information
PART NUMBER
(Note)
TEMP. RANGE
(°C)
PART MARKING
PACKAGE
(Pb-Free)
PKG. DWG. #
QLX4300SIQT7
QLX4300SIQ
0 to +70
46 Ld QFN
7” Prod. Tape & Reel; Qty 1,000
L46.4x7
QLX4300SIQSR
QLX4300SIQ
0 to +70
46 Ld QFN
7” Sample Reel; Qty 100
L46.4x7
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach
materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering
operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
Pin Configuration
CP2[B]
CP2[C]
CP1[C]
CP2[A]
CP1[B]
CP1[A]
ENB
CLK
QLx4300-S45
(46 LD 4x7 QFN)
TOP VIEW
46 45 44 43 42 41 40 39
DT
1
38 BGREF
IN1[P]
2
37 OUT1[P]
IN1[N]
3
36 OUT1[N]
VDD
4
35 VDD
IN2[P]
5
34 OUT2[P]
IN2[N] 6
33 OUT2[N]
VDD 7
32 VDD
EXPOSED PAD
(GND)
IN3[P] 8
31 OUT3[P]
IN3[N] 9
30 OUT3[N]
VDD 10
29 VDD
IN4[P] 11
28 OUT4[P]
IN4[N] 12
27 OUT4[N]
IS1 13
26 IS3
IS2 14
25 IS4
GND 15
24 MODE
2
CP4[C]
CP4[B]
CP4[A]
CP3[C]
CP3[B]
CP3[A]
DO
DI
16 17 18 19 20 21 22 23
FN6982.1
November 19, 2009
QLx4300-S45
Pin Descrptions
PIN NAME
PIN NUMBER
DESCRIPTION
DT
1
IN1[P,N]
2, 3
Equalizer 1 differential input, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
4GHz frequency response is recommended.
VDD
4, 7, 10, 29,
32, 35
Power supply. 1.2V supply voltage. The use of parallel 100pF and 10nF decoupling capacitors to
ground is recommended for each of these pins for broad high-frequency noise suppression.
IN2[P,N]
5, 6
Equalizer 2 differential input, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
4GHz frequency response is recommended.
IN3[P,N]
8, 9
Equalizer 3 differential input, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
4GHz frequency response is recommended.
IN4[P,N]
11, 12
Equalizer 4 differential input, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
4GHz frequency response is recommended.
IS1
13
Impedance Select 1. CMOS logic input. When the voltage on this pin is LOW, the single-ended
input impedance of In1P and In1N each go above 200kΩ and powers down the channel. This pin
should be connected to the Fundamental Reset signal in PCI Express™. Otherwise, connect to
VDD to hold the input impedance at 50Ω.
IS2
14
Impedance Select 2. CMOS logic input. When the voltage on this pin is LOW, the single-ended
input impedance of In2P and In2N each go above 200kΩ and powers down the channel. This pin
should be connected to the Fundamental Reset signal in PCI Express™. Otherwise, connect to
VDD to hold the input impedance at 50Ω.
GND
15
Ground
DI
16
Serial data input, CMOS logic. Input for serial data stream to program internal registers
controlling the boost for all four equalizers. Synchronized with clock (CLK) on pin 46. Overrides
the boost setting established on CP control pins. Internally pulled down.
DO
17
Serial data output, CMOS logic. Output of the internal registers controlling the boost for all four
equalizers. Synchronized with clock on pin 46. Equivalent to serial data input on DI but delayed
by 21 clock cycles.
CP3[A,B,C]
18, 19, 20
Control pins for setting equalizer 3. CMOS logic inputs. Pins are read as a 3-digit number to set
the boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25kΩ
resistor.
CP4[A,B,C]
21, 22, 23
Control pins for setting equalizer 4. CMOS logic inputs. Pins are read as a 3-digit number to set
the boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25kΩ
resistor.
MODE
24
Boost-level control mode input, CMOS logic. Allows serial programming of internal registers
through pins DI, ENB, and Clk when set HIGH. Resets all internal registers to zero and uses boost
levels set by CP pins when set LOW. If serial programming is not used, this pin should be
grounded.
IS4
25
Impedance Select 4. CMOS logic input. When the voltage on this pin is LOW, the single-ended
input impedance of In4P and In4N each go above 200kΩ and powers down the channel. This pin
should be connected to the Fundamental Reset signal in PCI Express™. Otherwise, connect to
VDD to hold the input impedance at 50Ω.
IS3
26
Impedance Select 3. CMOS logic input. When the voltage on this pin is LOW, the single-ended
input impedance of In3P and In3N each go above 200kΩ and powers down the channel. This pin
should be connected to the Fundamental Reset signal in PCI Express™. Otherwise, connect to
VDD to hold the input impedance at 50Ω.
OUT4[N,P]
27, 28
Equalizer 4 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
4GHz frequency response is recommended.
OUT3[N,P]
30, 31
Equalizer 3 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
4GHz frequency response is recommended.
Detection Threshold. Reference DC current threshold for input signal power detection. Data
output OUT[k] is muted when the power of the equalized version of IN[k] falls below the
threshold. Tie to ground to disable electrical idle preservation and always enable the limiting
amplifier.
3
FN6982.1
November 19, 2009
QLx4300-S45
Pin Descrptions (Continued)
PIN NAME
PIN NUMBER
DESCRIPTION
OUT2[N,P]
33, 34
Equalizer 2 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
4GHz frequency response is recommended.
OUT1[N,P]
36, 37
Equalizer 1 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
4GHz frequency response is recommended.
BGREF
38
CP2[C,B,A]
39, 40, 41
Control pins for setting equalizer 2. CMOS logic inputs. Pins are read as a 3-digit number to set
the boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25kΩ
resistor.
CP1[C,B,A]
42, 43, 44
Control pins for setting equalizer 1. CMOS logic inputs. Pins are read as a 3-digit number to set
the boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25kΩ
resistor.
ENB
45
Serial data enable (active low), CMOS logic. Internal registers can be programmed with DI and
CLK pins only when the ENB pin is ‘LOW’. Internally pulled down.
CLK
46
Serial data clock, CMOS logic. Synchronous clock for serial data on DI and DO pins. Data on DI
is latched on the rising clock edge. Clock speed is recommended to be between 10MHz and
20MHz. Internally pulled down.
EXPOSED
PAD
-
External bandgap reference resistor. Recommended value of 6.04kΩ ±1%.
Exposed ground pad. For proper electrical and thermal performance, this pad should be
connected to the PCB ground plane.
4
FN6982.1
November 19, 2009
QLx4300-S45
Absolute Maximum Ratings
Thermal Information
Supply Voltage (VDD to GND) . . . . . . . . . . . . -0.3V to 1.3V
Voltage at All Input Pins . . . . . . . . . . . -0.3V to VDD + 0.3V
ESD Rating at All Pins . . . . . . . . . . . . . . . . . . . . 2kV (HBM)
Thermal Resistance (Typical)
θJA (°C/W) θJc (°C/W)
46 Ld QFN Package (Note 1). . . . .
32
2.3
Operating Ambient Temperature Range. . . . . . 0°C to +70°C
Storage Ambient Temperature Range . . . . . -55°C to +150°C
Maximum Junction Temperature. . . . . . . . . . . . . . . +125°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTE:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief
TB379 for details.
Operating Conditions
PARAMETER
SYMBOL
Supply Voltage
MIN
TYP
MAX
UNITS
VDD
1.1
1.2
1.3
V
TA
0
25
70
°C
3.125
Gb/s
Operating Ambient Temperature
Bit Rate
CONDITION
NRZ data applied to any channel
1.5
Control Pin Characteristics Typical values are at VDD = 1.2V, TA = +25°C, and VIN = 800mVP-P, unless otherwise
noted. VDD = 1.1V to 1.3V, TA = 0°C to +70°C.
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
0
350
mV
VDD
mV
250
mV
NOTES
Input ‘LOW’ Logic Level
VIL
DI, Clk, ENB
0
Input ‘HIGH’ Logic Level
VIH
DI, Clk, ENB
750
Output ‘LOW’ Logic Level
VOL
IS[k], DO
0
Output ‘HIGH’ Logic Level
VOH
IS[k], DO
1000
VDD
mV
0
1
kΩ
2
27.5
kΩ
2
∞
kΩ
2
100
µA
‘LOW’ Resistance State
CP[k][A,B,C]
‘MID’ Resistance State
CP[k][B,C]
22.5
‘HIGH’ Resistance State
CP[k][A,B,C]
500
Input Current
Current draw on digital pin, i.e.,
CP[k][A,B,C], DI, Clk, ENB
0
25
30
NOTE:
2. If four CP pins are tied together, the resistance values in this table should be divided by four.
Electrical Specifications
PARAMETERS
Typical values are at VDD = 1.2V, TA = +25°C, and VIN = 800mVP-P, unless otherwise noted.
VDD = 1.1V to 1.3V, TA = 0°C to +70°C.
SYMBOL
Supply Current
IDD
Cable Input Amplitude
Range
VIN
CONDITION
MIN
TYP
MAX
260
Measured differentially at data source
before encountering channel loss
UNITS NOTES
mA
800
1200
1600
mVP-P
DC Differential Input
Resistance
Measured on input channel IN[k]
80
100
120
Ω
DC Single-Ended Input
Resistance
Measured on input channel IN[k]P or
IN[k]N
40
50
60
Ω
3
Input Return Loss
(Differential)
SDD11
50MHz to 3.75GHz
10
dB
4
Input Return Loss
(Common Mode)
SCC11
50MHz to 3.75GHz
6
dB
4
5
FN6982.1
November 19, 2009
QLx4300-S45
Electrical Specifications
Typical values are at VDD = 1.2V, TA = +25°C, and VIN = 800mVP-P, unless otherwise noted.
VDD = 1.1V to 1.3V, TA = 0°C to +70°C. (Continued)
PARAMETERS
SYMBOL
Input Return Loss
(Com. to Diff. Conversion)
SDC11
Output Amplitude Range
VOUT
CONDITION
50MHz to 3.75GHz
Active data transmission mode; Measured
differentially at OUT[k]P and OUT[k]N with
50Ω load on both output pins
MIN
MAX
20
450
Line Silence mode; Measured differentially
at OUT[k]P and OUT[k]N with 50Ω load on
both output pins
Differential Output
Impedance
TYP
Measured on OUT[k]
80
UNITS NOTES
dB
550
650
mVP-P
10
20
mVP-P
105
120
Ω
4
Output Return Loss
(Differential)
SDD22
50MHz to 3.75GHz
10
dB
4
Output Return Loss
(Common Mode)
SCC22
50MHz to 3.75GHz
5
dB
4
Output Return Loss (Com.
to Diff. Conversion)
SDC22
50MHz to 3.75GHz
20
dB
4
Output Residual Jitter
3.125Gb/s; Up to 20m 24AWG standard
twin-axial cable (approx. -25dB @
2.5GHz); 800mVP-P ≤ VIN ≤ 1600mVP-P
tr, tf
Output Transition Time
0.15
0.25
UI
3, 5, 6
60
80
ps
7
50
ps
500
ps
Time to transition from active data to line
silence (muted output) on 20m 24AWG
standard twin-axial cable at 3.125Gb/s
15
ns
8, 11
Time from last bit of ALIGN(0) for SAS OOB
signaling to line silence (<20mVP-P
output); Meritec 24AWG 20m; 3.125Gb/s
14
ns
12
Time to transition from line silence mode
(muted output) to active data on 20m
24AWG standard twin-axial cable at
3.125Gb/s
20
ns
8, 11
Time from first bit of ALIGN(0) for SAS
OOB signaling to 450mVP-P output;
Meritec 24AWG 20m; 3.125Gb/s
19
ns
12
For SAS OOB signaling support; Meritec
24AWG 20m
5
ns
12
20% to 80%
Lane-to-Lane Skew
Propagation Delay
From IN[k] to OUT[k]
Data-to-Line Silence
Response Time
tDS
Line Silence-to-Data
Response Time
Timing Difference (SAS)
tSD
|tDS - tSD|
30
NOTES:
3. After channel loss, differential amplitudes at QLx4300-S45 inputs must meet the input voltage range specified in “Absolute
Maximum Ratings” on page 5.
4. Temperature = +25°C, VDD = 1.2V.
5. Output residual jitter is the difference between the total jitter at the lane extender output and the total jitter of the transmitted
signal (as measured at the input to the channel). Total jitter (TJ) is DJPP + 14.1 x RJRMS.
6. Measured using a PRBS 27-1 pattern. Deterministic jitter at the input to the lane extender is due to frequency-dependent,
media-induced loss only.
7. Rise and fall times measured using a 1GHz clock with a 20ps edge rate.
8. For active data mode, cable input amplitude is 400mVP-P (differential) or greater. For line silence mode, cable input amplitude
is 20mVP-P (differential) or less.
9. Measured differentially across the data source.
6
FN6982.1
November 19, 2009
QLx4300-S45
NOTES: (Continued)
10. During line silence, transmitter noise in excess of this voltage range may result in differential output amplitudes from the
QLx4300-S45 that are greater than 20mVP-P.
11. The data pattern preceding line silence mode is comprised of the PCIe electrical idle ordered set (EIOS). The data pattern
following line silence mode is comprised of the PCIe electrical idle exit sequence (EIES).
12. The data pattern preceding or following line silence mode is comprised of the SAS-2 ALIGN (0) sequence for OOB signaling
at 3.125Gb/s, and amplitude of 800mVP-P.
Serial Bus Timing Characteristics
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
CLK Setup Time
tSCK
From the falling edge of ENB
10
ns
DI Setup Time
tSDI
Prior to the rising edge of CLK
10
ns
DI Hold Time
tHDI
From the rising edge of CLK
6
ns
ENB ‘HIGH’
tHEN
From the falling edge of the last data bit’s CLK
10
ns
Boost Setting Operational
tD
From ENB ‘HIGH’
10
DO Hold Time
tCQ
From the rising edge of CLK to DO transition
Clock Rate
fCLK
Reference clock for serial bus EQ programming
12
ns
ns
20
MHz
Typical Performance Characteristics
VDD = 1.2V, TA = +25°C, unless otherwise noted. Performance was characterized using the system testbed shown in
Figure 1. Unless otherwise noted, the transmitter generated a non-return-to-zero (NRZ) PRBS-7 sequence at 800mVP-P
(differential) with 10ps of peak-to-peak deterministic jitter. This transmit signal was launched into twin-axial cable test
channels of varying gauges and lengths. The loss characteristics of these test channels are plotted as a function of
frequency in Figure 2. The received signal at the output of these test channels was then processed by the QLx4300-S45
before being passed to a receiver. Eye diagram measurements were made with 4000 waveform acquisitions and include
random jitter.
Pattern
Generator
SMA
Adapter
Card
SMA
Adapter
Card
Ω Twin-Axial
100O
Cable
QLx4300-S45
Eval Board
Oscilloscope
FIGURE 1. DEVICE CHARACTERIZATION TEST SETUP
TEST CHANNEL LOSS CHARACTERISTICS
0
-5
SDD21 (dB)
-10
-15
-20
-25
-30
10m
-35
15m
-40
20m
-45
25m
-50
0
1
2
3
4
5
6
Frequency (GHz)
FIGURE 2. 26 AWG TWIN-AXIAL CABLE LOSS AS A FUNCTION OF FREQUENCY FOR VARIOUS TEST CHANNELS
7
FN6982.1
November 19, 2009
QLx4300-S45
Typical Performance Characteristics (Continued)
0.35
0.3
Jitter (ps)
0.25
0.2
0.15
10m
0.1
15m
20m
0.05
25m
0
0
5
10
15
20
25
30
35
Boost Setting
FIGURE 2. JITTER VS BOOST SETTING FOR VARIOUS CABLE LENGTHS, PRBS-7, 0.03PS SYSTEM JITTER INCLUDED
60mV/div
80mV/div
OUTPUT EYE DIAGRAMS
64ps/div
64ps/div
FIGURE 4. QLx4300-S45 OUTPUT AFTER 10m OF 26AWG
TWIN-AXIAL CABLE, 3.125Gb/s
80mV/div
80mV/div
FIGURE 3. RECEIVED SIGNAL AFTER 10m OF 26AWG
TWIN-AXIAL CABLE, 3.125Gb/s
64ps/div
FIGURE 5. RECEIVED SIGNAL AFTER 15m OF 26AWG
TWIN-AXIAL CABLE, 3.125Gb/s
8
64ps/div
FIGURE 6. QLx4300-S45 OUTPUT AFTER 15m OF 26AWG
TWIN-AXIAL CABLE, 3.125Gb/s
FN6982.1
November 19, 2009
QLx4300-S45
80mV/div
70mV/div
Typical Performance Characteristics (Continued)
64ps/div
64ps/div
FIGURE 8. QLx4300-S45 OUTPUT AFTER 20m OF 26AWG
TWIN-AXIAL CABLE, 3.125Gb/s
60mV/div
60mV/div
FIGURE 7. RECEIVED SIGNAL AFTER 20m OF 26AWG
TWIN-AXIAL CABLE, 3.125Gb/s
64ps/div
64ps/div
FIGURE 9. RECEIVED SIGNAL AFTER 25m OF 26AWG
TWIN-AXIAL CABLE, 3.125Gb/s
FIGURE 10. QLx4300-S45 OUTPUT AFTER 25m OF 26AWG
TWIN-AXIAL CABLE, 3.125Gb/s
RETURN LOSS AND CROSSTALK CHARACTERISTICS
0
-5
Channel 1
Channel 2
Channel 3
-5
-10
Channel 4
-10
Channel 1
SCC22 (dB)
SCC11 (dB)
0
-15
-20
-25
Channel 2
Channel 3
Channel 4
-15
-20
-25
-30
-30
0
0.5
1
1.5
2
2.5
3
3.5
4
Frequency (GHz)
FIGURE 11. INPUT COMMON-MODE RETURN LOSS
9
0
0.5
1
1.5
2
2.5
3
3.5
4
Frequency (GHz)
FIGURE 12. OUTPUT COMMON-MODE RETURN LOSS
FN6982.1
November 19, 2009
QLx4300-S45
0
0
-5
-5
-10
-10
SDD22 (dB)
SDD11 (dB)
Typical Performance Characteristics (Continued)
-15
-20
Channel 1
Channel 2
Channel 3
Channel 4
-25
-30
Channel 1
Channel 2
Channel 3
Channel 4
-15
-20
-25
-30
-35
-35
0
0.5
1
1.5
2
2.5
3
3.5
0
4
0.5
FIGURE 13. INPUT DIFFERENTIAL RETURN LOSS
FIGURE 15. DIFFERENTIAL CROSSTALK BETWEEN
ADJACENT INPUT CHANNEL
Operation
The QLx4300-S45 is an advanced quad lane-extender for
high-speed interconnects. A functional diagram of one of
the four channels in the QLx4300-S45 is shown in
Figure 17. In addition to a robust equalization filter to
compensate for channel loss and restore signal fidelity,
the QLx4300-S45 contains unique integrated features to
preserve special signaling protocols typically broken by
other equalizers. The signal detect function is used to
mute the channel output when the equalized signal falls
below the level determined by the Detection Threshold
(DT) pin voltage. This function is intended to preserve
periods of line silence (“quiescent state” in InfiniBand
contexts).
As illustrated in Figure 17, the core of each high-speed
signal path in the QLx4300-S45 is a sophisticated
equalizer followed by a limiting amplifier. The equalizer
compensates for skin loss, dielectric loss, and impedance
discontinuities in the transmission channel. Each
10
1
1.5
2
2.5
3
3.5
4
Frequency (GHz)
Frequency (GHz)
FIGURE 14. OUTPUT DIFFERENTIAL RETURN LOSS
FIGURE 16. DIFFERENTIAL CROSSTALK BETWEEN
ADJACENT INPUT CHANNELS
equalizer is followed by a limiting amplification stage that
provides a clean output signal with full amplitude swing
and fast rise-fall times for reliable signal decoding in a
subsequent receiver.
IN[k]
IS[k]
>200kΩ
SETTABLE
EQUILIZER
LIMITING
AMPLIFIER
OUT[k]
BIT SELECT
(CP[k]/DI)
AMPLITUDE
DETECTOR
+
-
MUTE
ENABLED
DT
FIGURE 17. FUNCTIONAL DIAGRAM OF A SINGLE
CHANNEL WITHIN THE QLx4300-S45
Individually Adjustable Equalization Boost
Each channel in the QLx4300-S45 features an
independently settable equalizer for custom signal
restoration. Each equalizer can be set to one of 32 levels
of compensation when the serial bus is used to program
FN6982.1
November 19, 2009
QLx4300-S45
the boost level and one of 18 compensation levels when
the CP[k] pins are used to set the level. The equalizer
transfer functions for a subset of these compensation
levels are plotted in Figure 18. The flexibility of this
adjustable compensation architecture enables signal
fidelity to be optimized on a channel-by-channel basis,
providing support for a wide variety of channel
characteristics and data rates ranging from 2.5Gb/s to
3.125Gb/s. Because the boost level is externally set
rather than internally adapted, the QLx4300-S45
provides reliable communication from the very first bit
transmitted. There is no time needed for adaptation and
control loop convergence. Furthermore, there are no
pathological data patterns that will cause the
QLx4300-S45 to move to an incorrect boost level.
The “Applications Information” section beginning on
page 12 details how to set the boost level by both the
CP-pin voltage approach and the serial programming
approach.
VDD
IN[k] P
50Ω
Buffer
50Ω
IN[k] N
FIGURE 19. CML INPUT EQUIVALENT CIRCUIT FOR THE
QLx4300-S45
VDD
52Ω
52Ω
OUT[k] P
OUT[k] N
FIGURE 18. EQUALIZER TRANSFER FUNCTIONS FOR
SETTINGS 0, 5, 10, 15, 20, 25, AND 31 IN
THE QLx4300-S45
FIGURE 20. CML OUTPUT EQUIVALENT CIRCUIT FOR
THE QLx4300-S45
CML Input and Output Buffers
NOTE: The load value of 52Ω is used to internally match
SDD22 for a characteristic impedance of 50Ω.
The input and output buffers for the high-speed data
channels in the QLx4300-S45 are implemented using
CML. Equivalent input and output circuits are shown in
Figures 19 and 20, respectively.
Line Silence/Electrical Idle/Quiescent Mode
Line silence is commonly broken by the limiting
amplification in other equalizers. This disruption can be
detrimental in many systems that rely on line silence as
part of the protocol. The QLx4300-S45 contains special
lane management capabilities to detect and preserve
periods of line silence while still providing the
fidelity-enhancing benefits of limiting amplification during
active data transmission. Line silence is detected by
measuring the amplitude of the equalized signal and
comparing that to a threshold set by the current at the
DT pin. When the amplitude falls below the threshold,
the output driver stages are muted and held at their
nominal common mode voltage1.
1. The output common mode voltage remains constant during both active data transmission and output muting modes.
11
FN6982.1
November 19, 2009
Applications Information
Several aspects of the QLx4300-S45 are capable of being
dynamically managed by a system controller to provide
maximum flexibility and optimum performance. These
functions are controlled by interfacing to the highlighted
pins in Figure 21. The specific procedures for controlling
these aspects of the QLx4300-S45 are the focus of this
section.
CP2[B]
CP2[C]
CP2[A]
CP1[B]
CP1[C]
ENB
In addition to controlling the input impedance, the IS[k]
pin powers down the equalizer channel when pulled low.
This feature allows a system controller individually to
power down unused channels and to minimize power
consumption. Example: the signal to power down a
channel could come from an Intelligent Platform
Management controller in ATCA applications for
E-Keying. The current draw for a channel is reduced from
50mA to 3.8mA when powered down.
CLK
Channel Power-Down
CP1[A]
QLx4300-S45
46 45 44 43 42 41 40 39
DT
1
38 BGREF
IN1[P]
2
37 OUT1[P]
IN1[N]
3
36 OUT1[N]
VDD
4
35 VDD
IN2[P]
5
34 OUT2[P]
IN2[N] 6
33 OUT2[N]
VDD 7
32 VDD
EXPOSED PAD
(GND)
IN3[P] 8
31 OUT3[P]
IN3[N] 9
30 OUT3[N]
VDD 10
29 VDD
IN4[P] 11
28 OUT4[P]
IN43[N] 12
27 OUT4[N]
IS1 13
26 IS3
IS2 14
25 IS4
GND 15
24 MODE
CP4[C]
CP4[B]
CP4[A]
CP3[C]
CP3[B]
CP3[A]
DI
DO
16 17 18 19 20 21 22 23
FIGURE 21. PIN DIAGRAM HIGHLIGHTING PINS USED
FOR DYNAMIC CONTROL OF THE
QLx4300-S45
TABLE 1. DESCRIPTIONS OF PINS THAT CAN BE USED TO SET EQUALIZATION BOOST LEVEL
PIN NAME
PIN
NUMBER
DI
16
Serial data input, CMOS logic. Input for serial data stream to program internal registers controlling
the boost for all four equalizers. Synchronized with clock (CLK) on pin 46. Overrides the boost
setting established on CP control pins. Internally pulled down.
DO
17
Serial data output, CMOS logic. Output of the internal registers controlling the boost for all four
equalizers. Synchronized with clock on pin 46. Equivalent to serial data input on DI but delayed by
21 clock cycles.
CP3[A,B,C]
18, 19, 20
Control pins for setting equalizer 3. CMOS logic inputs. Pins are read as a 3-digit number to set the
boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25kΩ resistor.
CP4[A,B,C]
21, 22, 23
Control pins for setting equalizer 4. CMOS logic inputs. Pins are read as a 3-digit number to set the
boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25kΩ resistor.
MODE
24
Boost-level control mode input, CMOS logic. Allows serial programming of internal registers
through pins DI, ENB, and Clk when set “HIGH”. Resets all internal registers to zero and uses boost
levels set by CP pins when set LOW. If serial programming is not used, this pin should be grounded.
CP2[C,B,A]
39, 40, 41
Control pins for setting equalizer 2. CMOS logic inputs. Pins are read as a 3-digit number to set the
boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25kΩ resistor.
CP1[C,B,A]
42, 43, 44
Control pins for setting equalizer 1. CMOS logic inputs. Pins are read as a 3-digit number to set the
boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25kΩ resistor.
ENB
45
Serial data enable (active low), CMOS logic. Internal registers can be programmed with DI and CLK
pins only when the ENB pin is ‘LOW’. Internally pulled down.
CLK
46
Serial data clock, CMOS logic. Synchronous clock for serial data on DI and DO pins. Data on DI is
latched on the rising clock edge. Clock speed is recommended to be between 10MHz and 20MHz.
Internally pulled down.
DESCRIPTION
12
FN6982.1
November 19, 2009
QLx4300-S45
Equalization Boost Level
Channel equalization for the QLx4300-S45 can be
individually set to either (a) one of 18 levels through the
DC voltages on external control pins or (b) one of 32
levels via a set of registers programmed by a low speed
serial bus. The pins used to control the boost level are
highlighted in Figure 21. Descriptions of these pins are
listed in Table 1. Please refer to “Pin Descrptions” on
page 3 for descriptions of all other pins on the
QLx4300-S45.
The boost setting for equalizer channel k can be read as
a three digit ternary number across CP[k][A,B,C]. The
ternary value is established by the value of the resistor
between VDD and the CP[k][A,B,C] pin.
As a second option, the equalizer boost setting can be
taken from a set of registers programmed through a
serial bus interface (pins 16, 17, 45, and 46). Using this
interface, a set of registers is programmed to store the
boost level. A total of 21 registers are used. Registers 2
through 21 are parsed into four 5-bit words. Each 5-bit
word determines which of 32 boost levels to use for the
corresponding equalizer. Register 1 instructs the
QLx4300-S45 to use registers 2 through 21 to set the
boost level rather than the control pins CP[k][A,B,C].
Both options have their relative advantages. The control
pin option minimizes the need for external controllers as
the boost level can be set in the board design resulting in
a compact layout. The register option is more flexible for
cases in which the optimum boost level will not be known
and can be changed by a host bus adapter with a small
number of pins. It is noted that the serial bus interface
can also be daisy-chained among multiple QLx4300-S45
devices to afford a compact programmable solution even
when a large number of data lines need to be equalized.
Upon power-up, the default value of all the registers (and
register 1 in particular) is zero, and thus, the CP pins are
used to set the boost level. This permits an alternate
interpretation on setting the boost level. Specifically, the
CP pins define the default boost level until the registers
are (if ever) programmed via the serial bus.
TABLE 2. MAPPING BETWEEN CP-SETTING RESISTOR
AND PROGRAMMED BOOST LEVELS
RESISTANCE BETWEEN CP PIN AND VDD
CP[A]
CP[B]
CP[C]
SERIAL
BOOST LEVEL
Open
Open
Open
0
Open
Open
25kΩ
2
Open
Open
0Ω
4
Open
25kΩ
Open
6
Open
25kΩ
25kΩ
8
Open
25kΩ
0Ω
10
Open
0Ω
Open
12
Open
0Ω
25kΩ
14
Open
0Ω
0Ω
15
0Ω
Open
Open
16
0Ω
Open
25kΩ
17
0Ω
Open
0Ω
19
0Ω
25kΩ
Open
21
0Ω
25kΩ
25kΩ
23
0Ω
25kΩ
0Ω
24
0Ω
0Ω
Open
26
0Ω
0Ω
25kΩ
28
0Ω
0Ω
0Ω
31
Control Pin Boost Setting
When register 1 of the QLx4300-S45 is zero (the default
state on power-up), the voltages at the CP pins are used
to determine the boost level of each channel. For each of
the four channels, k, the [A], [B], and [C] control pins
(CP[k]) are associated with a 3-bit non binary word.
While [A] can take one of two values, ‘LOW’ or ‘HIGH’,
[B] and [C] can take one of three different values: ‘LOW’,
‘MIDDLE’, or ‘HIGH’. This is achieved by changing the
value of a resistor connected between VDD and the CP
pin, which is internally pulled low with a 25kΩ resistor.
Thus, a ‘HIGH’ state is achieved by using a 0Ω resistor,
‘MIDDLE’ is achieved with a 25kΩ resistor, and ‘LOW’ is
achieved with an open resistance. Table 2 defines the
mapping from the 3-bit CP word to the 18 out of 32
possible levels available via the serial interface.
If all four channels are to use the same boost level, then
a minimum number of board resistors can be realized by
tying together like CP[k][A,B,C] pins across all channels
k. For instance, all four CP[k][A] pins can be tied to the
same resistor running to VDD. Consequently, only three
resistors are needed to control the boost of all four
channels. If the CP Pins are tied together and the 25kΩ is
used, the value changes to a 6.25kΩ resistor because the
25kΩ is divided by 4.
13
FN6982.1
November 19, 2009
QLx4300-S45
Optimal Cable Boost Settings
The settable equalizing filter within the QLx4300-S45
enables the device to optimally compensate for
frequency-dependent attenuation across a wide variety
of channels, data rates, and encoding schemes. For the
reference channels plotted in Figure 2, Table 3 shows the
optimal boost setting when transmitting a PRBS-7 signal.
The optimal boost setting is defined as the equalizing
filter setting that minimizes the output residual jitter of
the QLx4300-S45. The settings in Table 4 represent the
optimal settings for the QLx4300-S45 across an ambient
temperature range of 0°C to +70°C. The optimal setting
at room temperature (+20°C to +40°C) is generally one
to two settings lower than the values listed in Table 3.
TABLE 3. OPTIMAL CABLE BOOST SETTINGS
CABLE
APPROX. LOSS @
1.5625GHz (dB)
QLx4300-S45
BOOST
Cable A
17
12
Cable B
23
16
Cable C
28
23
NOTE: Optimal boost settings should be determined on an
application-by-application basis to account for variations in
channel type, loss characteristics, and encoding schemes. The
settings in this table are presented as guidelines to be used as
a starting point for application-specific optimization.
Register Description
The QLx4300-S45’s internal registers are listed in
Table 4. Register 1 determines whether the CP pins or
register values 2 through 21 are used to set the boost
level. When this register is set, the QLx4300-S45 uses
registers 2-6, 7-11, 12-16, and 17-21 to set the boost
level of equalizers 1, 2, 3, and 4. When register 1 is not
set, the CP pins are used to determine the boost level for
each equalizer channel. The use of five registers for each
equalizer channel allows all 32 boost levels as candidate
boost levels.
TABLE 4. DESCRIPTION OF INTERNAL SERIAL REGISTERS
REGISTER
EQUALIZER
CHANNEL
1
1-4
2
1
DESCRIPTION
CP control override – Use registers 2 through 21 (rather than CP pins) to establish the boost
levels when this bit is set.
Equalizer setting bit 0 (LSB).
3
Equalizer setting bit 1.
4
Equalizer setting bit 2.
5
Equalizer setting bit 3.
6
Equalizer setting bit 4 (MSB).
7
2
Equalizer setting bit 0 (LSB).
8
Equalizer setting bit 1.
9
Equalizer setting bit 2.
10
Equalizer setting bit 3.
11
Equalizer setting bit 4 (MSB).
12
3
Equalizer setting bit 0 (LSB).
13
Equalizer setting bit 1.
14
Equalizer setting bit 2.
15
Equalizer setting bit 3.
16
Equalizer setting bit 4 (MSB).
17
4
Equalizer setting bit 0 (LSB).
18
Equalizer setting bit 1.
19
Equalizer setting bit 2.
20
Equalizer setting bit 3.
21
Equalizer setting bit 4 (MSB).
14
FN6982.1
November 19, 2009
QLx4300-S45
ENB
tSCK
tHEN
CLK
tSDI tHDI
DI
R21
R20
R19
R1
FIGURE 22. TIMING DIAGRAM FOR PROGRAMMING THE INTERNAL REGISTERS OF THE QLx4300-S45
Serial Bus Programming
Pins 16 (DI), 45 (ENB), and 46 (CLK) are used to
program the registers inside the QLx4300-S45. Figure 22
shows an exemplary timing diagram for the signals on
these pins. The serial bus can be used to program a
single QLx4300-S45 according to the following steps:
1. The ENB pin is pulled ‘LOW’.
- While this pin is ‘LOW’, the data input on DI are
read into registers but not yet latched.
- A setup time of tSCK is needed between ENB going
‘LOW’ and the first rising clock edge.
2. At least 21 values are read from DI on the rising
edge of the CLK signal.
- If more than 21 values are passed in, then only the
last 21 values are kept in a FIFO fashion.
- The data on DI should start by sending the value
destined for register 21 and finish by sending the
value destined for register 1.
- A range of clock frequencies can be used. A typical
rate is 10MHz. The clock should not exceed 20MHz.
- Setup (tSDI) and hold (tHDI) times are needed
around the rising clock edge.
3. The ENB pin is pulled ‘HIGH’ and the contents of the
registers are latched and take effect.
- After clocking in the last data bit, an additional
tHEN should elapse before pulling the ENB signal
‘HIGH’.
- After completing these steps, the new values will
affect within tD.
uses a common ENB signal as the serial data is
carried-over from one QLx4300-S45 to the next.
Separate ENB Signals
Multiple QLx4300-S45 devices can be programmed from
a common serial data stream as shown in Figure 23.
Here, each QLx4300-S45 is provided its own ENB signal,
and only one of these ENB signals is pulled ‘LOW’, and
hence accepting the register data one at a time. In this
situation, the programming of each equalizer follows the
steps outlined in Figure 22.
DI/DO Carryover
The DO pin (pin 17) can be used to daisy-chain the serial
bus among multiple QLx4300-S45 chips. The DO pin
outputs the overflow data from the DI pin. Specifically, as
data is pipelined into a QLx4300-S45, it proceeds
according to the following flow. First, a bit goes into
shadow register 1. Then, with each clock cycle, it shifts
over into subsequent higher numbered registers. After
shifting into register 21, it is output on the DO pin on the
same clock cycle. Thus, the DO signal is equal to the DI
signal, but delayed by 20 clock cycles. The timing
diagram for the DO pin is shown in Figure 24 where the
first 20 bits output from the DO are indefinite and
subsequent bits are the data fed into the DI pin. The
delay between the rising clock edge and the data
transition is tCQ.
A diagram for programming multiple QLx4300-S45s is
shown in Figure 25. It is noted that the board layout
should ensure that the additional clock delay experienced
between subsequent QLx4300-S45s should be no more
than the minimum value of tCQ, i.e. 12ns.
Programming Multiple QLx4300-S45
Devices
The serial bus interface provides a simple means of
setting the equalizer boost levels with a minimal amount
of board circuitry. Many of the serial interface signals can
be shared among the QLx4300-S45 devices on a board
and two options are presented in this section. The first
uses common clock and serial data signals along with
separate ENB signals to select which QLx4300-S45
accepts the programmed changes. The second method
15
FN6982.1
November 19, 2009
QLx4300-S45
Serial
Register
Data
QLx4300-S45
(A)
DI
QLx4300-S45
(B)
DI
ENB
CLK
QLx4300-S45
(C)
DI
ENB
DO
CLK
QLx4300-S45
(D)
DI
ENB
DO
CLK
ENB
DO
CLK
DO
Clock
ENB (A)
ENB (B)
ENB (C)
ENB (D)
FIGURE 23. SERIAL BUS PROGRAMMING MULTIPLE QLx4300-S45 DEVICES USING SEPARATE ENB SIGNALS
ENB
20 Clock Cycles
21st Rising Edge
tSCK
CLK
t CQ
First Bit from DI
DO
FIGURE 24. TIMING DIAGRAM FOR DI/DO CARRYOVER
Serial
Register
Data
QLx4300-S45
(A)
ENB
DI
QLx4300-S45
(B)
ENB
DI
QLx4300-S45
(C)
ENB
DI
QLx4300-S45
(D)
ENB
DI
CLK
CLK
CLK
CLK
DO
DO
DO
DO
Clock
ENB
FIGURE 25. SERIAL BUS PROGRAMMING MULTIPLE QLx4300-S45 DEVICES USING DI/DO CARRYOVER
16
FN6982.1
November 19, 2009
QLx4300-S45
ENB
tSCK
tHEN
CLK
tSDI tHDI
DI
R21
R20
QLx4300-S45 (D)
R1
R21
R1
QLx4300-S45 (C)
R21
R1
R21
QLx4300-S45 (B)
R1
QLx4300-S45 (A)
FIGURE 26. TIMING DIAGRAM FOR PROGRAMMING MULTIPLE QLx4300-S45 DEVICES USING DI/DO CARRYOVER
Detection Thereshold (DT) Pin Functionality
The QLx4300-S45 is capable of maintaining periods of
line silence on any of its four channels by monitoring
each channel for loss of signal (LOS) conditions and
subsequently muting the outputs of a respective channel
when such a condition is detected. A reference current
applied to the detection threshold (DT) pin is used to set
the LOS threshold of the internal signal detection
circuitry. Current control on the DT pin is done via one or
two external resistors. Nominally, both a pull-up and
pull-down resistor are tied to the DT pin (Figure 27A),
but if adequate control of the supply voltage is
maintained to within ±3% of 1.2V, then a simple pull
down resistor is adequate (as in Figure 27B). Resistors
used should be at least 1/16W, with ±1% precision.
FIGURE 27A.
The internal bias point of the DT pin, nominally 1.05V, is
used in conjunction with the voltage divider (R1 and R2)
shown in Figure 27A to set the reference current on the
DT pin.
Case 1: Channels with less than or equal to 17dB loss at
1.5625GHz:
For signals transmitted on channels having less than
or equal to 25dB of loss at 2.5GHz, the optimal DT
reference current is 0µA. This optimal reference
current may be achieved by either leaving the DT pin
floating, or tying the DT pin to ground (GND) with a
10MΩ resistor.
FIGURE 27B.
Case 2: Channels with greater 17dB loss at 1.5625GHz:
For channels exhibiting more than 25dB of total loss
(this includes cable or FR-4 loss) the DT pin should
be configured for a reference sink current (coming
out of the DT pin) of approximately 2µA. A typical
configuration for a 2µA sink current is given in
Figure 27C. If the configuration in Figure 27B is
utilized, a 525kΩ resistor is used.
FIGURE 27C.
FIGURE 27.
17
FN6982.1
November 19, 2009
QLx4300-S45
Typical Application Reference Designs
Figures 28 and 29 show reference design schematics for a QLx4300-S45 evaluation board with an SMA connector
interface. Figure 28 shows the schematic for the case when the equalizer boost level is set via the CP pins. Figure 29
shows the schematic for the case when the level is set via the serial bus interface.
CP2[C]
39
CP2[B]
40
CP2[A]
41
CP1[B]
CP1[C]
42
44
43
NC
CP1[A]
45
9
30
10
29
11
28
12
27
13
26
14
25
15
24
OUT1[N]
1.2V
OUT2[P]
OUT2[N]
1.2V
OUT3[P]
OUT3[N]
1.2V
OUT4[P]
OUT4[N]
IS3
IS4
MODE
EQ Boost Control
for Channels 3 and 4
(See pages 15-17)
= SMA Connector
Bypass circuit for each VDD pin: 4, 7, 10, 29, 32, 35
(*100pF capacitor should be positioned closest to the pin)
A
OUT1[P]
CP4[C]
DI
BGREF
23
31
NC
100pF*
10nF
1.2V
ENB
8
16
GND
32
22
IS2
Impedance Select (Channels 1 and 2)
7
21
IS1
33
CP4[A]
IN4[N]
34
6
CP4[B]
IN4[P]
QLx4300-S45
5
20
1.2V
35
CP3[C]
IN3[N]
4
19
IN3[P]
36
18
1.2V
37
3
CP3[B]
IN2[P]
IN2[N]
2
17
1.2V
Ω
6kO
38
CP3[A]
IN1[N]
EQ Boost Control
for Channels 1 and 2
(See pages 15-17)
1
NC
DT
IN1[P]
46
CLK
100k
47nF
NC
Detection threshold
reference current
DO
42.2k
1.2V
A) DC Blocking Capacitors = X7R or COG
0.1µF (>4GHz bandwidth)
Impedance Select (Channels 3 and 4)
MODE at 1.2V: Serial Control Mode
MODE at GND: Binary Control Mode
QLx4300-S45
LANE EXTENDER
Reference
Control Pin Mode
Quellan, Inc.
FIGURE 28. APPLICATION CIRCUIT FOR THE QLx4300-S45 EVALUATION BOARD USING THE CONTROL PINS FOR
SETTING THE EQUALIZER COMPENSATION LEVEL
18
FN6982.1
November 19, 2009
QLx4300-S45
Typical Application Reference Designs (Continued)
CP2[C]
39
CP2[B]
40
41
CP2[A]
CP1[C]
42
CP1[B]
43
CP1[A]
30
10
29
11
28
12
27
13
26
14
25
15
24
A
OUT1[P]
OUT1[N]
1.2V
OUT2[P]
OUT2[N]
1.2V
OUT3[P]
OUT3[N]
1.2V
OUT4[P]
OUT4[N]
IS3
IS4
MODE
CP4[C]
CP4[B]
BGREF
23
9
22
31
21
8
DI
Bypass circuit for each VDD pin: 4, 7, 10, 29, 32, 35
(*100pF capacitor should be positioned closest to the pin)
44
32
Serial Data In
100pF*
10nF
1.2V
45
Serial Clock In
7
16
GND
33
CP4[A]
IS2
Impedance Select (Channels 1 and 2)
34
6
20
IS1
QLx4300-S45
5
CP3[C]
IN4[N]
35
19
1.2V
IN4[P]
4
CP3[B]
IN3[N]
36
18
IN3[P]
37
3
17
1.2V
2
CP3[A]
IN2[P]
IN2[N]
Ω
6kO
38
Serial Data Out
1.2V
46
CLK
IN1[N]
NC
1
DO
DT
IN1[P]
ENB
Detection threshold
reference current
100k
47nF
42.2k
1.2V
Enable Active Low
Figures 28 and 29 show reference design schematics for a QLx4300-S45 evaluation board with an SMA connector
interface. Figure 28 shows the schematic for the case when the equalizer boost level is set via the CP pins. Figure 29
shows the schematic for the case when the level is set via the serial bus interface.
NC
= SMA Connector
A) DC Blocking Capacitors = X7R or COG
0.1µF (>4GHz bandwidth)
Impedance Select (Channels 3 and 4)
MODE at 1.2V: Serial Control Mode
MODE at GND: Binary Control Mode
QLx4300-S45
LANE EXTENDER
Reference
Serial Control Mode
Quellan, Inc.
FIGURE 29. APPLICATION CIRCUIT FOR THE QLx4300-S45 EVALUATION BOARD USING THE SERIAL BUS
INTERFACE FOR SETTING THE EQUALIZER COMPENSATION LEVEL
19
FN6982.1
November 19, 2009
QLx4300-S45
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications
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infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any
patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
20
FN6982.1
November 19, 2009
QLx4300-S45
Package Outline Drawing
L46.4x7
46 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE (TQFN)
Rev 0, 9/09
2.80
4.00
42X 0.40
A
B
46
39
6
PIN 1
INDEX AREA
7.00
38
5.50 ±0.1
Exp. DAP
5.60
15
24
(4X)
6
PIN 1
INDEX AREA
1
0.05
46X 0.20 4
0.10 M C A B
SIDE VIEW
TOP VIEW
16
23
2.50 ±0.1
Exp. DAP
46X 0.40
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
0.70 ±0.05
C
SEATING PLANE
0.05 C
SIDE VIEW
C
0.152 REF
5
0 . 00 MIN.
0 . 05 MAX.
DETAIL "X"
( 3.80 )
( 2.50)
NOTES:
( 6.80 )
( 42X 0.40)
( 5.50 )
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5.
Tiebar shown (if present) is a non-functional feature.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
(46X 0.20)
either a mold or mark feature.
( 46 X 0.60)
TYPICAL RECOMMENDED LAND PATTERN
21
FN6982.1
November 19, 2009
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