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THC63LVD1027_Rev.3.00_E
THC63LVD1027
Dual Link LVDS Repeater
General Description
Features
The THC63LVD1027 LVDS(Low Voltage Differential
Signaling) repeater is designed to support pixel data
transmission between Host and Flat Panel Display up to
WUXGA resolution.
THC63LVD1027 receives the dual link LVDS data
streams and transmits the LVDS data through various
line rate conversion modes, Dual Link Input / Dual Link
Output, Single Link Input / Dual Link Output, and Dual
Link Input / Single Link Output.
•
•
•
•
•
•
30bits/pixel dual link LVDS Receiver
30bits/pixel dual Link LVDS Transmitter
Wide LVDS input skew margin: ± 480ps at 75MHz
Accurate LVDS output timing: ± 250ps at 75MHz
Reduced swing LVDS output mode supported to
suppress the system EMI
Various line rate conversion modes supported
Dual link input / Dual link output [clkout=1x clkin]
Single link input / Dual link output [clkout=1/2x clkin]
Dual link input / Single link output [clkout=2x clkin]
•
•
•
•
•
Distribution (signal duplication) mode supported
Power down mode supported
3.3V single voltage power supply
No external components required for PLLs
64pin TSSOP with Exposed PAD (0.5mm lead pitch)
Block Diagram
Dual In / Dual Out Mode
THine® THC63LVD1027
85MHz
THC63LVD1027
85MHz
85MHz
30bit Data
LVDS
1st Link
Clock
LVDS-Tx
Serialize
LVDS-Rx
De-Serialize
PLL
30bit Data
LVDS
1st Link
Inter-Link
Multiplex
&
De-Multiplex
85MHz
THC63LVD1027
PLL
Single In / Dual Out Mode
Clock
135MHz
THC63LVD1027
LVDS
2nd Link
LVDS-Rx
De-Serialize
85MHz
85MHz
LVDS
2nd Link
30bit Data
Distribution Mode
Clock
PLL
Clock
85MHz
LVDS-Tx
Serialize
30bit Data
LDO
Regulator
67.5MHz
67.5MHz
Dual In / Single Out Mode
42.5MHz
THC63LVD1027
85MHz
42.5MHz
3.3v Power Supply
Decoupling Capacitor
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THine Electronics,Inc.
THC63LVD1027_Rev.3.00_E
Pin Out
RS
1
64
GND
CAP
2
63
CAP
GND
3
62
GND
VDD
4
61
VDD
RA1–
5
60
TA1–
RA1+
6
59
TA1+
RB1–
7
58
TB1–
RB1+
8
57
TB1+
RC1–
9
56
TC1–
RC1+
10
55
TC1+
RCLK1–
11
54
TCLK1–
RCLK1+
12
53
TCLK1+
RD1–
13
52
TD1–
RD1+
14
51
TD1+
RE1–
15
50
TE1–
RE1+
16
49
TE1+
48
TA2–
47
TA2+
46
TB2–
45
TB2+
RA2–
17
RA2+
18
RB2–
19
RB2+
20
TSSOP64
Exposed PAD
Top View
65 GND (Exposed PAD)
RC2–
21
44
TC2–
RC2+
22
43
TC2+
RCLK2–
23
42
TCLK2–
RCLK2+
24
41
TCLK2+
RD2–
25
40
TD2–
RD2+
26
39
TD2+
RE2–
27
38
TE2–
RE2+
28
37
TE2+
VDD
29
36
VDD
GND
30
35
GND
CAP
31
34
MODE1
PD
32
33
MODE0
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THC63LVD1027_Rev.3.00_E
Pin Description
Pin Name
Direction
Type
Description
RA1+/–
LVDS data input for channel A of 1st Link
RB1+/–
LVDS data input for channel B of 1st Link
RC1+/–
LVDS data input for channel C of 1st Link
RD1+/–
LVDS data input for channel D of 1st Link
RE1+/–
LVDS data input for channel E of 1st Link
RCLK1+/–
LVDS clock input for 1st Link
RA2+/–
LVDS data input for channel A of 2nd Link
Input
RB2+/–
LVDS data input for channel B of 2nd Link
RC2+/–
LVDS data input for channel C of 2nd Link
RD2+/–
LVDS data input for channel D of 2nd Link
RE2+/–
LVDS data input for channel E of 2nd Link
LVDS clock input for 2nd Link
RCLK2+/–
LVDS
In Distribution and Single-in/Dual-out mode, RCLK2+/- must be Hi-Z.
(see “Mode selection” below in this page.)
TA1+/–
LVDS data output for channel A of 1st Link
TB1+/–
LVDS data output for channel B of 1st Link
TC1+/–
LVDS data output for channel C of 1st Link
TD1+/–
LVDS data output for channel D of 1st Link
TE1+/–
LVDS data output for channel E of 1st Link
TCLK1+/–
TA2+/–
LVDS clock output for 1st Link
Output
LVDS data output for channel A of 2nd Link
TB2+/–
LVDS data output for channel B of 2nd Link
TC2+/–
LVDS data output for channel C of 2nd Link
TD2+/–
LVDS data output for channel D of 2nd Link
TE2+/–
LVDS data output for channel E of 2nd Link
TCLK2+/-
LVDS clock output for 2nd Link
Power Down
PD
H: Normal operation
L: Power down state, all LVDS output signals turn to Hi-Z
LVDS output swing level selection
RS
H: Normal swing
L: Reduced swing
Mode selection
Input
LV-TTL
MODE1
MODE0
MODE1
MODE0
RCLK2+/-
Description
L
L
clkin
Dual-in / Dual-out mode
L
L
Hi-Z
Distribution mode
H
L
Hi-Z
Single-in / Dual-out mode
L
H
clkin
Dual-in / Single-out mode
H
H
-
Reserved
In Distribution and Single-in/Dual-out mode, RCLK2+/- must be Hi-Z.
VDD
GND
3.3v power supply pins
Power
CAP
Copyright©2013 THine Electronics, Inc.
—
Ground pins (Exposed PAD is also Ground)
Decoupling capacitor pins
These pins should be connected to external decoupling capacitors (CCAP).
Recommended CCAP is 0.1uF
3/22
THine Electronics,Inc.
THC63LVD1027_Rev.3.00_E
Mode Setting
Input/Output
MODE1
MODE0
(Input mode)
(Output mode)
H: Single
H: Single
L: Dual
L: Dual
CLK in
L
L
Hi-Z
L
L
Hi-Z
H
L
CLK in
L
H
--
H
H
RCLK2+/-
Dual-In/Dual-Out
(Fig.1-1, 12-1)
Distribution
(Fig.1-2, 12-2)
Single-In/Dual-Out
(Fig.1-3, 12-3)
Dual-In/Single-Out
(Fig.1-4, 12-4)
Reserved
Signal Flow for Each Setting
Dual-In / Dual-Out
CLK
Frequency
f
RA1+/RB1+/RC1+/RD1+/DATA Rate RE1+/f
RCLK1+/-
Distribution mode
TA1+/CLK
TB1+/Frequency
TC1+/f
TD1+/TE1+/DATA Rate
f
TCLK1+/-
CLK
Frequency
f
RA2+/RB2+/RC2+/RD2+/DATA Rate RE2+/f
RCLK2+/-
TA2+/CLK
TB2+/Frequency
TC2+/f
TD2+/TE2+/DATA Rate
TCLK2+/f
CLK
Frequency
f
RA1+/RB1+/RC1+/RD1+/DATA Rate RE1+/f
RCLK1+/-
Same Data
RA2+/RB2+/RC2+/RD2+/RE2+/RCLK2+/-
Hi-z
Must be
Hi-z
TA2+/CLK
TB2+/Frequency
TC2+/f
TD2+/TE2+/DATA Rate
TCLK2+/f
=TCLK1+/-
Fig.1-2
Single-In / Dual-Out
Dual-In / Single-Out
RA1+/RB1+/RC1+/RD1+/DATA Rate RE1+/f
RCLK1+/-
TA1+/CLK
TB1+/Frequency
TC1+/f/2
TD1+/TE1+/DATA Rate
TCLK1+/f/2
RA2+/RB2+/RC2+/RD2+/RE2+/RCLK2+/-
TA2+/CLK
TB2+/Frequency
TC2+/f/2
TD2+/TE2+/DATA Rate
TCLK2+/f/2
Hi-z
Must be
Hi-z
=TCLK1+/-
Fig.1-1
CLK
Frequency
f
CLK
Frequency
f
RA1+/RB1+/RC1+/RD1+/DATA Rate RE1+/f
RCLK1+/-
TA1+/CLK
TB1+/Frequency
TC1+/2f
TD1+/TE1+/DATA Rate
TCLK1+/2f
CLK
Frequency
f
TA2+/TB2+/TC2+/TD2+/TE2+/TCLK2+/-
RA2+/RB2+/RC2+/RD2+/DATA Rate RE2+/f
RCLK2+/-
Fig.1-3
Copyright©2013 THine Electronics, Inc.
TA1+/CLK
TB1+/Frequency
TC1+/f
TD1+/TE1+/DATA Rate
TCLK1+/f
Hi-z
Fig.1-4
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THine Electronics,Inc.
THC63LVD1027_Rev.3.00_E
Output Control / Fail Safe
THC63LVD1027 has a function to control output depending on LVDS input condition.
PD
RCLK1+/-
RCLK2+/-
Output
L
*
*
All Hi-Z
H
Hi-Z
*
All Hi-Z
H
CLK in
CLK in
Refer to p.4 Mode Setting #
H
CLK in
Hi-Z
Refer to p.4 Mode Setting #
*: Don’t care
#: If a particular input data pair is Hi-Z, the corresponding output data become L according to LVDS DC spec.
For fail-safe purpose, all LVDS input pins are connected to VDD via resistance for detecting state of Hi-Z.
VDD
LVDS input buffer
Internal circuit of THC63LVD1027
Fig.2
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THine Electronics,Inc.
THC63LVD1027_Rev.3.00_E
Absolute Maximum Ratings
Parameter
Min
Max
Unit
Power Supply voltage
–0.3
4.0
V
LVDS Input Voltage
-0.3
VDD+0.3
V
Junction Temperature
—
125
ºC
Storage Temperature
–55
125
ºC
Reflow Peak Temperature / Time
—
260 / 10sec.
ºC
Maximum Power Dissipation @+25 °C
—
2.5
W
Operating Conditions
Symbol
Parameter
Min
Typ
Max
Unit
Ta
Ambient Temperature
–20
25
70
ºC
VDD
Power Supply voltage
3.0
3.3
3.6
V
Input
20
—
85
MHz
Output
20
—
85
MHz
Input
20
—
85
MHz
Output
20
—
85
MHz
Input
40
—
135
MHz
Output
20
—
67.5
MHz
Input
20
—
42.5
MHz
Output
40
—
85
MHz
Dual-in / Dual-out
Distribution
Fclk
Single-in / Dual-out
Dual-in / Single-out
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THC63LVD1027_Rev.3.00_E
Power Dissipation
Symbol
Parameter
Conditions
Dual-in/Dual-out
Distribution
Operating Current
ICCW
Min
Typ
Max
Unit
CLKIN=40MHz
—
—
265
mA
CLKIN=65MHz
—
—
305
mA
CLKIN=75MHz
—
—
325
mA
CLKIN=85MHz
—
—
340
mA
CLKIN=40MHz
—
—
215
mA
CLKIN=65MHz
—
—
235
mA
CLKIN=75MHz
—
—
245
mA
CLKIN=85MHz
—
—
260
mA
—
—
175
mA
—
—
190
mA
—
—
200
mA
CLKIN=85MHz
—
—
210
mA
CLKIN=112MHz
—
—
230
mA
CLKIN=135MHz
—
—
250
mA
CLKIN=20MHz
—
—
215
mA
CLKIN=32.5MHz
—
—
235
mA
CLKIN=37.5MHz
—
—
245
mA
CLKIN=42.5MHz
—
—
260
mA
—
—
—
8
mA
CLKIN=40MHz
(Worst Case Pattern)
Fig1
CLKIN=65MHz
CLKIN=75MHz
Single-in/Dual-out
Dual-in/Single-out
ICCS
Power Down Current
—
RL_TX = 100Ω
CL=5pF
RS=VDD
Fig2
TCLKx+
Tyx+
x=1,2
y= A, B, C, D, E
Fig.3 Test Pattern (LVDS Output Full Toggle Pattern)
x=1,2
y= A, B, C, CLK, D, E
Tyx+
5pF
100Ω
TyxLVDS Output Load
Fig.4 LVDS Output Load
Copyright©2013 THine Electronics, Inc.
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THine Electronics,Inc.
THC63LVD1027_Rev.3.00_E
Electrical Characteristics
THC63LVD1027 DC Specifications
Symbol
Vcap
Parameter
Conditions
Capacitor pin appearance voltage
CCAP = 0.1µF
Min.
Typ.
Max.
—
1.8
—
Units
VIL_TTL
LV-TTL Input Low Voltage
—
GND
—
0.8
VIH_TTL
LV-TTL Input High Voltage
—
2.0
—
VDD
IIN_TTL
LV-TTL Input Leakage Current
—
-4
—
+4
μA
Conditions
Min.
Typ.
Max.
Units
V
LVDS Receiver DC Specifications
Symbol
Parameter
VIN_RX
LVDS-Rx Input voltage range
—
0.3
—
2.1
VIC_RX
LVDS-Rx Common voltage
—
0.6
1.2
1.8
VTH_RX
LVDS-Rx differential High threshold
—
—
+100
VTL_RX
LVDS-Rx differential Low threshold
-100
—
—
| VID_RX |
LVDS-Rx differential Input Voltage
—
100
—
600
LVDS-Rx Input Leakage current
—
-0.3
—
0.3
IIN_RX
VIC_RX = 1.2V
V
mV
mA
LVDS Transmitter DC Specifications
Symbol
VOC_TX
ΔVOC_TX
| VOD_TX |
ΔVOD_TX
Parameter
Conditions
Min.
Typ.
Max.
Units
—
1.125
1.25
1.375
V
—
—
—
35
mV
Normal swing
250
350
450
Reduced swing
100
200
300
—
—
—
35
mV
Vout= GND
-24
—
—
mA
Vout= GND to Vcc
-10
—
+10
uA
LVDS-Tx Common voltage
Change in VOC between
complementary output states
LVDS-Tx differential
Output Voltage
RL_TX = 100Ω
Change in VOD between
complementary output states
IOS_TX
LVDS-Tx Output Short current
IOZ_TX
LVDS-Tx Output Tri-state current
Copyright©2013 THine Electronics, Inc.
PD=GND
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mV
THine Electronics,Inc.
THC63LVD1027_Rev.3.00_E
THC63LVD1027 AC Characteristics
Symbol
Parameter
Conditions
Phase Lock Loop Set
Time (Fig.3)
tLT
tDL
Min
Typ
Max
Unit
—
—
—
10
ms
Dual-in/Dual-out
CLKIN=75MHz
9tRCP+3
9tRCP+5
9tRCP+7
Distribution
CLKIN=75MHz
9tRCP+3
9tRCP+5
9tRCP+7
Single-in/Dual-out
CLKIN=75MHz
(11+2/7)tRCP+3
(11+2/7)tRCP+5
(11+2/7)tRCP+7
Dual-in/Single-out
CLKIN=37.5MHz
(8+5/14)tRCP+3
(8+5/14)tRCP+5
(8+5/14)tRCP+7
—
2tRCP
—
—
—
2tRCP
—
—
—
4tRCP
Must be 2ntRCP
(n=integer)
—
—
Data Latency (Fig.4)
tDEH
DE input High time (Fig.5)
tDEL
DE input Low time (Fig.5)
Single-in/ Dual-out
DE input Period (Fig.5)
tDEINT
AC Timing Diagrams
VDD
3.0V
RCLK1+/-
2.0V
PD
tLT
TCLKx+/x=1,2
Note:
1) Vdifftc = (TCLK+) - (TCLK-)
Vdifftc = 0V
Fig.5 Phase Lock Loop Set Time
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ns
ns
THC63LVD1027_Rev.3.00_E
AC Timing Diagrams (Continued)
RCLK1+
Vdiffrc = 0V
Ryx+/x= 1,2
y= A, B, C, D, E
Note:
1) Vdiffrc = (RCLK+) - (RCLK-)
2) Vdifftc = (TCLK+) - (TCLK-)
Current Data
tDL
TCLK1+
Vdifftc = 0V
Tyx+/x= 1,2
y= A, B, C, D, E
Current Data
Fig.6 DATA Latency
RCLK1+
DE
DE
DE
DE
DE
DE
RC1+
tDEH
tDEL
tDEINT
Fig.7 Single link input / Dual link output mode RC1(DE) input timing
Copyright©2013 THine Electronics, Inc.
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THine Electronics,Inc.
THC63LVD1027_Rev.3.00_E
LVDS Receiver AC Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
tRCP
LVDS Clock Period
—
7.4
—
50
tRCH
LVDS Clock High duration
—
2/7 tRCP
4/7 tRCP
5/7 tRCP
tRCL
LVDS Clock Low duration
—
2/7 tRCP
3/7 tRCP
5/7 tRCP
CLKIN=75MHz
480
—
—
CLKIN=112MHz(1)
250
—
—
CLKIN=135MHz(1)
220
—
—
CLKIN=75MHz
480
—
—
CLKIN=112MHz(1)
250
—
—
CLKIN=135MHz(1)
220
—
—
tRSUP
tRHLD
LVDS data input setup margin
LVDS data input hold margin
tRIP6
LVDS data input position 6
—
2/7tRCP - tRHLD
2/7 tRCP
2/7tRCP + tRSUP
tRIP5
LVDS data input position 5
—
3/7tRCP - tRHLD
3/7 tRCP
3/7tRCP + tRSUP
tRIP4
LVDS data input position 4
—
4/7tRCP - tRHLD
4/7 tRCP
4/7tRCP + tRSUP
tRIP3
LVDS data input position 3
—
5/7tRCP - tRHLD
5/7 tRCP
5/7tRCP + tRSUP
tRIP2
LVDS data input position 2
—
6/7tRCP - tRHLD
6/7 tRCP
6/7tRCP + tRSUP
tRIP1
LVDS data input position 1
—
7/7tRCP - tRHLD
7/7 tRCP
7/7tRCP + tRSUP
tRIP0
LVDS data input position 0
—
8/7tRCP - tRHLD
8/7 tRCP
8/7tRCP + tRSUP
tCK12
Skew Time between RCLK1
and RCLK2 (Fig.6)
—
-0.3 tRCP
—
0.3 tRCP
(1) Single Link Input / Dual Link Output mode , VIC_RX = 1.2V , tRCH = 4/7 tRCP
LVDS Receiver Input Timing
tRIP0
tRIP1
tRIP2
tRIP3
tRIP4
tRIP5
tRIP6
Ryx+/-
D<6>
D<5>
D<4>
D<3>
D<2>
D’<1>
D’<0>
tRCP
tRCH
tRCL
RCLKx+
RCLKxx= 1, 2
y= A, B, C, D, E
Ry1+/- skew margin is the one between RCLK1+/- and Ry1+/-.
Ry2+/- skew margin is the one between RCLK2+/- and Ry2+/-.
Fig.8
Copyright©2013 THine Electronics, Inc.
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THine Electronics,Inc.
Unit
ns
ps
ps
ps
THC63LVD1027_Rev.3.00_E
LVDS Receiver Input Timing (Continued)
Note:
1) Vdiffrc = (RCLK+) - (RCLK-)
(RCLK1+)-(RCLK1-)
Vdiffrc = 0V
tCK12
(RCLK2+)-(RCLK2-)
Vdiffrc = 0V
Fig.9 Skew Time between RCLK1 and RCLK2
Copyright©2013 THine Electronics, Inc.
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THine Electronics,Inc.
THC63LVD1027_Rev.3.00_E
LVDS Transmitter AC Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
tTCP
LVDS Clock Period
—
11.76
—
50
tTCH
LVDS Clock High duration
—
—
4/7 tTCP
—
tTCL
LVDS Clock Low duration
—
—
3/7 tTCP
—
tTSUP
LVDS data output setup
CLKOUT=75MHz
—
—
250
tTHLD
LVDS data output hold
CLKOUT=75MHz
—
—
250
tTOP6
LVDS data output position 6
—
2/7tTCP - tTHLD
2/7 tTCP
2/7tTCP + tTSUP
tTOP5
LVDS data output position 5
—
3/7tTCP - tTHLD
3/7 tTCP
3/7tTCP + tTSUP
tTOP4
LVDS data output position 4
—
4/7tTCP - tTHLD
4/7 tTCP
4/7tTCP + tTSUP
tTOP3
LVDS data output position 3
—
5/7tTCP - tTHLD
5/7 tTCP
5/7tTCP + tTSUP
tTOP2
LVDS data output position 2
—
6/7tTCP - tTHLD
6/7 tTCP
6/7tTCP + tTSUP
tTOP1
LVDS data output position 1
—
7/7tTCP - tTHLD
7/7 tTCP
7/7tTCP + tTSUP
tTOP0
LVDS data output position 0
—
8/7tTCP - tTHLD
8/7 tTCP
8/7tTCP + tTSUP
tLVT
LVDS Transition Time (Fig7)
—
—
0.6
1.5
LVDS Transmitter Output Timing
tTOP0
tTOP1
tTOP2
tTOP3
tTOP4
tTOP5
tTOP6
Tyx+/-
D<6>
D<5>
D<4>
D<3>
D<2>
D’<1>
D’<0>
tTCP
tTCH
TCLKx+
tTCL
TCLKxx=1,2
y= A, B, C, D, E
Ty1+/- output timing is the one between TCLK1+/- and Ty1+/-.
Ty2+/- output timing is the one between TCLK2+/- and Ty2+/-.
Fig.10
Vdifft
80%
80%
20%
20%
tLVT
Note:
1) Vdifft = (Tyx+) - (Tyx-)
x= 1, 2
y= A, B, C, CLK, D, E
tLVT
Fig.11 LVDS Transition Time
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THine Electronics,Inc.
Unit
ns
ps
ps
ns
THC63LVD1027_Rev.3.00_E
LVDS Data Mapping
Dual-in / Dual-out mode
LVDS-Rx Input Mapping
RCLK1+/–
RA1+/–
G1 [4]
R1 [9]
R1 [8]
R1 [7]
R1 [6]
R1 [5]
R1 [4]
G3 [4]
R3 [9]
R3 [8]
R3 [7]
R3 [6]
R3 [5]
R3 [4]
RB1+/–
B1 [5]
B1 [4]
G1 [9]
G1 [8]
G1 [7]
G1 [6]
G1 [5]
B3 [5]
B3 [4]
G3 [9]
G3 [8]
G3 [7]
G3 [6]
G3 [5]
RC1+/–
DE
VSYNC HSYNC B1 [9]
B1 [8]
B1 [7]
B1 [6]
DE
VSYNC HSYNC B3 [9]
B3 [8]
B3 [7]
B3 [6]
RD1+/–
data11
B1 [3]
B1 [2]
G1 [3]
G1 [2]
R1 [3]
R1 [2]
data11
B3 [3]
B3 [2]
G3 [3]
G3 [2]
R3 [3]
R3 [2]
RE1+/–
data12
B1 [1]
B1 [0]
G1 [1]
G1 [0]
R1 [1]
R1 [0]
data12
B3 [1]
B3 [0]
G3 [1]
G3 [0]
R3 [1]
R3 [0]
RA2+/–
G2 [4]
R2 [9]
R2 [8]
R2 [7]
R2 [6]
R2 [5]
R2 [4]
G4 [4]
R4 [9]
R4 [8]
R4 [7]
R4 [6]
R4 [5]
R4 [4]
RB2+/–
B2 [5]
B2 [4]
G2 [9]
G2 [8]
G2 [7]
G2 [6]
R2 [5]
B4 [5]
B4 [4]
G4 [9]
G4 [8]
G4 [7]
G4 [6]
G4 [5]
RC2+/–
DE
VSYNC HSYNC B2 [9]
B2 [8]
B2 [7]
B2 [6]
DE
VSYNC HSYNC B4 [9]
B4 [8]
B4 [7]
B4 [6]
RD2+/–
data21
B2 [3]
B2 [2]
G2 [3]
G2 [2]
R2 [3]
R2 [2]
data21
B4 [3]
B4 [2]
G4 [3]
G4 [2]
R4 [3]
R4 [2]
RE2+/–
data22
B2 [1]
B2 [0]
G2 [1]
G2 [0]
R2 [1]
R2 [0]
data22
B4 [1]
B4 [0]
G4 [1]
G4 [0]
R4 [1]
R4 [0]
RCLK2+/–
LVDS-Tx Output Mapping
TCLK1+/–
TA1+/–
G1 [4]
R1 [9]
R1 [8]
R1 [7]
R1 [6]
R1 [5]
R1 [4]
G3 [4]
R3 [9]
R3 [8]
R3 [7]
R3 [6]
R3 [5]
R3 [4]
TB1+/–
B1 [5]
B1 [4]
G1 [9]
G1 [8]
G1 [7]
G1 [6]
G1 [5]
B3 [5]
B3 [4]
G3 [9]
G3 [8]
G3 [7]
G3 [6]
G3 [5]
TC1+/–
DE
VSYNC HSYNC B1 [9]
B1 [8]
B1 [7]
B1 [6]
DE
VSYNC HSYNC B3 [9]
B3 [8]
B3 [7]
B3 [6]
TD1+/–
data11
B1 [3]
B1 [2]
G1 [3]
G1 [2]
R1 [3]
R1 [2]
data11
B3 [3]
B3 [2]
G3 [3]
G3 [2]
R3 [3]
R3 [2]
TE1+/–
data12
B1 [1]
B1 [0]
G1 [1]
G1 [0]
R1 [1]
R1 [0]
data12
B3 [1]
B3 [0]
G3 [1]
G3 [0]
R3 [1]
R3 [0]
TA2+/–
G2 [4]
R2 [9]
R2 [8]
R2 [7]
R2 [6]
R2 [5]
R2 [4]
G4 [4]
R4 [9]
R4 [8]
R4 [7]
R4 [6]
R4 [5]
R4 [4]
TB2+/–
B2 [5]
B2 [4]
G2 [9]
G2 [8]
G2 [7]
G2 [6]
G2 [5]
B4 [5]
B4 [4]
G4 [9]
G4 [8]
G4 [7]
G4 [6]
G4 [5]
TC2+/–
DE
VSYNC HSYNC B2 [9]
B2 [8]
B2 [7]
B2 [6]
DE
VSYNC HSYNC B4 [9]
B4 [8]
B4 [7]
B4 [6]
TD2+/–
data21
B2 [3]
B2 [2]
G2 [3]
G2 [2]
R2 [3]
R2 [2]
data21
B4 [3]
B4 [2]
G4 [3]
G4 [2]
R4 [3]
R4 [2]
TE2+/–
data22
B2 [1]
B2 [0]
G2 [1]
G2 [0]
R2 [1]
R2 [0]
data22
B4 [1]
B4 [0]
G4 [1]
G4 [0]
R4 [1]
R4 [0]
TCLK2+/–
( Regardless of the Data Latency )
Data bits “data11, data12, data21, data22” are available for additional data transmission.
Fig.12-1
Copyright©2013 THine Electronics, Inc.
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THine Electronics,Inc.
THC63LVD1027_Rev.3.00_E
Distribution Mode
In Distribution mode, RCLK2+/- must be High-Z.
LVDS-Rx Input Mapping
RCLK1+/–
RA1+/–
G1 [4]
R1 [9]
R1 [8]
R1 [7]
R1 [6]
R1 [5]
R1 [4]
G2 [4]
R2 [9]
R2 [8]
R2 [7]
R2 [6]
R2 [5]
R2 [4]
RB1+/–
B1 [5]
B1 [4]
G1 [9]
G1 [8]
G1 [7]
G1 [6]
G1 [5]
B2 [5]
B2 [4]
G2 [9]
G2 [8]
G2 [7]
G2 [6]
G2 [5]
RC1+/–
DE
VSYNC HSYNC B1 [9]
B1 [8]
B1 [7]
B1 [6]
DE
VSYNC HSYNC B2 [9]
B2 [8]
B2 [7]
B2 [6]
RD1+/–
data11
B1 [3]
B1 [2]
G1 [3]
G1 [2]
R1 [3]
R1 [2]
data11
B2 [3]
B2 [2]
G2 [3]
G2 [2]
R2 [3]
R2 [2]
RE1+/–
data12
B1 [1]
B1 [0]
G1 [1]
G1 [0]
R1 [1]
R1 [0]
data12
B2 [1]
B2 [0]
G2 [1]
G2 [0]
R2 [1]
R2 [0]
Hi-Z
RCLK2+/–
RA2+/–
no care
RB2+/–
no care
RC2+/–
no care
RD2+/–
no care
RE2+/–
no care
LVDS-Tx Output Mapping
TCLK1+/–
TA1+/–
G1 [4]
R1 [9]
R1 [8]
R1 [7]
R1 [6]
R1 [5]
R1 [4]
G2 [4]
R2 [9]
R2 [8]
R2 [7]
R2 [6]
R2 [5]
R2 [4]
TB1+/–
B1 [5]
B1 [4]
G1 [9]
G1 [8]
G1 [7]
G1 [6]
G1 [5]
B2 [5]
B2 [4]
G2 [9]
G2 [8]
G2 [7]
G2 [6]
G2 [5]
TC1+/–
DE
VSYNC HSYNC B1 [9]
B1 [8]
B1 [7]
B1 [6]
DE
VSYNC HSYNC B2 [9]
B2 [8]
B2 [7]
B2 [6]
TD1+/–
data11
B1 [3]
B1 [2]
G1 [3]
G1 [2]
R1 [3]
R1 [2]
data11
B2 [3]
B2 [2]
G2 [3]
G2 [2]
R2 [3]
R2 [2]
TE1+/–
data12
B1 [1]
B1 [0]
G1 [1]
G1 [0]
R1 [1]
R1 [0]
data12
B2 [1]
B2 [0]
G2 [1]
G2 [0]
R2 [1]
R2 [0]
TA2+/–
G1 [4]
R1 [9]
R1 [8]
R1 [7]
R1 [6]
R1 [5]
R1 [4]
G2 [4]
R2 [9]
R2 [8]
R2 [7]
R2 [6]
R2 [5]
R2 [4]
TB2+/–
B1 [5]
B1 [4]
G1 [9]
G1 [8]
G1 [7]
G1 [6]
G1 [5]
B2 [5]
B2 [4]
G2 [9]
G2 [8]
G2 [7]
G2 [6]
G2 [5]
TC2+/–
DE
VSYNC HSYNC B1 [9]
B1 [8]
B1 [7]
B1 [6]
DE
VSYNC HSYNC B2 [9]
B2 [8]
B2 [7]
B2 [6]
TD2+/–
data11
B1 [3]
B1 [2]
G1 [3]
G1 [2]
R1 [3]
R1 [2]
data11
B2 [3]
B2 [2]
G2 [3]
G2 [2]
R2 [3]
R2 [2]
TE2+/–
data12
B1 [1]
B1 [0]
G1 [1]
G1 [0]
R1 [1]
R1 [0]
data12
B2 [1]
B2 [0]
G2 [1]
G2 [0]
R2 [1]
R2 [0]
TCLK2+/–
(Regardless of the Data Latency)
Data bits “data11, data12” are available for additional data transmission.
Fig.12-2
Copyright©2013 THine Electronics, Inc.
15/22
THine Electronics,Inc.
THC63LVD1027_Rev.3.00_E
Single-in / Dual-out mode
In Single-in / Dual-out mode, RCLK2+/- must be High-Z.
LVDS-Rx Input Mapping
RCLK1+/–
RA1+/–
G1 [4]
R1 [9]
R1 [8]
R1 [7]
R1 [6]
R1 [5]
R1 [4]
G2 [4]
R2 [9]
R2 [8]
R2 [7]
R2 [6]
R2 [5]
R2 [4]
RB1+/–
B1 [5]
B1 [4]
G1 [9]
G1 [8]
G1 [7]
G1 [6]
G1 [5]
B2 [5]
B2 [4]
G2 [9]
G2 [8]
G2 [7]
G2 [6]
G2 [5]
RC1+/–
DE
VSYNC HSYNC B1 [9]
B1 [8]
B1 [7]
B1 [6]
DE
VSYNC HSYNC B2 [9]
B2 [8]
B2 [7]
B2 [6]
RD1+/–
data11
B1 [3]
B1 [2]
G1 [3]
G1 [2]
R1 [3]
R1 [2]
data11
B2 [3]
B2 [2]
G2 [3]
G2 [2]
R2 [3]
R2 [2]
RE1+/–
data12
B1 [1]
B1 [0]
G1 [1]
G1 [0]
R1 [1]
R1 [0]
data12
B2 [1]
B2 [0]
G2 [1]
G2 [0]
R2 [1]
R2 [0]
Hi-Z
RCLK2+/–
RA2+/–
no care
RB2+/–
no care
RC2+/–
no care
RD2+/–
no care
RE2+/–
no care
LVDS-Tx Output Mapping
TCLK1+/–
TA1+/–
G1 [4]
R1 [9]
R1 [8]
R1 [7]
R1 [6]
R1 [5]
R1 [4]
TB1+/–
B1 [5]
B1 [4]
G1 [9]
G1 [8]
G1 [7]
G1 [6]
G1 [5]
TC1+/–
DE
VSYNC
HSYNC
B1 [9]
B1 [8]
B1 [7]
B1 [6]
TD1+/–
data11
B1 [3]
B1 [2]
G1 [3]
G1 [2]
R1 [3]
R1 [2]
TE1+/–
data12
B1 [1]
B1 [0]
G1 [1]
G1 [0]
R1 [1]
R1 [0]
TA2+/–
G2 [4]
R2 [9]
R2 [8]
R2 [7]
R2 [6]
R2 [5]
R2 [4]
TB2+/–
B2 [5]
B2 [4]
G2 [9]
G2 [8]
G2 [7]
G2 [6]
G2 [5]
TC2+/–
DE
VSYNC
HSYNC
B2 [9]
B2 [8]
B2 [7]
B2 [6]
TD2+/–
data11
B2 [3]
B2 [2]
G2 [3]
G2 [2]
R2 [3]
R2 [2]
TE2+/–
data12
B2 [1]
B2 [0]
G2 [1]
G2 [0]
R2 [1]
R2 [0]
TCLK2+/–
( Regardless of the Data Latency )
Data bits “data11, data12” are available for additional data transmission.
Fig.12-3(a)
Copyright©2013 THine Electronics, Inc.
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THine Electronics,Inc.
THC63LVD1027_Rev.3.00_E
Single Link Input
RCLK1+
DE
DE
DE
DE
DE
DE
RC1+/Ry1+/-
A
B
C
D
y= A, B, C, D, E
Dual Link Output
TCLK1+
TCLK2+
DE
DE
DE
TC1+/TC2+/Ty1+/-
A
C
Ty2+/-
B
D
( Regardless of the Data Latency )
Schematic diagram
of DE transition
Single-in / Dual-out mode uses DE signal L-to-H-edge to start distribution of input data.
Fig.12-3(b)
Copyright©2013 THine Electronics, Inc.
17/22
THine Electronics,Inc.
THC63LVD1027_Rev.3.00_E
Dual-in / Single-out mode
LVDS-Rx Input Mapping
RCLK1+/–
RA1+/–
G1 [4]
R1 [9]
R1 [8]
R1 [7]
R1 [6]
R1 [5]
R1 [4]
RB1+/–
B1 [5]
B1 [4]
G1 [9]
G1 [8]
G1 [7]
G1 [6]
G1 [5]
RC1+/–
DE
VSYNC
HSYNC
B1 [9]
B1 [8]
B1 [7]
B1 [6]
RD1+/–
data11
B1 [3]
B1 [2]
G1 [3]
G1 [2]
R1 [3]
R1 [2]
RE1+/–
data12
B1 [1]
B1 [0]
G1 [1]
G1 [0]
R1 [1]
R1 [0]
RA2+/–
G2 [4]
R2 [9]
R2 [8]
R2 [7]
R2 [6]
R2 [5]
R2 [4]
RB2+/–
B2 [5]
B2 [4]
G2 [9]
G2 [8]
G2 [7]
G2 [6]
G2 [5]
RC2+/–
DE
VSYNC
HSYNC
B2 [9]
B2 [8]
B2 [7]
B2 [6]
RD2+/–
data21
B2 [3]
B2 [2]
G2 [3]
G2 [2]
R2 [3]
R2 [2]
RE2+/–
data22
B2 [1]
B2 [0]
G2 [1]
G2 [0]
R2 [1]
R2 [0]
RCLK2+/–
LVDS-Tx Output Mapping
TCLK1+/–
TA1+/–
G1 [4]
R1 [9]
R1 [8]
R1 [7]
R1 [6]
R1 [5]
R1 [4]
G2 [4]
R2 [9]
R2 [8]
R2 [7]
R2 [6]
R2 [5]
R2 [4]
TB1+/–
B1 [5]
B1 [4]
G1 [9]
G1 [8]
G1 [7]
G1 [6]
G1 [5]
B2 [5]
B2 [4]
G2 [9]
G2 [8]
G2 [7]
G2 [6]
G2 [5]
TC1+/–
DE
VSYNC HSYNC B1 [9]
B1 [8]
B1 [7]
B1 [6]
DE
VSYNC HSYNC B2 [9]
B2 [8]
B2 [7]
B2 [6]
TD1+/–
data11
B1 [3]
B1 [2]
G1 [3]
G1 [2]
R1 [3]
R1 [2]
data21
B2 [3]
B2 [2]
G2 [3]
G2 [2]
R2 [3]
R2 [2]
TE1+/–
data12
B1 [1]
B1 [0]
G1 [1]
G1 [0]
R1 [1]
R1 [0]
data22
B2 [1]
B2 [0]
G2 [1]
G2 [0]
R2 [1]
R2 [0]
TCLK2+/–
Hi-Z
TA2+/–
Hi-Z
TB2+/–
Hi-Z
TC2+/–
Hi-Z
TD2+/–
Hi-Z
TE2+/–
Hi-Z
( Regardless of the Data Latency )
Data bits “data11, data12, data21, data22” are available for additional data transmission.
Fig.12-4
Copyright©2013 THine Electronics, Inc.
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THine Electronics,Inc.
THC63LVD1027_Rev.3.00_E
Note
1)LVDS input pin connection
When LVDS line is not drived from the previous device, the line is pulled up to 3.3V internally in THC63LVD1027.
This can cause violation of absolute maximum ratings to the previous LVDS Tx device whose operating condition is
lower voltage power supply than 3.3V. This phenomenon may happen at power on phase of the whole system including
THC63LVD1027. One solution for this problem is PD=L control during no LVDS input period because pull-up resistors are cut off at power down state.
LVDS Tx side PCB
LVDS Rx side PCB
VDD
Low VDD
THC63LVD1027
LVDS Tx
or
LVDS Tx
integrated
device
LVDS input buffer
Internal circuit of THC63LVD1027
2)Power On Sequence
Don’t input RCLK#+/- before THC63LVD1027 is on in order to keep absolute maximum ratings.
Copyright©2013 THine Electronics, Inc.
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THine Electronics,Inc.
THC63LVD1027_Rev.3.00_E
3)Cable Connection and Disconnection
Don’t connect and disconnect the LVDS cable, when the power is supplied to the system.
4)GND Connection
Connect the each GND of the PCB which Transmitter, Receiver and THC63LVD1027 on it.
It is better for EMI reduction to place GND cable as close to LVDS cable as possible.
5)Multi Drop Connection
Multi drop connection is not recommended.
THC63LVD1027
TCLK1,2-
LVDS Rx
TCLK1,2+
LVDS Rx
6)Asynchronous use
Asynchronous use such as following systems are not recommended.
Page.11 tCK12 spec should be kept.
CLKOUT
IC
LVDS Tx
RCLK1+/-
LVDS Tx
RCLK2+/-
DATAOUT
CLKOUT
DATAOUT
THC63LVD1027
Asynchronous use such as following systems are not recommended.
CLKIN
TCLK1+/-
LVDS Rx
DATAIN
IC
THC63LVD1027
TCLK2+/-
Copyright©2013 THine Electronics, Inc.
LVDS Rx
DATAIN
20/22
THine Electronics,Inc.
THC63LVD1027_Rev.3.00_E
Package
THC63LV1027
1
17.00
± 0.10
± 0.20
6.10 ± 0.10
8.10
S
0.50
± 0.10
0.10
S
0.20 TYP
1.10 MAX
0.90
3.05 REF
4.45 REF
± 0.10
0 ~ 8 deg
0.25 BSC
0.60
0.05 ~ 0.15
± 0.15
1.00 REF
Detail of Lead End
Unit: mm
Exposed PAD is GND and must be soldered to PCB.
Copyright©2013 THine Electronics, Inc.
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THine Electronics,Inc.
THC63LVD1027_Rev.3.00_E
Notices and Requests
1. The product specifications described in this material are subject to change without prior notice.
2. The circuit diagrams described in this material are examples of the application which may not
always apply to the customer's design. We are not responsible for possible errors and omissions in
this material. Please note if errors or omissions should be found in this material, we may not be
able to correct them immediately.
3. This material contains our copy right, know-how or other proprietary. Copying or disclosing to
third parties the contents of this material without our prior permission is prohibited.
4. Note that if infringement of any third party's industrial ownership should occur by using this
product, we will be exempted from the responsibility unless it directly relates to the production
process or functions of the product.
5. This product is presumed to be used for general electric equipment, not for the applications which
require very high reliability (including medical equipment directly concerning people's life,
aerospace equipment, or nuclear control equipment). Also, when using this product for the
equipment concerned with the control and safety of the transportation means, the traffic signal
equipment, or various Types of safety equipment, please do it after applying appropriate measures
to the product.
6. Despite our utmost efforts to improve the quality and reliability of the product, faults will occur
with a certain small probability, which is inevitable to a semi-conductor product. Therefore, you
are encouraged to have sufficiently redundant or error preventive design applied to the use of the
product so as not to have our product cause any social or public damage.
7. Please note that this product is not designed to be radiation-proof.
8. Customers are asked, if required, to judge by themselves if this product falls under the category of
strategic goods under the Foreign Exchange and Foreign Trade Control Law.
THine Electronics, Inc.
E-mail : [email protected]
Copyright©2013 THine Electronics, Inc.
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THine Electronics,Inc.
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