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DATASHEET
Laser Diode Driver with APC Amplifier for Printers
ISL58115
Features
The ISL58115 is a high-performance laser driver that provides
controlled current to grounded laser diodes. A bias current is
summed with the switched current at the IOUT output, allowing
the user to optimize laser diode performance.
• Voltage-controlled Output Current Source
Output switched current flows when the LVDS signal DATA is high.
The output current returns to the fixed-threshold value when
DATA is low. Complete IOUT shut-off is achieved by holding the
CHPEN low, which will override all other control pins.
A fast settling APC amplifier connects directly to the monitor
diode. The ISL58115 does not exhibit any time-dependent droop
since the calibration gain is stored as a digital number.
ISL58115CRZ-T13
PART
MARKING
58115 CRZ
PACKAGE
Tape & Reel
(Pb-free)
24 Ld QFN
• Internal LVDS Termination Resistors
• 300MHz Switching
• Up to 110mA Output Current
• Rise Time < 500ps
• Fall Time < 500ps
• APC Loop for Write Power Control
• Fast Settling APC Amplifier
• Single +5V Supply (±10%)
Ordering Information
PART NUMBER
(Notes 1, 2)
• Very Few External Components Needed
• Disable Feature for Power-Up Protection and Conserving Power
• Zero Droop
PKG.
DWG. #
L24.4x5B
• Pb-Free (RoHS compliant)
Load Configuration
• Common-cathode LD, Common-anode PD
NOTES:
IOUT PDIN
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pbfree material sets, molding compounds/die attach materials, and
100% matte tin plate plus anneal (e3 termination finish, which is
RoHS compliant and compatible with both SnPb and Pb-free
soldering operations). Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
GND
Applications
• Laser Printer Applications
• Laser Diode Current Switching
July 29, 2013
FN6671.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2010, 2013. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL58115
Pin Configuration
20 HPSB
21 CALB
22 VC
23 NC
24 GND
ISL58115
(24 LD QFN)
TOP VIEW
NC 1
19 NC
DATA 2
18 GND
DATAB 3
17 VCC
THERMAL
THERMAL
PAD
GND 4
16 IOUT
13 PDIN
Pin Descriptions
IVOUT 12
NC 7
RSET 11
14 VCC
RBIAS 10
NC 6
RPS 9
15 VCC
CHPEN 8
DIS 5
PIN
NAME
PIN
NUMBER
I/O
TYPE
DATA
2
I
LVDS
Input data to control Laser Switching Control
DATAB
3
I
LVDS
Input data to control Laser Switching Control
GND
4, 18, 24
DIS
5
NC
DESCRIPTION
Ground
Ground
I
Digital
Disable output current
1, 6, 7, 19,
23
I
No connect
CHPEN
8
I
Digital
Chip Enable; Pull High to Enable
RPS
9
I
Analog
External resistor sets the Hsync detection power
RBIAS
10
Analog
Resistors set bias threshold current. See “Applications Information” on page 7 for more details
RSET
11
O
Analog
Bandgap derived internal reference
IVOUT
12
O
Analog
Calibrate channel with an external trimpot to GND
Adjust the IV amplifier gain
PDIN
13
I
Analog
Photo Diode input to the IV amplifier
VCC
14, 15, 17
Power
Supply Voltage
IOUT
16
O
Analog
Laser Current Output
HPSB
20
I
TLL
Hsync Power Select Enable; Active Low. During HPSB is low AND Hsync signal from photo
detector is low, the output current is set by RPS
CALB
21
I
TTL
Samples the laser power for APC; Active Low
VC
22
I
Analog
Thermal
Pad
-
No connect
Voltage Controlling Laser Switching Current; 0V to 2V input for 0% to 100% output
Exposed Thermal Pad should be soldered to GND
NOTE: Pins with the same name are not necessary internally connected together. LDD pins must not be used for connecting together external components
or features.
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2
FN6671.1
July 29, 2013
ISL58115
Absolute Maximum Ratings (TA = +25°C)
Recommended Operating Conditions
Voltages Applied to:
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6.0V
All Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VCC + 0.5V
IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VCC
LVDS Max Current Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
ESD Rating
Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . . . 3kV
Charged Device Model (Tested per JESD22-C110D) . . . . . . . . . . . .1.5kV
Machine Model (Tested per JESD22-A115B) . . . . . . . . . . . . . . . . . . 200V
Latch Up (Tested per JESD78B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical, Notes 3, 4)
JA (°C/W)
24 Ld QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
42
Operating Ambient Temperature Range . . . . . . . . . . . . . . . . 0°C to +85°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
3. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
4. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise
noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
VCC = 5.0V, DIS = Lo, TA = +25°C, RSET = 3.0kΩ, unless otherwise indicated.
DESCRIPTION
CONDITIONS
MIN
(Note 5)
TYP
MAX
(Note 5)
UNIT
4.5
5.0
5.5
V
VCC
Supply Voltage
ISdis
Supply Current (Disabled)
DIS = SLPEN = HPSB = Hi
0.3
1.0
mA
IS2
Supply Current (Standby)
DIS = Hi
22
31
mA
VLO
Low Voltage Threshold
All TTL inputs
1.2
V
VHI
High Voltage Threshold
All TTL inputs
2.8
ILO
Input Low Current
All TTL inputs
-20
IHI
Input High Current
All TTL inputs
VSHUT
VCC Shut Down Voltage
VLVDS
LVDS Input Level
Differential, with Vcm = 1.25V
VCMR
LVDS Common Mode Voltage Range
300mVP-P
VC
Control Voltage
RTermination
Internal LVDS Termination Resistor
Laser Amplifier Output
PARAMETER
V
-10
2.5
µA
1
µA
2.9
V
0.2
V
0.2
2.2
V
0.3
2.6
V

180
VCC = 5.0V, DIS = Lo, TA = +25°C, RSET = 3.0kΩ, unless otherwise indicated.
DESCRIPTION
CONDITIONS
MIN
(Note 5)
TYP
MAX
(Note 5)
UNIT
IOUT
IOUTSW-max
Switched Output Current
VC = 2.6V
75
81
mA
IOUTBIAS-max
Bias Output Current
RBIAS = 1k
20
35
mA
IOFF
Output Off Current
DIS pin set to HIGH
-75
0
FREQOP
Operating Frequency
IOUT = maximum switch current
200
IOUTPSRR
IOUT Supply Sensitivity
IOUT = 20mA, VCC = 5V ±10%
13
%/V
tR-IOUT
IOUT Rise Time
10% to 90%; typical LD for printer
0.5
ns
tF-IOUT
IOUT Fall Time
90% to 10%; typical LD for printer
0.7
ns
OUTENx_ton
IOUT on Propagation Delay
DATAx crossing to IOUT at 50% of final value
Submit Document Feedback
3
+75
µA
MHz
5
7
ns
FN6671.1
July 29, 2013
ISL58115
Laser Amplifier Output
PARAMETER
VCC = 5.0V, DIS = Lo, TA = +25°C, RSET = 3.0kΩ, unless otherwise indicated.
DESCRIPTION
VCBW
CONDITIONS
MIN
(Note 5)
Bandwidth of VC
APC Electrical Specifications
PARAMETER
TYP
MAX
(Note 5)
UNIT
14
MHz
VCC = 5.0V, DIS = Lo, TA = +25°C, RSET = 3.0kΩ, unless otherwise indicated.
DESCRIPTION
CONDITIONS
MIN
(Note 5)
TYP
MAX
(Note 5)
UNIT
tAPC-50
APC Response Time
0V to 2V step of VC
7.5
µs
IVgain
IV Amplifier Gain
External resistor RIV = 500
3.1
k
NOTE:
5. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
Timing Diagram
CHPEN
DIS
VC
CALB
DATA(LVDS)
HPSB
FIXED BIAS
LEVEL
SET BY RBIAS
IOUT
OFF
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4
SET BY
RPS
IOUT RISES TO
ITS VC DEFINED
VALUE USING
THE LAST
CALIBRATION
GAIN SETTING IN
<1µs
OFF
FN6671.1
July 29, 2013
ISL58115
IOUT Control
CHPEN
DIS
DATA
CALB
HPSB
IOUT
COMMENTS
x
x
OFF
CHPEN is slow to enable
Full standby current, no IOUT
POWER-DOWN (SLEEP MODE)
0
x
x
STANDBY (FULL STANDBY CURRENT, NO IOUTS)
1
1
x
x
x
OFF
1
0
x
1
1
ON, BIAS ONLY
1
0
x
0
1
ON, CAL to level set by VC
1
0
1
1
1
ON
0
x
1
0
Hsync power
x
1
x
INVALID
NORMAL DRIVE
Hsync POWER
1
Output current defined by RPS
INVALID LOGIC COMBINATION
1
0
NOTE: DATA1 and DATA2: 1 implies DATA>DATAB, 0 implies DATA<DATAB
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5
FN6671.1
July 29, 2013
ISL58115
Typical Application
DATA
GND
+
-
DATAB
BEAD
+5V
LOGIC CNTRL
4.7µF
VCC
+
-
68
0.1µF
SWITCHING
DRIVER
GAIN
CONTROL
IOUT
VC
RPS
+
-
GND
LASER
VCC
VCC
RSET
0.1µF
3kΩ
RBIAS
BANDGAP
REF.
3kΩ
NC
NC
NC
NC
CALB
PDIN
+
-
HPSP
CAL.
POT
IV AMPLIFIER
DIS
LOGIC BLOCK
CHPEN
IVOUT
5kΩ
NC
GND
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FN6671.1
July 29, 2013
ISL58115
Applications Information
During calibration mode, the internal servo control will bring the
laser diode output power level to match the voltage control level
set by VC voltage.
APC System Overview
As the laser heats up (or ages) its output power declines relative
to the applied current, so some form of power control is required.
The laser is optically coupled to a photo-diode, so that the laser’s
optical output can be measured. Laser optical output power is
controlled by comparing the externally applied control voltage
with the voltage produced by the IV-amplifier which converts the
photo-diode’s output current into a voltage. Since the calibrated
gain is stored as a digital number in a register, the ISL58115
exhibits none of the time-dependent droop that is seen in most
printers' laser diode drivers. This is of particular importance
during high dot/inch graphics modes where the line may be
slowed down very significantly to allow 2400 dots per inch or
even more.
Fixed-Threshold Laser Bias Control
When a laser is driven from below threshold to well above
threshold, it exhibits a few cycles of a damped oscillation. The
amplitude of this oscillation is minimized when the laser is kept
above threshold. The “fixed” bias mode is set by asserting a logic
Low on the SLPEN pin. To set the laser bias threshold currents,
IBIAS, connect external resistors from RBIAS pins to GND. Figure
1 shows value of RBIAS corresponding to desired bias current.
IBIAS (mA)
100
Horizontal edge detection
When HPSB is low, the output current is set by RPS. Asserting
HPSB low overrides both channel data inputs. HPSB should not
be asserted low during a calibration cycle. When HPSB is low, the
desired output current IRPS is governed by the following
equation:
RPS
1.05V
I RPS = 40  -----------------------  ---------------CalDAC R SET
(EQ. 3)
where the CalDAC setting (from the last write power calibration)
ensures laser temperature and aging compensation. The
CalDAC’s units are ohms. Full scale is about 380Ω and CalDAC is
defined as CalDAC = 255/code*380Ω.
The horizontal sync pulse is meant to be a power level that
overrides VC calibration and sets the output current to a fixed
level.
Typical Application
Upon the printer being powered up, the lasers should be
calibrated. This would establish nominal light power outputs,
typically a few milliwatts at the laser regardless of the ambient
temperature and also any laser aging.
Once everything is ready for printing, the paper is in position and
the mirror-motor is phase-locked then the print line(s) can be
written. Before, or after, the beam is over the photo-sensitive
drum, each laser can be re-calibrated. This continual recalibration will compensate for any temperature drift of the laser,
especially at the initial warming up period.
10
1
0.1
1
10
RBIAS (k)
FIGURE 1. RBIAS vs BIAS CURRENT
Scaling External Resistors
RSET is used to scale the switching output current. Switching
output current, ISW, is the function of VC and RSET.
2
VC
I SW = I SW Gain   ---------------- – ---------------
R

R
DAC
SET
(EQ. 1)
Where ISWGain = ~17, RDAC = 400.
RBIAS sets bias threshold current. Figure 1 exhibits the
relationship between IBIAS and RBIAS. The bias current is set as
Equation 2:
InternalVref
I BIAS = BiasChannelGain  -----------------------------------R BIAS
(EQ. 2)
Where BiasChannelGain = ~40, InternalVref = 1.0V.
Controlling the Sampling
The switching levels are sampled independently. This can be
done during the “off-paper” period.
Submit Document Feedback
7
Since the calibrated gain is stored as a digital number in a
register, the ISL58115 exhibits no time-dependent droop. With
no droop to degrade performance the only limitation now is the
lasers' own temperature change along the line. This in turn can
be compensated for to some extent by adding a data-dependent
compensation signal to the analog VCx input pin. It may be found
that in fast draft modes for example, that the laser temperature
change is sufficiently small that many lines can be written before
the laser(s) need to be re-calibrated. If the printed page has a low
enough duty cycle, no re-calibration may be needed at all.
The ISL58115 has analog voltage inputs to allow the laser power
level to be adjusted during the line. Typically this would be driven
with a PWM, low bandwidth signal to compensate for the
differing beam path length as the beam is swept from one side
of the page to the other.
Undervoltage, overcurrent and over-temperature error conditions
are ORed together and made available on the ERRB pin.
Note on Illegal Logic Combination
In normal use, CALB going low (active) without DIS being low
(active) would be meaningless. Likewise with HPSB going low
(active). Therefore, a combination of these should be avoided at
all times. If this combination is applied, the chip will not work
properly. To exit this mode, either set CALB to Low or/and DIS to
Hi.
FN6671.1
July 29, 2013
ISL58115
Power Supply Decoupling
DIS
CALB
HPSB
FIGURE 2. ILLEGAL COMBINATION
Due to the high values of current being switched rapidly on and
off, it is important to ensure that the power supply is well
decoupled to ground. During switching, the VCC undergoes severe
current transients, thus every effort should be made to decouple
the VCC as close to the package as possible. Symptoms that
could arise include poor rise/fall times, current overshoot, and
poor settling response. It is recommended that VCC inputs
should be bypassed with 4.7µF // 100nF // 470pF to GND
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest Rev.
DATE
REVISION
CHANGE
July 29, 2013
FN7659.1
Conversion to New Intersil Template.
June 15, 2010
FN7659.0
Initial release.
About Intersil
Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management
semiconductors. The company's products address some of the largest markets within the industrial and infrastructure, personal
computing and high-end consumer markets. For more information about Intersil, visit our website at www.intersil.com.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting
www.intersil.com/en/support/ask-an-expert.html. Reliability reports are also available from our website at
http://www.intersil.com/en/support/qualandreliability.html#reliability
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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FN6671.1
July 29, 2013
ISL58115
Package Outline Drawing
L24.4x5B
24 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 10/06
4.00
PIN 1
A
2.50
24X0.40
PIN #1 INDEX AREA
CHAMFER 0.400
× X 45°
INDEX AREA
B
6
20
24
6
1
0.50
19
5.00
3.50
0.5x6=3.00 REF
7
13
12
0.10
4X
8
0.25±0.05
0.50
TOP VIEW
0.10 M C A B
0.5x4=2.00 REF
BOTTOM VIEW
SEE DETAIL X''
0.10 C
C
SEATING PLANE
0.08 C
0.90±0.10
(24x0.25)
SIDE VIEW
(4.80 TYP)
(3.50)
(20x0.50)
0 . 20 REF
(2.50)
5
C
(24x0.60)
(3.80 TYP)
0 . 00 MIN.
0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.20mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
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FN6671.1
July 29, 2013
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