DATASHEET

ISL9216, ISL9217
®
Data Sheet
November 2, 2007
8 to 12 Cell Li-Ion Battery Overcurrent
Protection and Analog Front End Chip Set
The ISL9216 and ISL9217 chipset provides overcurrent
protection and voltage monitoring for multi-cell li-ion battery
packs consisting of 8 to 12 cells. When used together, these
devices provide integrated overcurrent protection circuitry,
short circuit protection, an internal voltage regulator, internal
cell balancing switches, cell voltage level shifters, and drive
circuitry for external FET devices that control pack charge
and discharge. Level shifting of the analog output voltage
from the upper cells and communication between the chips
is handled automatically.
Overcurrent and short circuit thresholds reside in internal
RAM registers and are selected independently via software
using an I2C serial interface. Detection and time-out delays
can be individually varied using internal registers.
Using an internal analog multiplexer, the device provides
monitoring of cell voltage by a separate microcontroller with
A/D converter. Software on this microcontroller implements
all battery control functionality, except for overcurrent and
short circuit shutdown.
Applications
• Power Tools
• Battery Backup Systems
• E-bikes
FN6488.1
Features
• Software selectable overcurrent protection levels and
variable protect detection/release times
- 4 Discharge overcurrent thresholds
- 4 Short circuit thresholds
- 4 Charge overcurrent thresholds
- 8 Overcurrent delay times (Charge)
- 8 Overcurrent delay times (Discharge)
- 2 Short circuit delay times (Discharge)
• Automatic FET turn-off and cell balance disable on
reaching external (battery) or internal (IC) temperature
limit
• Automatic over-ride of cell balance on reaching internal
(IC) temperature limit
• Fast short circuit pack shutdown
• Can use current sense resistor, FET rDS(ON), or Sense
FET for overcurrent detection
• Four battery backed software controlled flags
• Allows three different FET controls:
- Back-to-back N-Channel FETs for charge and discharge
control
- Single N-Channel FET for discharge control
- N-Channel FET for discharge, with separate, optional
(smaller) back-to-back FET for charge
• Chips cascade for packs of 8 to 12 cells
• Portable Test Equipment
• Integrated charge/discharge FET drive circuitry with
200µA (typ) turn on current and 150mA (typ) discharge
FET turn off current
• Medical Systems
• Hybrid Vehicle
• Military Electronics
• 10% accurate 3.3V voltage regulator (35mA out with
external NPN transistor having current gain of 70)
Ordering Information
• Cell voltage monitor accurate to within 25mV
PART NUMBER
(Note)
PART
MARKING
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL9216IRZ*
ISL9216 IRZ
32 Ld 5x5 QFN
L32.5x5B
ISL9217IRZ*
921 7IRZ
24 Ld 4x4 QFN
L24.4x4D
• Monitored cell voltage output stable in 100µs
• Internal cell balancing FETs handle up to 200mA of
balancing current for each cell (with the number of cells
being balanced limited by the maximum power dissipation
of 400mW)
*Add “-T” suffix for tape and reel. Please refer to TB347 for details
on reel specifications.
• Simple I2C host interface
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets; molding compounds/die attach
materials and 100% matte tin plate PLUS ANNEAL - e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
• Sleep operation with programmable negative edge or
positive edge wake-up
1
• <10µA sleep mode
• Pb-free (RoHS compliant)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL9216, ISL9217
Pinouts
ISL9216 (LOWER)
(32 LD 5X5 QFN)
TOP VIEW
RGO
TEMP3V
19
RGC
RGC
20
WKUP
WKUP
21
SDA
SDAO
22
SCL
SCL
23
SCLHV
NC
24
SDAOHV
VC7/VCC
ISL9217 (UPPER)
(24 LD 4X4 QFN)
TOP VIEW
32
31
30
29
28
27
26
25
16 AO
SDAIHV
3
22 VMON
VCELL5
4
15 NC
VCELL6
4
21 CFET
CB5
5
14 VSS
WKUPR
5
20 DFET
VCELL4
6
13 CB1
VCELL5
6
19 CSENSE
CB5
7
18 DSENSE
VCELL4
8
17 DSREF
7
8
9
10
11
12
2
9
10
11
12
13
14
15
16
VSS
3
CB1
CB6
VCELL1
23 AO
CB2
2
VCELL2
VC7/VCC
CB3
17 SDAI
VCELL3
2
CB4
VCELL6
VCELL1
24 TEMPI
CB2
1
VCELL2
HVI2C
CB3
18 RGO
VCELL3
1
CB4
CB7
FN6488.1
November 2, 2007
ISL9216, ISL9217
Functional Diagram
ISL9217
3.3VDC
REGULATOR
VC7/VCC
RGO
CELL
VOLTAGES
CB7
RGC
VCELL6
CB6
VCELL5
CB5
VCELL4
CB4
VCELL3
MUX
7
INTERNAL
TEMPERATURE
SENSOR/
COMPARATOR
LEVEL
SHIFTERS/
CELL
BALANCE
CIRCUITS
OSC
REGISTERS
CB3
VCELL2
POWER
CONTROL
CONTROL
LOGIC
CB2
VCELL1
CB1
I2C I/F
BACKUP
SUPPLY
VSS
WKUPR
AO
WKUP
SCL SDAO SDAI
SCLHV SDAIHV SDAOHV HVI2C
ISL9216
SCL
SDA
LEVEL/SHIFTERS
VC7/VCC
I2C I/F
CELL
VOLTAGES
VCELL6
7
MUX
2
POWER
CONTROL
VCELL5
CB5
VCELL4
CB4
VCELL3
LEVEL
SHIFTERS/
CELL
BALANCE
CIRCUITS
REGISTERS
OVERCURRENT
PROTECTION
CIRCUITS
(THRESHOLD
DETECT AND
TIMING)
CB3
VCELL2
RGO
CONTROL
LOGIC
FET CONTROL
CIRCUITRY
CB1
RGC
3.3VDC
REGULATOR
CB2
VCELL1
WKUP
OSC
TEMPERATURE
SENSOR,
INT/EXT
COMPARATOR,
EXT TEMP
3
VMON
CFET
DFET
VSS
DSREF
DSENSE
CSENSE
BACKUP
SUPPLY
AO
TEMPI TEMP3V
FN6488.1
November 2, 2007
ISL9216, ISL9217
Pin Descriptions
SYMBOL
DESCRIPTION
VC7/VCC Battery Cell 7 Voltage Input/VCC Supply. This pin is used to monitor the voltage of this battery cell externally at pin AO. This pin also
provides the operating voltage for the IC circuitry.
VCELLN
Battery Cell N Voltage Input. This pin is used to monitor the voltage of this battery cell externally at pin AO. VCELLN connects to the
positive terminal of CELLN and the negative terminal of CELLN+1.
CBN
Cell Balancing FET Control Output N. This internal FET diverts a fraction of the current around a cell while the cell is being charged
or adds to the current pulled from a cell during discharge in order to perform a cell voltage balancing operation. This function is generally
used to reduce the voltage on an individual cell relative to other cells in the pack. The cell balancing FETs are turned on or off by an
external controller.
VSS
Ground. This pin connects to the most negative terminal in the battery string.
DSREF
Discharge Current Sense Reference (ISL9216 only). This input provides a separate reference point for the charge and discharge
current monitoring circuits. with a separate reference connection, it is possible to minimize errors that result from voltage drops on the
ground lead when the load is drawing large currents. If a separate reference is not necessary, connect this pin to VSS.
DSENSE Discharge Current Sense Monitor (ISL9216 only). This input monitors the discharge current by monitoring a voltage. It can monitor
the voltage across a sense resistor, or the voltage across the DFET, or by using a FET with a current sense pin. The voltage on this
pin is measured with reference to DSREF.
CSENSE Charge Current Sense Monitor (ISL9216 only). This input monitors the charge current by monitoring a voltage. It can monitor the
voltage across a sense resistor, or the voltage across the CFET, or by using a FET with a current sense pin. The voltage on this pin is
measured with reference to VSS.
DFET
Discharge FET Control (ISL9216 only). The ISL9216 controls the gate of a discharge FET through this pin. The power FET is a NChannel device. The FET is turned on only by the microcontroller. The FET can be turned off by the microcontroller, but the ISL9216
can also turn off the FET in the event of an overcurrent or short circuit condition. If the microcontroller detects an undervoltage condition
on any of the battery cells, it will turn off the FET off by controlling this output with a control bit.
CFET
Charge FET Control (ISL9216 only). The ISL9216 controls the gate of a charge FET through this pin. The power FET is a N-Channel
device. The FET is turned on only by the microcontroller. The FET can be turned off by the microcontroller, but the ISL9216 can also
turn off the FET in the event of an overcurrent condition. If the microcontroller detects an overvoltage condition on any of the battery
cells, it will turn off the FET off by controlling this output with a control bit.
VMON
Discharge Load Monitoring (ISL9216 only). In the event of an overcurrent or short circuit condition, the microcontroller can enable
a series diode and resistor that connects between the VMON pin and VSS. When FETs open because of an overcurrent or short circuit
condition, and the load remains, the voltage at VMON will be near the VCC voltage. When the load is released, the voltage at VMON
drops below a threshold indicating that the overcurrent or short circuit condition is resolved. At this point, the LDFAIL flag is cleared
and operation can resume.
AO
Analog Multiplexer Output. The analog output pin is used by an external microcontroller to monitor the cell voltages and temperature
sensor voltages. The microcontroller selects the specific voltage being applied to the output by writing to a control register.
TEMP3V Temperature Monitor Output Control (ISL9216 only). This pin outputs a voltage to be used in a divider that consists of a fixed resistor
and a thermistor. The thermistor is located in close proximity to the cells. The TEMP3V output is connected internally to the RGO
voltage through a PMOS switch only during a measurement of the temperature, otherwise the output is off. The TEMP3V output can
be turned on continuously with a special control bit.
Microcontroller Wake-up Control. This pin is also turned on when any of the DSC, DOC, or COC bits are set. This can be used to
wake-up a sleeping microcontroller to respond to overcurrent conditions with its own control mechanism.
TEMPI
Temperature Monitor Input (ISL9216 only). This pin inputs the voltage across a thermistor to determine the temperature of the cells.
When this input voltage drops below TEMP3V/13, an external over-temperature condition exists. The TEMPI voltage is also fed to the
AO output pin through an analog multiplexer so the temperature of the cells can be monitored by the microcontroller.
RGO
Regulated Output Voltage. This pin connects to the emitter of an external NPN transistor and works in conjunction with the RGC pin
to provide a regulated 3.3V. The voltage at this pin provides feedback for the regulator and power for many of the ISL9216 and ISL9217
internal circuits. For the ISL9216, this output also provides the 3.3V output voltage for the microcontroller and other external circuits.
RGC
Regulated Output Control. This pin connects to the base of an external NPN transistor and works in conjunction with the RGO pin to
provide a regulated 3.3V. The RGC output provides the control signal to provide the 3.3V regulated voltage on the RGO pin.
WKUP
Wake-up Voltage. This input wakes up the part when the voltage crosses a turn-on threshold (wake-up is edge triggered) and the
condition of the pin is reflected in the WKUP bit (The WKUP bit is level sensitive).
• WKPOL bit = ”1”: the device wakes up on the rising edge of the WKUP pin. Also, the WKUP bit is HIGH only when the WKUP pin
voltage > threshold.
• WKPOL bit = ”0”, the device wakes up on the falling edge of the WKUP pin. Also, the WKUP bit is HIGH only when the WKUP pin
voltage < threshold.
4
FN6488.1
November 2, 2007
ISL9216, ISL9217
Pin Descriptions (Continued)
SYMBOL
DESCRIPTION
WKUPR
Wake-up Upper Device Signal (ISL9216 only). This output wakes up the ISL9217 (upper device) when the output is turned on by the
microcontroller. Once the upper device is awake, this output can be turned off.
SDA
Serial Data (ISL9216 only). This is the bi-directional data line for an I2C interface.
SCL
Serial Clock. This is the clock line for an I2C communication link.
SDAI
Serial Data Input (ISL9217 only). This pin is a uni-directional I2C serial data input from the ISL9216 to the cascaded ISL9217 device.
This pin connects to the ISL9216 SDAOHV pin.
SDAO
Serial Data Output (ISL9217 only). This pin is a uni-directional I2C serial data output to the ISL9216 from the cascaded ISL9217
device. This pin connects to the ISL9216 SDAIHV pin.
SDAIHV
Serial Data Input (ISL9216 only). This pin is a uni-directional I2C serial data input from the cascaded ISL9217 device to the ISL9216.
This pin connects to the ISL9217 SDAO pin.
SDAOHV Serial Data Output (ISL9216 only). This pin is a uni-directional serial data output from the ISL9216 to the cascaded ISL9217 device.
This pin connects to the ISL9217 SDAI pin.
SCLHV
Serial Clock Output (ISL9216 only). This pin sends clock pulses from the lower device (ISL9216) to the upper device (ISL9217) for
communication between cascaded devices
HVI2C
HV I2C Reference Voltage (ISL9216 only). This is a reference voltage for the ISL9216 to facilitate the communication link between
cascaded devices. Tie this pin on the ISL9216 to the RGO pin of the ISL9217.
5
FN6488.1
November 2, 2007
ISL9216, ISL9217
Absolute Maximum Ratings
Thermal Information
Power Supply Voltage, VCC . . . . . . . . . .VSS - 0.5V to VSS + 36.0V
Cell Voltage, VCELL
VCELLN to (VCELLN-1), VCELL1-VSS . . . . . . . . . . . . -0.5V to 5V
Terminal Voltage, VTERM1
(SCL, SDA, CSENSE, DSENSE, TEMPI, RGO, AO,
TEMP3V, SDAI, SDAO) . . . . . . . . . . . . VSS - 0.5 to VRGO + 0.5V
Terminal Voltage
VTERM2 (CFET, VMON) . . . . . . . . . . . . . . . . . VSS - 22.0V to VCC
VTERM3 (WKUP) . . . . . . . . . . . . . . VSS - 0.5V to VCC(VCC <27V)
VTERM4 (RGC). . . . . . . . . . . . . . . . . . . . . . . . . . VSS - 0.5V to 5V
VTERM5, (SDAOHV, SDAIHV, SCLHV)
. . . . . . . . . . . . . . . . . . . . . . . . VCELL5 - 0.5V to VHVI2C + 0.5V
VTERM6, (all other pins) . . . . . . . . . . . . VSS - 0.5V to VCC + 0.5V
Thermal Resistance (Typical, Notes 1, 2) θJA (°C/W) θJC (°C/W)
32 Ld QFN . . . . . . . . . . . . . . . . . . . . . .
31
2
24 Ld QFN . . . . . . . . . . . . . . . . . . . . . .
32
2
Continuous Package Power Dissipation . . . . . . . . . . . . . . . .400mW
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . -55 to +125°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Operating Voltage
VCC pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2V to 30.1V
VCELL1-VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3V to 4.3V
VCELLN-(VCELLN-1) . . . . . . . . . . . . . . . . . . . . . . . . 2.2V to 4.3V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. θJC, “case temperature” location is at the center of the exposed metal pad on the package underside. See Tech Brief TB379.
Operating Specifications All Specifications Apply to Both the ISL9216 and ISL9217 Separately Over the Recommended Operating
Conditions, Unless Otherwise Specified.
DESCRIPTION
SYMBOL
Operating Voltage
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
31
V
4
9.2
V
1.7
2.3
V
9.2
Power-up Condition 1
VPORVCC VCC voltage (Note 3)
Power-up Condition 2 Threshold
VPOR123 VCELL1 - VSS and VCELL2 - VCELL1 and
VCELL3 - VCELL2 (rising) (Note 3)
Power-up Condition 2 Hysteresis
VPORhys VCELL1 - VSS and VCELL2 - VCELL1 and
VCELL3 - VCELL2 (falling) (Note 3)
1.1
70
3.3V Regulated Voltage
VRGO
0μA < IRGC < 350μA
3.0
3.3
3.3VDC Voltage Regulator Control
Current Limit
IRGC
(Control current at output of RGC.
Recommend NPN with gain of 70+)
0.35
0.50
VCC Supply Current
IVCC1
Power-up defaults, WKUP pin = 0V.
RGO Supply Current
IRGO1
VCC Supply Current
IVCC2
RGO Supply Current
IRGO2
VCC Supply Current
IVCC3
RGO Supply Current
IRGO3
LDMONEN bit = 1, VMON floating, CFET = 1,
DFET = 1, WKPOL bit = 1, VWKUP = 10V,
[AO3:AO0] bits = 06H.
3.6
V
mA
400
510
µA
300
410
µA
400
700
µA
450
650
µA
10
µA
1
µA
14
µA
Default register settings, except SLEEP
bit = 1. WKUP pin = VCELL1
IVCELL1 AO3:AO0 = 0000H
VCELL Input Current - VCELL1
mV
VCELL Input Current - VCELL5
IVCELL1 AO3:AO0 = 0000H (ISL9216 Only)
20
µA
VCELL Input Current - VCELLN
IVCELLN AO3:AO0 = 0000H
10
µA
OVERCURRENT/SHORT CIRCUIT PROTECTION SPECIFICATIONS (ISL9216 only)
Overcurrent Detection Threshold
(Discharge) Voltage Relative to DSREF
(Default in Boldface)
6
VOCD
VOCD = 0.10V (OCDV1, OCDV0 = 0, 0)
0.08
0.10
0.12
V
VOCD = 0.12V (OCDV1, OCDV0 = 0, 1)
0.10
0.12
0.14
V
VOCD = 0.14V (OCDV1, OCDV0 = 1, 0)
0.12
0.14
0.16
V
VOCD = 0.16V (OCDV1, OCDV0 = 1, 1)
0.14
0.16
0.18
V
FN6488.1
November 2, 2007
ISL9216, ISL9217
Operating Specifications All Specifications Apply to Both the ISL9216 and ISL9217 Separately Over the Recommended Operating
Conditions, Unless Otherwise Specified. (Continued)
DESCRIPTION
SYMBOL
Overcurrent Detection Threshold
(Charge) Voltage Relative to DSREF
(Default in Boldface)
Short Current Detection Threshold
(Discharge) Voltage Relative to DSREF
(Default in Boldface)
Load Monitor Input Threshold
(falling edge)
VOCC
VSC
VVMON
Load Monitor Input Threshold
(hysteresis)
MIN
TYP
MAX
UNIT
VOCC = 0.10V (OCCV1, OCCV0 = 0, 0)
TEST CONDITIONS
-0.12
-0.10
-0.07
V
VOCC = 0.12V (OCCV1, OCCV0 = 0, 1)
-0.14
-0.12
-0.09
V
VOCC = 0.14V (OCCV1, OCCV0 = 1, 0)
-0.16
-0.14
-0.11
V
VOCC = 0.16V (OCCV1, OCCV0 = 1, 1)
-0.18
-0.16
-0.13
V
VOC = 0.20V (SCDV1, SCDV0 = 0, 0)
0.15
0.20
0.25
V
VOC = 0.35V (SCDV1, SCDV0 = 0, 1)
0.30
0.35
0.40
V
VOC = 0.65V (SCDV1, SCDV0 = 1, 0)
0.60
0.65
0.70
V
VOC = 1.20V (SCDV1, SCDV0 = 1, 1)
1.10
1.20
1.30
V
LDMONEN bit = “1”
1.1
1.45
1.8
V
VVMONH LDMONEN bit = “1”
Load Monitor Current
IVMON
Short Circuit Time-out
tSCD
Over Discharge Current Time-out
(Default in Boldface)
tOCD
Over Charge Current Time-out
(Default in Boldface)
tOCC
7
0.25
mV
20
40
60
µA
Internal short circuit detection delay
(SCLONG bit = ‘0’)
90
190
290
µs
Internal short circuit detection delay
(SCLONG bit = ‘1’)
5
10
15
ms
tOCD = 160ms (OCDT1, OCDT0 = 0, 0 and
DTDIV = 0)
80
160
240
ms
tOCD = 320ms (OCDT1, OCDT0 = 0, 1 and
DTDIV = 0)
160
320
480
ms
tOCD = 640ms (OCDT1, OCDT0 = 1, 0 and
DTDIV = 0)
320
640
960
ms
tOCD = 1280ms (OCDT1, OCDT0 = 1, 1 and
DTDIV = 0)
640
1280
1920
ms
tOCD = 2.5ms (OCDT1, OCDT0 = 0, 0 and
DTDIV = 1)
1.25
2.50
3.75
ms
tOCD = 5ms (OCDT1, OCDT0 = 0, 1 and
DTDIV = 1)
2.5
5
7.5
ms
tOCD = 10ms (OCDT1, OCDT0 = 1, 0 and
DTDIV = 1)
5
10
15
ms
tOCD = 20ms (OCDT1, OCDT0 = 1, 1 and
DTDIV = 1)
10
20
30
ms
tOCC = 80ms (OCCT1, OCCT0 = 0, 0 and
CTDIV = 0)
40
80
120
ms
tOCC = 160ms (OCCT1, OCCT0 = 0, 1 and
CTDIV = 0)
80
160
240
ms
tOCC = 320ms (OCCT1, OCCT0 = 1, 0 and
CTDIV = 0)
160
320
480
ms
tOCC = 640ms (OCCT1, OCCT0 = 1, 1 and
CTDIV = 0)
320
640
960
ms
tOCC = 2.5ms (OCCT1, OCCT0 = 0, 0 and
CTDIV = 1)
1.25
2.50
3.75
ms
tOCC = 5ms (OCCT1, OCCT0 = 0, 1 and
CTDIV = 1)
2.5
5
7.5
ms
tOCC = 10ms (OCCT1, OCCT0 = 1, 0 and
CTDIV = 1)
5
10
15
ms
tOCC = 20ms (OCCT1, OCCT0 = 1, 1 and
CTDIV = 1)
10
20
30
ms
FN6488.1
November 2, 2007
ISL9216, ISL9217
Operating Specifications All Specifications Apply to Both the ISL9216 and ISL9217 Separately Over the Recommended Operating
Conditions, Unless Otherwise Specified. (Continued)
DESCRIPTION
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OVER-TEMPERATURE PROTECTION SPECIFICATIONS
Internal Temperature Shutdown
Threshold
TINTSD
Internal Temperature Hysteresis
THYS
Internal Over-Temperature Turn-on Delay
Time
TITD
External Temperature Output Current
IXT
External Temperature Limit Threshold
TXTF
Temperature drop needed to restore
operation after an over-temperature
shutdown.
115
°C
105
°C
128
ms
Current output capability at TEMP3V pin
(ISL9216 only)
1.2
Voltage at VTEMPI (ISL9216 only);
-20
0
+20
mV
60
110
160
mV
Relative to:
V
TEMP3V
------------------------------
13
mA
. (Falling edge)
External Temperature Limit Hysteresis
TXTH
Voltage at VTEMPI (ISL9216 only).
External Temperature Monitor Delay
tXTD
Delay between activating the external
sensor and the internal over-temp
detection. (ISL9216 only)
1
ms
External Temperature Autoscan On Time
tXTAON
TEMP3V is ON (3.3V) (ISL9216 only)
5
ms
External Temperature Autoscan Off Time
tXTAOFF TEMP3V output is off. (ISL9216 only)
635
ms
ANALOG OUTPUT SPECIFICATIONS
Cell Monitor Analog Output Voltage
Accuracy
Cell Monitor Analog Output External
Temperature Accuracy
Internal Temperature Monitor Output
Voltage Slope
Internal Temperature Monitor Output
VAO6A
[VCELL1 - (VSS)]/2 - AO
[VCELLN - (VCELLN-1)]/2 - AO for N = 1 to 5.
(ISL9216 only)
-25
30
mV
VAO6B
VCELL6 - AO.
(ISL9216 only)
-42
58
mV
VAO7A
[VCELL1 - (VSS)]/2 - AO
[VCELLN - (VCELLN-1)]/2 - AO for N = 1 to 5.
(ISL9217 only)
-20
25
mV
VAO7B
[VCELLN - (VCELLN-1)]/2 - AO for N = 6 to 7.
(ISL9217 only)
-32
43
mV
VAOXT
External temperature monitoring accuracy.
Voltage error at AO when monitoring TEMPI
voltage (measured with TEMPI = 1V)
-10
10
mV
VINTMON Internal temperature monitor voltage
change
TINT25
Output at +25°C
tVSC
From SCL falling edge at data bit 0 of
command to AO output stable within 0.5%
of final value. AO voltage steps from 0V to
2V. (Note 6)
Cell Balance Transistor rDS(ON)
RCB
(Note 5)
Cell Balance Transistor Current
ICB
AO Output Stabilization Time
-3.5
mV/°C
1.31
V
0.1
ms
CELL BALANCE SPECIFICATIONS
8
Ω
5
200
mA
FN6488.1
November 2, 2007
ISL9216, ISL9217
Operating Specifications All Specifications Apply to Both the ISL9216 and ISL9217 Separately Over the Recommended Operating
Conditions, Unless Otherwise Specified. (Continued)
DESCRIPTION
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
3.5
5.0
6.5
V
WAKE-UP/SLEEP SPECIFICATIONS
Device WKUP Pin Voltage Threshold
(WKUP pin active HIGH rising edge)
Device WKUP Pin Hysteresis
(WKUP pin active HIGH)
VWKUP1 WKUP pin rising edge (WKPOL = 1)
Device wakes up and sets WKUP flag
HIGH. (ISL9216 only)
100
VWKUP1H WKUP pin falling edge hysteresis
(WKPOL = 1) sets WKUP flag LOW (does
not automatically enter sleep mode)
(ISL9216 only)
Internal Resistor on WKUP
RWKUP
Device WKUP Pin Voltage Threshold
(WKUP pin active LOW - Falling Edge)
VWKUP2 WKUP pin falling edge (WKPOL = 0)
Device wakes up and sets WKUP flag
HIGH.
Resistance from WKUP pin to VSS
(WKPOL = 1) (ISL9216 only)
130
Device Wake-up Delay
tWKUP
Delay after voltage on WKUP pin crosses
the threshold (rising or falling) before
activating the WKUP bit.
330
kΩ
VCELL1 - 2.6 VCELL1 - 2.0 VCELL1 - 1.2
V
200
mV
VWKUP2H WKUP pin rising edge hysteresis
(WKPOL = 0) sets WKUP flag LOW (does
not automatically enter sleep mode)
Device WKUP Pin Hysteresis
(WKUP pin active LOW)
230
mV
20
40
60
ms
FET CONTROL SPECIFICATIONS (For VCELL1, VCELL2, VCELL3 voltages from 2.8V to 4.3V - ISL9216 only)
Control Outputs Response Time
(CFET, DFET)
tCO
Bit 0 to start of control signal (DFET)
Bit 1 to start of control signal (CFET)
1.0
µs
CFET Gate Voltage
VCFET
No load on CFET
VCELL3 - 0.5
VCELL3
V
DFET Gate Voltage
VDFET
No load on DFET
VCELL3 - 0.5
VCELL3
V
FET Turn-on Current (DFET)
IDF(ON)
DFET voltage = 0 to VCELL3 - 1.5V
80
130
400
µA
FET Turn-on Current (CFET)
ICF(ON)
CFET voltage = 0 to VCELL3 - 1.5V
80
200
400
µA
100
180
FET Turn-off Current (DFET)
IDF(OFF) DFET voltage = VDFET to 1V
DFET Resistance to VSS
RDF(OFF) VDFET <1V (When turning off the FET)
mA
11
Ω
100
kHz
3.5
µs
SERIAL INTERFACE CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)
SCL Clock Frequency
fSCL
SCL Falling Edge to SDA Output Data
Valid
tAA
From SCL falling crossing VIH(min), until
SDA exits the VIL(max) to VIH(min) window.
tBUF
SDA crossing VIH(min) during a STOP
condition to SDA crossing VIH(min) during
the following START condition.
Clock LOW Time
tLOW
Measured at the VIL(max) crossing.
4.7
µs
Clock HIGH Time
tHIGH
Measured at the VIH(min) crossing.
4.0
µs
Time the Bus Must be Free Before Start of
New Transmission
4.7
µs
Start Condition Setup Time
tSU:STA
SCL rising edge to SDA falling edge. Both
crossing the VIH(min) level.
4.7
µs
Start Condition Hold Time
tHD:STA
From SDA falling edge crossing VIL(max) to
SCL falling edge crossing VIH(min).
4.0
µs
Input Data Setup Time
tSU:DAT
From SDA exiting the VIL(max) to VIH(min)
window to SCL rising edge crossing
VIL(min).
250
ns
Input Data Hold Time
tHD:DAT
From SCL rising edge crossing VIH(min) to
SDA entering the VIL(max) to VIH(min)
window.
300
ns
Stop Condition Setup Time
tSU:STO
From SCL rising edge crossing VIH(min) to
SDA rising edge crossing VIL(max).
4.0
µs
9
FN6488.1
November 2, 2007
ISL9216, ISL9217
Operating Specifications All Specifications Apply to Both the ISL9216 and ISL9217 Separately Over the Recommended Operating
Conditions, Unless Otherwise Specified. (Continued)
DESCRIPTION
SYMBOL
Stop Condition Hold Time
TEST CONDITIONS
tHD:STO From SDA rising edge to SCL falling edge.
Both crossing VIH(min).
Data Output Hold Time
tDH
From SCL falling edge crossing VIL(max)
until SDA enters the VIL(max) to VIH(min)
window. (Note 4)
MIN
TYP
MAX
UNIT
4.0
µs
0
ns
SDA and SCL Rise Time
tR
From VIL(max) to VIH(min).
1000
ns
SDA and SCL Fall Time
tF
From VIH(min) to VIL(max).
300
ns
Capacitive Loading of SDA or SCL
Cb
Total on-chip and off-chip
400
pF
SDA and SCL Bus Pull-up Resistor - Off
Chip
ROUT
Input Leakage Current (SCL, SDA, SDAI,
SDAO, SCLHV, SDAIHV, SDAOHV)
ILI
Maximum is determined by tR and tF.
For Cb = 400pF, max is about 2kΩ ~ 2.5kΩ
For Cb = 40pF, max is about 15kΩ to 20kΩ
1
kΩ
-10
10
µA
Input Buffer LOW Voltage (SCL, SDA,
SDAI)
VIL1
Voltage relative to VSS of the device.
-0.3
VRGO x 0.3
V
Input Buffer HIGH Voltage (SCL, SDA,
SDAI)
VIH1
Voltage relative to VSS of the device.
VRGO x 0.7
VRGO + 0.1V
V
Input LOW Voltage (SDAIHV)
VIL2
SDAIHV pulled up to HCI2C. (ISL9216 only) VCELL5 - 0.3
VVCELL5 +
[VHVI2C VVCELL5] x 0.3
V
Input HIGH Voltage (SDAIHV)
VIH2
SDAIHV pulled up to HCI2C. (ISL9216 only) VVCELL5 +
[VHVI2C VVCELL5] x
0.7
VHVI2C + 0.1V
V
Output Buffer LOW Voltage (SDA, SDAO)
VOL1
IOL = 1mA
(voltage relative to VSS of the device)
0.4
V
Output Buffer LOW Voltage (SDAOHV)
VOL2
IOL = 1mA
VVCELL5 + 0.5
V
SDA, SCL, SDAI Input Buffer Hysteresis
I2CHYST Sleep bit = 0
(Note 4)
V
0.05*VRGO
NOTES:
3. Power-up of the device requires all VCELL1, VCELL2, VCELL3, and VCC to be above the limits specified.
4. The device provides an internal hold time of at least 300ns for the SDA signal to bridge the unidentified region of the falling edge of SCL.
5. Limits established by characterization and are not production tested.
6. Maximum output capacitance = 15pF
10
FN6488.1
November 2, 2007
ISL9216, ISL9217
Wake-up Timing (WKPOL = 0)
<tWKUP
VWKUP2H
VWKUP2
<tWKUP
WKUP PIN
tWKUP
tWKUP
WKUP BIT
Wake-up Timing (WKPOL = 1)
<tWKUP
VWKUP1
VWKUP1H
WKUP PIN
<tWKUP
tWKUP
tWKUP
WKUP BIT
Change in Voltage Source, FET Control
SCL
BIT
3
SDA
BIT
2
BIT
1
BIT
0
BIT
1
BIT
0
DATA
AO
tVSC
tCO
tCO
tVSC
tCO
DFET (ISL9216 ONLY)
CFET (ISL9216 ONLY)
11
FN6488.1
November 2, 2007
ISL9216, ISL9217
Automatic Temperature Scan (ISL9216 only)
AUTO TEMP CONTROL
(INTERNAL ACTIVATION)
635ms
MONITOR TIME = 5ms
3.3V
HIGH IMPEDANCE
TEMP3V PIN
EXTERNAL
TEMPERATURE
OVER-TEMPERATURE
THRESHOLD
TMP3V/13
DELAY TIME = 1ms
DELAY TIME = 1ms
MONITOR TEMP DURING THIS
TIME PERIOD
XOT BIT
FET SHUTDOWN AND CELL BALANCE TURN-OFF
(IF ENABLED)
Discharge Overcurrent/Short Circuit Monitor (ISL9216 only) (Assumes DENOCD and DENSCD bits are ‘0’)
VSC
VOCD
VDSENSE
tSCD
‘1’
‘0’
DOC BIT
tSCD
tOCD
‘1’
‘0’
DSC BIT
3.3V
TEMP3V
OUTPUT
REGISTER 1 READ
REGISTER 1 READ
12V
DFET
OUTPUT
µC TURNS ON DFET
12
FN6488.1
November 2, 2007
ISL9216, ISL9217
Charge Overcurrent Monitor (ISL9216 only) (Assumes DENOCC bit is ‘0’)
VCSENSE
VOCC
tOCC
‘1’
‘0’
COC BIT
3.3V
TEMP3V
OUTPUT
REGISTER 1 READ
12V
CFET
OUTPUT
µC TURNS ON CFET
Serial Interface Timing Diagrams
Bus Timing
tF
tHIGH
tLOW
tR
SCL
tSU:STA
tSU:DAT
tHD:DAT
tSU:STO
tHD:STA
SDA INPUT
tAA
tDH
tBUF
SDA OUTPUT
This timing shows the communication with the ISL9216. Communication with the ISL9217 (through the ISL9216) adds some lag time, however,
overall the communication with the ISL9217 meets the same timing requirements as communication with the ISL9216.
Symbol Table
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
13
FN6488.1
November 2, 2007
ISL9216, ISL9217
Registers
TABLE 1. REGISTERS
ADDR
REGISTER
READ/WRITE
7
6
5
4
3
2
1
0
00H
Configuration
Status
Read only
CU
Cascade U
CL
Cascade L
Reserved
WKUP
WKUP pin
Status
Reserved
Reserved
Reserved
Reserved
01H
Operating Status
(Note 9)
Read only
Reserved
Reserved
XOT
Ext over
temp
IOT
Int over
Temp
LDFAIL
Load Fail
(VMON)
DSC
Short
Circuit
02H
Cell Balance
Read/Write
CB7ON
CB6ON/
WKUPR
CB5ON
CB4ON
CB3ON
CB2ON
DOC
COC
Discharge Charge OC
OC
CB1ON
Reserved
AO1
AO0
Cell balance FET control bits (plus WKUP of ISL9217 in cascade)
03H
Analog Out
Read/Write
UFLG1
UFLG0
User Flag 1 User Flag 0
Reserved
Reserved
AO3
AO2
Analog output select bits
04H
FET Control
Read/Write
SLEEP
Force
Sleep
(Note 10)
LDMONEN
Turn on
VMON
connection
Reserved
Reserved
Reserved
Reserved
CFET
Turn on
Charge
FET
(Note 11)
DFET
Turn on
Disharge
FET
(Note 11)
05H
Discharge Set
Read/Write
(Write only if
DISSETEN bit
set)
DENOCD
OCDV1
OCDV0
DENSCD
SCDV1
SCDV0
OCDT1
OCDT0
06H
Charge Set
Read/Write
(Write only if
CHSETEN bit
set)
Turn off
automatic
OCD
control
DENOCC
Turn off
automatic
OCC
control
Configure Overcurrent
Discharge Threshold
OCCV1
OCCV0
Configure Overcurrent
Charge Threshold
07H
Feature Set
Read/Write
(Write only if
FSETEN bit
set)
TMP3ON
DIS3
ATMPOFF
Turn off Disable 3.3V Temp 3.3V
keep on
automatic reg. (device
requires
external
external
temp scan
3.3V)
08H
Write Enable
Read/Write
FSETEN
Enable
Feature
Set writes
09H:
FFH
Reserved
NA
Turn off
Configure Short Circuit
automatic
Discharge Threshold
SCD control
Configure Overcurrent
Discharge Time-out
SCLONG
Long Shortcircuit delay
CTDIV
Divide
charge
time by 32
DTDIV
Divide
discharge
time by 64
DISXTSD
Disable
external
thermal
shutdown
DISITSD
Disable
internal
thermal
shutdown
POR
DISWKUP
Force POR Disable
WKUP pin
UFLG3
UFLG2
Reserved
CHSETEN DISSETEN
User Flag 3 User Flag 2
Enable
Enable
Charge Set Discharge
writes
Set writes
OCCT1
OCCT0
Configure Overcurrent
Charge Time-out
Reserved
WKPOL
Wake-up
Polarity
Reserved
RESERVED
NOTES:
7. A “1” written to a control or configuration bit causes the action to be taken. A “1” read from a status bit indicates that the condition exists.
8. “Reserved” indicates that the bit or register is reserved for future expansion. When writing to addresses 2, 3, 4, 6, 7, and 8: write a reserved bit
with the value “0”. Do not write to reserved registers at addresses 09H through FFH. Ignore reserved bits that are returned in a read operation.
9. These status bits are automatically cleared when the register is read. All other status bits are cleared when the condition is cleared.
10. This SLEEP bit is cleared on initial power-up, by the WKUP pin going high (when WKPOL = ”1”) or by the WKUP pin going low (when
WKPOL = ”0”), and by writing a “0” to the location with an I2C command.
11. When the automatic responses are enabled, these bits are automatically reset by hardware when an overcurrent or short circuit condition turns
off the FETs. At all other times, an I2C write operation controls the output to the respective FET and a read returns the current state of the FET
drive output circuit (though not the actual voltage at the output pin).
12. The shaded registers are not used in the ISL9217 device. Shaded status registers return ‘0’ when read. Shaded “read/write” registers can be read
and written, but they provide no functionality. When writing to the shaded areas in the ISL9217, the locations must be written as “0”.
14
FN6488.1
November 2, 2007
ISL9216, ISL9217
Status Registers
TABLE 2. CONFIGURATION STATUS REGISTER (ADDR: 00H)
BIT
FUNCTION
DESCRIPTION
7
CU
Cascade U
Indicates the device is an ISL9217. This bit is set in hardware and cannot be changed.
6
CL
Cascade L
Indicates the device is an ISL9216. This bit is set in hardware and cannot be changed.
5
SA
Reserved for ISL9208 devices.
4
WKUP
This bit is set and reset by hardware.
Wake-up Pin Status When ‘WKPOL’ is HIGH,
’WKUP’ HIGH = WKUP pin > Threshold voltage
‘WKUP’ LOW = WKUP pin < Threshold voltage
When ‘WKPOL’ is LOW
’WKUP’ HIGH = WKUP pin < Threshold voltage
‘WKUP’ LOW = WKUP pin > Threshold voltage
3
RESERVED
Reserved for future expansion.
2
RESERVED
Reserved for future expansion.
1
RESERVED
Reserved for future expansion.
0
RESERVED
Reserved for future expansion.
TABLE 3. OPERATING STATUS REGISTER (ADDR: 01H)
BIT
FUNCTION
DESCRIPTION
7
RESERVED
Reserved for future expansion.
6
RESERVED
Reserved for future expansion.
5
XOT
Ext Over-temp
(ISL9216 only)
This bit is set to “1” when the external thermistor indicates an over-temperature condition. If the temperature condition
has cleared, this bit is reset when the register is read.
4
IOT
Int Over-temp
This bit is set to “1” when the internal thermistor indicates an over-temperature condition. If the temperature condition
has cleared, this bit is reset when the register is read.
3
LDFAIL
Load Fail (VMON)
(ISL9216 only)
When the function is enabled, this bit is set to “1” by hardware when a discharge overcurrent or short circuit condition
occurs and the load remains heavy. When the load fail condition is cleared or under a light load, the bit is reset when the
register is read.
2
DSC
Short Circuit
(ISL9216 only)
This bit is set by hardware when a short circuit condition occurs during discharge. When the discharge short circuit
condition is removed, the bit is reset when the register is read.
1
DOC
Discharge OC
(ISL9216 only)
This bit is set by hardware when an overcurrent condition occurs during discharge. When the discharge overcurrent
condition is removed, the bit is reset when the register is read.
0
COC
Charge OC
(ISL9216 only)
This bit is set by hardware when an overcurrent condition occurs during charge. When the charge overcurrent condition
is removed, the bit is reset when the register is read.
15
FN6488.1
November 2, 2007
ISL9216, ISL9217
Control Registers
TABLE 4. CELL BALANCE CONTROL REGISTER (ADDR: 02H)
CONTROL REGISTER BITS
BIT 7
CB7ON
BIT 6
CB6ON
WKUPR
BIT 5
CB5ON
BIT 4
CB4ON
BIT 3
CB3ON
BIT 2
CB2ON
BIT 1
CB1ON
x
x
x
x
x
x
1
Cell1 ON
x
x
x
x
x
x
0
Cell1 OFF
x
x
x
x
x
1
x
Cell2 ON
x
x
x
x
x
0
x
Cell2 OFF
x
x
x
x
1
x
x
Cell3 ON
x
x
x
x
0
x
x
Cell3 OFF
x
x
x
1
x
x
x
Cell4 ON
x
x
x
0
x
x
x
Cell4 OFF
x
x
1
x
x
x
x
Cell5 ON
x
x
0
x
x
x
x
Cell5 OFF
x
1
x
x
x
x
x
Cell6 ON/WKUPR On (Note 13)
x
0
x
x
x
x
x
Cell6 OFF/WKUPR OFF (Note 13)
1
x
x
x
x
x
x
Cell7 ON (ISL9217 only)
0
x
x
x
x
x
x
Cell7 OFF (ISL9217 only)
Bit 0
RESERVED
BALANCE
Reserved for future expansion
NOTE:
13. WKUPR Pin refers to the ISL9216
16
FN6488.1
November 2, 2007
ISL9216, ISL9217
TABLE 5. ANALOG OUT CONTROL REGISTER (ADDR: 03H)
BITS
FUNCTION
DESCRIPTION
7
UFLG1
User Flag 1
General purpose flag usable by microcontroller software. This bit is battery backed up, even when RGO turns off.
6
UFLG0
User Flag 0
General purpose flag usable by microcontroller software. This bit is battery backed up, even when RGO turns off.
5:4
RESERVED
Reserved for future expansion
BIT 3
AO3
BIT 2
AO2
BIT 1
AO1
BIT 0
AO0
0
0
0
0
No Output (low power state)
0
0
0
1
VCELL1
0
0
1
0
VCELL2
0
0
1
1
VCELL3
0
1
0
0
VCELL4
0
1
0
1
VCELL5
0
1
1
0
VCELL6
0
1
1
1
VCELL7
1
0
0
0
External Temperature
1
0
0
1
Internal Temperature
1
x
1
x
Reserved
1
1
x
x
Reserved
OUTPUT VOLTAGE
TABLE 6. FET CONTROL REGISTER (ADDR: 04H)
BIT
FUNCTION
DESCRIPTION
7
SLEEP
Force Sleep
Setting this bit to “1” forces the device to go into a sleep condition. This turns off both FET outputs, the cell balance
outputs and the voltage regulator. This also resets the CFET, DFET, and CB7ON:CB1ON bits. The SLEEP bit is
automatically reset to “0” when the device wakes up. This does not reset the AO3:AO0 bits.
6
LDMONEN
Turn on VMON
connection
(ISL9216 only)
Writing a “1” to this bit turns on the VMON circuit. Writing a “0” to this bit turns off the VMON circuit. As such, the
microcontroller has full control of the operation of this circuit.
RESERVED
Reserved for future expansion.
1
CFET
(ISL9216 only)
Setting this bit to “1” turns on the charge FET.
Setting this bit to “0” turns off the charge FET.
This bit is automatically reset in the event of a charge overcurrent condition, unless the automatic response is disabled
by the DENOCC bit.
0
DFET
(ISL9216 only)
Setting this bit to “1” turns on the discharge FET.
Setting this bit to “0” turns off the discharge FET.
This bit is automatically reset in the event of a discharge overcurrent or discharge short circuit condition, unless the
automatic response is disabled by the DENOCD or DENSCD bits.
5:2
17
FN6488.1
November 2, 2007
ISL9216, ISL9217
Configuration Registers
The device is configured for specific application requirements using the Configuration Registers. The configuration register
consists of SRAM memory. This memory is powered by the RGO output. In a sleep condition, an internal switch powers the
contents of these registers from the VCELL1 input.
TABLE 7. DISCHARGE SET CONFIGURATION REGISTER (ADDR: 05H)
SETTING
FUNCTION
DENOCD
Turn off automatic OCD control
(ISL9216 only)
When set to ‘0’, a discharge overcurrent condition automatically turns off the FETs.
When set to ‘1’, a discharge overcurrent condition will not automatically turn off the FETs.
In either case, this condition sets the DOC bit, which also turns on the TEMP3V output.
Bit 5
OCDV0
Discharge Overcurrent Threshold
(ISL9216 only)
0
0
VOCD = 0.10V
0
1
VOCD = 0.12V
1
0
VOCD = 0.14V
1
1
VOCD = 0.16V
DENSCD
Turn off automatic SCD control
(ISL9216 only)
When set to ‘0’, a discharge short circuit condition turns off the FETs.
When set to ‘1’, a discharge short circuit condition will not automatically turn off the FETs.
In either case, the condition sets the SCD bit, which also turns on the TEMP3V output.
Bit 2
SCDV0
Discharge Short Circuit Threshold
(ISL9216 only)
0
0
VSCD = 0.20V
0
1
VSCD = 0.35V
1
0
VSCD = 0.65V
1
1
VSCD = 1.20V
Bit 0
OCDT0
Discharge Overcurrent Time-out
(ISL9216 only)
0
0
tOCD = 160ms (2.5ms if DTDIV = 1)
0
1
tOCD = 320ms (5ms if DTDIV = 1)
1
0
tOCD = 640ms (8ms if DTDIV = 1)
1
1
tOCD = 1280ms (16ms if DTDIV = 1)
Bit 7
Bit 6
OCDV1
Bit 4
Bit 3
SCDV1
Bit 1
OCDT1
18
FN6488.1
November 2, 2007
ISL9216, ISL9217
TABLE 8. CHARGE/TIME SCALE CONFIGURATION REGISTER (ADDR: 06H)
SETTING
FUNCTION
DENOCC
Turn off automatic OCC control
(ISL9216 only)
When set to ‘0’, a charge overcurrent condition automatically turns off the FETs.
When set to ‘1’, a charge overcurrent condition will not automatically turn off the FETs.
In either case, this condition sets the COC bit, which also turns on the TEMP3V output.
Bit 5
OCCV0
Charge Overcurrent Threshold
(ISL9216 only)
0
0
VOCD = 0.10V
0
1
VOCD = 0.12V
1
0
VOCD = 0.14V
1
1
VOCD = 0.16V
Bit 4
SCLONG
Short circuit long delay
(ISL9216 only)
When this bit is set to ‘0’, a short circuit needs to be in effect for 100µs before a shutdown
begins. When this bit is set to ‘1’. a short circuit needs to be in effect for 10ms before a
shutdown begins.
Bit 3
CTDIV
Divide charge time by 32
(ISL9216 only)
When set to “1”, the charge overcurrent delay time is divided by 32.
Bit 2
DTDIV
Divide discharge time by 64
(ISL9216 only)
When set to “1”, the discharge overcurrent delay time is divided by 64.
Bit 0
OCCT0
Charge Overcurrent Time-out
(ISL9216 only)
0
0
tOCC = 80ms (2.5ms if CTDIV=1)
0
1
tOCC = 160ms (4ms if CTDIV=1)
1
0
tOCC = 320ms (8ms if CTDIV=1)
1
1
tOCC = 640ms (16ms if CTDIV=1)
Bit 7
Bit 6
OCCV1
Bit 1
OCCT1
TABLE 9. FEATURE SET CONFIGURATION REGISTER (ADDR: 07H)
BIT
FUNCTION
DESCRIPTION
7
ATMPOFF
Turn off automatic external temp scan
(ISL9216 only)
When set to ‘1’ this bit disables the automatic temperature scan. When set to ‘0’, the temperature
is turned on for 5ms in every 640ms.
6
DIS3
Disable 3.3V reg
Setting this bit to “1” disables the internal 3.3V regulator. Setting this bit to “1” requires that there
be an external 3.3V regulator connected to the RGO pin.
5
TMP3ON
Temp 3.3V keep on
Setting this bit to “1” keeps ON the 3.3V output to the external temperature sensor.
4
DISXTSD
Disable external thermal shutdown
(ISL9216 only)
Setting this bit to “1” disables the automatic shutdown of the cell balance and power FETs in
response to an out of limit external temperature. While the automatic response is disabled, the
microcontroller can initiate a shutdown based on the XOT flag.
3
DISITSD
Disable internal thermal shutdown
Setting this bit to “1” disables the automatic shutdown of the cell balance and power FETs in
response to an out of limit internal temperature. While the automatic response is disabled, the
microcontroller can initiate a shutdown based on the IOT flag.
2
POR
Force POR
Setting this bit to “1” forces a POR condition. This resets all internal registers to zero.
1
DISWKUP
Disable WKUP pin
Setting this bit to “1” disables the WKUP pin function.
CAUTION: Setting this pin to ‘1’ prevents a wake-up condition. If the device then goes to sleep, it
cannot be waken without a communication link that resets this bit, or by power cycling the device.
0
WKPOL
Wake-up Polarity
Setting this bit to “1” sets the device to wake-up on a rising edge at the WKUP pin.
Setting this bit to “0” sets the device to wake-up on a falling edge at the WKUP pin.
CAUTION: Setting this pin to ‘1’ in the ISL9217 prevents a wake-up condition. If the device then
goes to sleep, it cannot be waken without power cycling the device.
19
FN6488.1
November 2, 2007
ISL9216, ISL9217
.
TABLE 10. WRITE ENABLE REGISTER (ADDR: 08H)
BIT
FUNCTION
DESCRIPTION
7
FSETEN
Enable discharge set writes
When set to “1”, allows writes to the Feature Set register. When set to “0”, prevents writes to the
Feature Set register (Addr: 07H). Default on initial power-up is “0”.
6
CHSETEN
Enable charge set writes
(ISL9216 only)
When set to “1”, allows writes to the Charge Set register. When set to “0”, prevents writes to the
Feature Set register (Addr: 06H). Default on initial power-up is “0”.
5
DISSETEN
Enable discharge set writes
(ISL9216 only)
When set to “1”, allows writes to the Discharge Set register (Addr: 05H). When set to “0”, prevents
writes to the Feature Set register. Default on initial power-up is “0”.
4
UFLG3
User Flag 3
General purpose flag usable by microcontroller software. This bit is battery backed up, even when
RGO turns off.
3
UFLG2
User Flag 3
General purpose flag usable by microcontroller software. This bit is battery backed up, even when
RGO turns off.
2
RESERVED
Reserved for future expansion.
1
RESERVED
Reserved for future expansion.
0
RESERVED
Reserved for future expansion.
12 CELLS
VCELL7
11 CELLS
VCELL7
10 CELLS
VCELL7
9 CELLS
VCELL7
8 CELLS
VCELL7
CB7
VCELL6
CB7
VCELL6
CB7
VCELL6
CB7
VCELL6
CB7
VCELL6
CB6
VCELL5
CB6
VCELL5
CB6
VCELL5
CB6
VCELL5
CB6
VCELL5
CB5
VCELL4
CB5
VCELL4
CB5
VCELL4
CB5
VCELL4
CB5
VCELL4
CB4
VCELL3
CB4
VCELL3
CB4
VCELL3
CB4
VCELL3
CB4
VCELL3
CB3
VCELL2
CB3
VCELL2
CB3
VCELL2
CB3
VCELL2
CB3
VCELL2
CB2
VCELL1
CB2
VCELL1
CB2
VCELL1
CB2
VCELL1
CB2
VCELL1
CB1
VSS
CB1
VSS
CB1
VSS
CB1
VSS
CB1
VSS AO
AO
AO
AO
AO
VCELL7
VCELL7
VCELL7
VCELL7
VCELL7
VCELL6
VCELL6
VCELL6
VCELL6
VCELL6
VCELL5
VCELL5
VCELL5
VCELL5
VCELL5
CB5
VCELL4
CB5
VCELL4
CB5
VCELL4
CB5
VCELL4
CB5
VCELL4
CB4
VCELL3
CB4
VCELL3
CB4
VCELL3
CB4
VCELL3
CB4
VCELL3
CB3
VCELL2
CB3
VCELL2
CB3
VCELL2
CB3
VCELL2
CB3
VCELL2
CB2
VCELL1
CB2
VCELL1
CB2
VCELL1
CB2
VCELL1
CB2
VCELL1
CB1
VSS
CB1
VSS
CB1
VSS
CB1
VSS
CB1
VSS
NOTE: MULTIPLE CELLS CAN BE CONNECTED IN PARALLEL
FIGURE 1. BATTERY CONNECTION OPTIONS
20
FN6488.1
November 2, 2007
ISL9216, ISL9217
Device Description
Design Theory
Instructed by the microcontroller, the ISL9216 and ISL9217
chip set performs cell voltage monitoring and cell balancing
operations. The ISL9216 has automatic overcurrent and
short circuit monitoring, and shut-down with built-in
selectable time delays. The ISL9216 also provides automatic
turn off of the power FETs and cell balancing FETs in an
over-temperature condition. All automatic functions of the
ISL9216 can be turned off and the microcontroller can
manage the operations through software.
Battery Connection
WKUPR pin of the ISL9216 connects to the ISL9217 WKUP
pin. When the ISL9216 WKUPR bit is set to “1”, the ISL9217
WKUP pin pulls low and the ISL9217 wakes up. Because of
this operation, it is important that the WKPOL bit of the
ISL9217 remain in the default state (ISL9217 WKPOL = 0).
Protection Functions
In the default, recommended condition, the ISL9216
automatically responds to discharge overcurrent, discharge
short circuit, charge overcurrent, internal over-temperature,
and external over-temperature. The designer can set
optional over-ride conditions that allow the response to be
dictated by the microcontroller. These are discussed in the
following section.
The ISL9216 and ISL9217 support packs of 8 to 12 series
connected Li-ion cells. Connection guidelines for each cell
combination are shown in Figure 1.
500
VCC
500
System Power-Up/Power-Down
RGC
The ISL9216 and ISL9217 power-up when the voltages on
their VCELL1, VCELL2, VCELL3, and VCC pins all exceed
their POR threshold. At this time, the devices each wake-up
and turn on their RGO output.
RGO
VSS
The regulator circuit provides 3.3VDC at pin RGO. It does
this by using a control voltage on the RGC pin to drive an
external NPN transistor (See Figure 2). For the ISL9216, the
transistor should have a beta of at least 70 to provide ample
current to the device and external circuits and should have a
VCE of greater than 60V (preferably higher) for a 12 cell
pack. For the ISL9217, the transistor selection is not as
critical because it will likely not drive any external circuits,
however, it should be rated with a VCE greater than 50V.
The voltage at the emitter of the NPN transistor is monitored
and regulated to 3.3V by the control signal RGC. RGO also
powers most of the ISL9216 and ISL9217 internal circuits. A
500Ω resistor is recommended in the collector of each NPN
transistor to minimize initial current surge when the regulator
turns on.
VCC
RGC
3.3V
RGO
VSS
GND
FIGURE 2. VOLTAGE REGULATOR CIRCUITS
ISL9216
WKUP
Once powered up, the devices remain in a wake-up state
until put to sleep by the microcontroller (typically when the
cells drop too low in voltage) or until the VCELL1, VCELL2,
VCELL3, or VCC voltages drop below their POR threshold.
WKUP
(STATUS)
WKUP Pin Operation
There are two ways to design a wake-up of the ISL9216. In
an active LOW connection (WKPOL = ’0’ - default), the
device wakes up when a charger is connected to the pack.
This pulls the WKUP pin low when compared to a reference
based on the VCELL1 voltage. In an active HIGH connection
(WKPOL = ‘1’) the device wakes up when then WKUP pin is
pulled high by a connection through an external switch. See
Figure 3.
Once the ISL9216 wakes up, the RGO powers up the
microcontroller. The microcontroller then wakes up the
ISL9217 by setting the WKUPR bit in the ISL9216. The
21
5V
330k*
WAKE-UP
CIRCUITS
WKPOL
(CONTROL)
VSS
* INTERNAL RESISTOR
ONLY CONNECTED WHEN
WKPOL = 1.
FIGURE 3. WAKE-UP CONTROL CIRCUITS
FN6488.1
November 2, 2007
ISL9216, ISL9217
OVERCURRENT SAFETY FUNCTIONS
The ISL9216 continually monitors the discharge current by
monitoring the voltage at the CSENSE and DSENSE pins. If
that voltage exceeds a selected value for a time exceeding a
selected delay, then the device enters an overcurrent or short
circuit protection mode. In these modes, the ISL9216
automatically turns off both power FETs and hence prevents
current from flowing through the terminals P+ and P-.
The voltage thresholds and the response times of the
overcurrent protection circuits are selectable for discharge
overcurrent, charge overcurrent, and discharge short circuit
conditions. The specific settings are determined by bits in
the “DISCHARGE SET CONFIGURATION REGISTER
(ADDR: 05H)” on page 18, and “CHARGE/TIME SCALE
CONFIGURATION REGISTER (ADDR: 06H)” on page 19.
(See also “REGISTERS” on page 14).
In an overcurrent condition, the ISL9216 automatically turns off
the voltage on CFET and DFET pins. The DFET output drives
the discharge FET gate low, turning off the FET quickly. The
CFET output turns off and allows the gate of the charge FET to
be pulled low through a resistor.
By turning off the FETs the ISL9216 prevents damage to the
battery pack caused by excessive current into or out of the cells
(as in the case of a faulty charger or short circuit condition).
When the ISL9216 detects a discharge overcurrent condition,
the ISL9216 turns off both power FETs and sets the DOC bit.
(When the FETs are turned off, the DFET and CFET bits are
also reset). The automatic response to overcurrent during
discharge is prevented by setting the DENOCD bit to “1”. The
external microcontroller can turn on the FETs at any time to
recover from this condition, but it would usually turn on the load
monitor function (by setting the LDMONEN bit) and monitor the
LDFAIL bit to detect that the overcurrent condition has been
removed.
When the ISL9216 detects a discharge short circuit condition,
both power FETs are turned off and DSC bit is set. (When the
FETs are turned off, the DFET and CFET bits are also reset).
The automatic response to short circuit during discharge is
prevented by setting the DENSCD bit to “1”. The external
microcontroller can turn on the FETs at any time to recover from
this condition, but it would usually turn on the load monitor
function (by setting the LDMONEN bit) and monitor the LDFAIL
bit to detect that the overcurrent condition has been removed.
When the ISL9216 detects a charge overcurrent condition, both
power FETs are turned off and COC bit is set. (When the FETs
are turned off, the DFET and CFET bits are also reset). The
automatic response to overcurrent during discharge is
prevented by setting the DENOCC bit to “1”. The external
microcontroller can turn on the FETs at any time to recover from
this condition, but it would usually wait to do this until the cell
voltages are not over charged and that the overcurrent
condition has been removed. Or, the microcontroller could wait
22
until the pack is removed from the charger and then reattached.
An alternative method of providing the protection function, if
desired by the designer, is to turn off the automatic safety
response. In this case, the ISL9216 device still monitors the
conditions and sets the status bits, but takes no action in
overcurrent or short circuit conditions. Safety of the pack
depends, instead, on the microcontroller to send commands to
the ISL9216 to turn off the FETs.
To facilitate a microcontroller response to an overcurrent
condition, especially if the microcontroller is in a low power
state, a charge overcurrent flag (COC), a discharge overcurrent
flag (DOC), or the short circuit flag (DSC) being set causes the
ISL9216 TEMP3V output to turn on and pull high. (See
Figure 5). This output can be used as an external interrupt by
the microcontroller to wake-up quickly to handle the overcurrent
condition.
LOAD MONITORING
The load monitor function in the ISL9216 (see Figure 4) is used
primarily to detect that the load has been removed following an
overcurrent or short circuit condition during discharge. This can
be used in a control algorithm to prevent the FETs from turning
on while the overload or short circuit condition remains.
The load monitor can also be used by the microcontroller
algorithms after an undervoltage condition on any cells
causes the FETs to turn off. Use of the load monitor prevents
the FETs from turning on while the load is still present. This
minimizes the possible “oscillations” that can occur when a
load is applied in a low capacity pack. It can also be part of a
system protection mechanism to prevent the load from
turning on automatically - i.e. some action must be taken
before the pack is again turned on.
P+
VSS
RL
OPEN
P-
DFET
R1
ISL9216
VMON
VREF
36V
LDFAIL
=1 if VMON > VVMONH
=0 if VMON ≤ VVMONL
LDMONEN
VSS
FIGURE 4. LOAD MONITOR CIRCUIT
FN6488.1
November 2, 2007
ISL9216, ISL9217
The load monitor circuit can be turned on or off by the
microcontroller. It is normally turned off to minimize current
consumption. It must be activated by the external
microcontroller for it to operate. The circuit works by
internally connecting the VMON pin to VSS through a
resistor. The circuit operates as shown in Figure 4.
In a typical pack operation, when an overcurrent or short
circuit event happens, the DFET turns off, opening the
battery circuit to the load. At this time, the RL is small and
the load monitor is initially off. In this condition, the voltage at
VMON could rise to nearly the pack voltage. However, since
in most configurations, this voltage would exceed the
maximum limits on the VMON pin, a series zener diode is
required.
Once the power FETs turn off, the microcontroller activates
the load monitor by setting the LDMONEN bit. This turns on
an internal FET that adds a pull-down resistor to the load
monitor circuit. While still in the overload condition the
combination of the load resistor, an external adjustment
resistor (R1), the zener diode, and the internal load monitor
resistor form a voltage divider. R1 is chosen so that when the
load is released to a sufficient level, the LDFAIL condition is
reset.
Because of the manual scan of the temperature, it may be
desired to turn off the automatic scan, although they can be
used at the same time without interference. To turn off the
automatic scan, set the ATMPOFF bit.
The microcontroller can over-ride both the automatic
temperature scan and the microcontroller controlled
temperature scan by setting the TEMP3ON configuration bit.
This turns on the TEMP3V output to keep the temperature
control voltage on all the time, for a continuous monitoring of
an over-temperature condition. This likely will consume a
significant amount of current, so this feature is usually used
for special or test purposes.
Protection
As a default, when the ISL9216 detects an internal or
external over-temperature condition, the FETs are turned off,
the cell balancing function is disabled, and the IOT bit or
XOT bit (respectively) is set.
Turning off the FETs in the event of an over-temperature
condition prevents continued discharge or charge of the cells
when they are over heated. Turning off the cell balancing in
the event of an over-temperature condition prevents damage
to the IC in the event too many cells are being balanced,
causing too much power dissipation in the ISL9216.
OVER-TEMPERATURE SAFETY FUNCTIONS
External Temperature Control
5ms
I2C
Without microcontroller intervention, the ISL9216
continuously turns on TEMP3V output (and the external
temperature monitor) for 5ms every 640ms. In this way, the
external temperature is monitored even if the microcontroller
is asleep. If the ATMPOFF bit is set, this automatic
temperature scan is turned off.
When the TEMP3V output turns on, the ISL9216 waits 1ms
for the temperature reading to stabilize, then compares the
external temperature voltage with an internal voltage divider
that is set to TEMP3V/13. When the thermistor voltage is
below the reference threshold after the delay, an external
temperature fail condition exists. To set the external overtemperature limit, set the value of RX resistor to the 12 times
the resistance of the thermistor at the over-temperature
threshold.
DECODE
The TEMP3V output pin also turns on when the
microcontroller sets the AO3:AO0 bits to select that the
external temperature voltage. This causes the TEMPI voltage
to be placed on AO and activates (after 1ms) the overtemperature detection. As long as the AO3:AO0 bits point to
the external temperature, the TEMP3V output remains on.
23
ATMPOFF
TMP3ON
CHARGE OC
DISCHARGE OC
DISCHARGE SC
OSC
OVERCURRENT
PROTECTION CIRCUITS
635ms
I2C
REGISTERS
RGO
AO3:AO0
TO
µC
EXT TEMP
VSS (ON)
AO
12R
TEMP3V
MUX
RX
TEMPI
1ms
DELAY
XOT
EXTERNAL
TEMP
MONITOR
R
The external temperature is monitored by using a voltage
divider consisting of a fixed resistor and a thermistor. This
divider is powered by the ISL9216 TEMP3V output. This
output is normally controlled so it is on for only short periods
to minimize current consumption.
ISL9216
VSS
TEMP FAIL
INDICATOR
FIGURE 5. EXTERNAL TEMPERATURE MONITORING AND
CONTROL (ISL9216 ONLY)
FN6488.1
November 2, 2007
ISL9216, ISL9217
In the event of an automatic over-temperature condition, cell
balancing is prevented and FETs are held off until the
temperature drops back below the temperature recovery
threshold. During this temperature shutdown period, the
microcontroller can monitor the internal temperature through
the analog output pin (AO), but any writes to the CFET bit,
DFET bit, or cell balancing bits are ignored
The automatic response to an internal over-temperature is
prevented by setting the DISITSD bit to “1”. The automatic
response to an external over-temperature is prevented by
setting the DISXTSD bit to “1”. In either case, it is important
for the microcontroller to monitor the internal and external
temperature to protect the pack and the electronics in an
over-temperature condition.
Cell Balancing
OVERVIEW
A typical ISL9216 and ISL9217 Li-ion battery pack consists
of 8 to 12 cells in series, with one or more cells in parallel.
This combination gives both the voltage and power
necessary for power tools, e-bikes, electric wheel chairs,
portable medical equipment, and battery powered industrial
applications. While the series/parallel combination of Li-ion
cells is common, the configuration is not as efficient as it
could be, because any capacity mismatch between seriesconnected cells reduces the overall pack capacity. This
mismatch is greater as the number of series cells and the
load current increase. Cell balancing techniques increase
the capacity and the operating time of Li-ion battery packs.
Analog Multiplexer Selection
ISL9217
The ISL9216 and ISL9217 devices can be used to externally
monitor individual battery cell voltages and temperatures.
Each quantity can be monitored at the analog output pin (AO)
and is selected using the I2C interface. See Figure 6.
I2C
LEVEL
SHIFT
VC7/VCC
LEVEL
SHIFT
VCELL6
REGS
To monitor the voltages on the ISL9217 inputs, set the
ISL9216 to monitor VCELL6, then set the ISL9217 to the
desired VCELL input. The ISL9216 and ISL9217 VCELL
input voltages are divided by 2, except for the ISL9216
VCELL6 input. This is a divide by 1 input. In this way, the
value read at the ISL9216 AO output is always a divide by 2
of the original cell voltage.
AO3:AO0
DECODE
AO
2
LEVEL
SHIFT
VCELL2
LEVEL
SHIFT
VCELL1
MUX
VSS
VOLTAGE MONITORING
Since the voltage on each of the Li-Ion Cells are normally
higher than the regulated supply voltage, it is necessary to
both level shift and divide the voltage. To get into the voltage
range required by the external A/D converter, the voltage
level shifter divides the cell voltage by 2. Therefore, a Li-Ion
cell with a voltage of 4.2V is reported via the AO pin to be
2.1V.
INT
TEMP
1
TEMPERATURE MONITORING
The voltage representing the external temperature applied at
the TEMPI terminal is directed to the AO terminal through a
MUX, as selected by the AO control bits (see Figures 5
and 6). The external temperature voltage is not divided by 2
as are the cell voltages. Instead it is a direct reflection of the
voltage at the TEMPI pin.
A similar operation occurs when monitoring the internal
temperature through the AO output, except there is no
external “calibration” of the voltage associated with the
internal temperature. For the internal temperature
monitoring, the voltage at the output is linear with respect to
temperature. (See “Operating Specifications” on page 6 for
information about the output voltage at +25°C and the output
slope relative to temperature).
I2C
SCL
SDA
VCC
ISL9216
LEVEL
SHIFT
LEVEL
SHIFT
VCELL6
LEVEL
SHIFT
VCELL5
LEVEL
SHIFT
VCELL4
LEVEL
SHIFT
VCELL1
REGS
AO3:AO0
DECODE
AO
2
VSS
MUX
1
EXT TEMP.
INT
TEMP
TEMPI
(ISL9216 ONLY)
FIGURE 6. ANALOG OUTPUT MONITORING DIAGRAM
24
FN6488.1
November 2, 2007
ISL9216, ISL9217
DEFINITION OF CELL BALANCING
Cell balancing is defined as the application of differential
currents to individual cells (or combinations of cells) in a
series string. Normally, of course, cells in a series string
receive identical currents. A battery pack requires additional
components and circuitry to achieve cell balancing. For the
ISL9216 and ISL9217 devices, the only external
components required are balancing resistors.
CELL BALANCE OPERATION
Cell balancing is accomplished through a microcontroller
algorithm. This algorithm compares the cell voltages (a
representation of the pack capacity) and turns on balancing
for the cells that have the higher voltages. There are many
parameters that should be considered when writing this
algorithm. An example cell balancing algorithm is available
in the ISL9216EVAL1Z evaluation kit.
See Diode D3 in Figure 8. This will reduce the CFET gate
voltage, but not significantly.
Finally, in all configurations, to protect the Charge FET itself
in the event of a large negative voltage on the Pack- pin,
zener diode D4 is added. The large negative voltage can
occur when the P- pin goes significantly negative, while the
CFET pin is being internally clamped at VSS. The zener
voltage of D4 should be less than the VGS(max)
specification of the FET.
VC7/VCC
ISL9216, ISL9217
21Ω
1W
CB7
MUST ASSUME ZERO rDS(ON)
FOR MAX CURRENT CALCULATION
200mA
7 6 5 4 3 2 1
The microcontroller turns on the specific cell balancing by
setting a bit in the Cell Balance Register. Each bit in the
register corresponds to one cell’s balancing control. When
the bit is set, an internal cell balancing FET turns on. This
shorts an external resistor across the specified cell. The
maximum current that can be drawn from (or bypassed
around) the cell is 200mA. This current is set by selecting
the value of the external resistor. Figure 7 shows an example
with a 200mA (maximum) balancing current.
With lower balancing current, more balancing FETs can be
turned on at once, without exceeding the device power
dissipation limits or generating excessive balancing current
that will heat the external resistor.
VCELL1
21Ω
1W
CB1
VSS
FIGURE 7. CELL BALANCING CONTROL EXAMPLE WITH
100mA BALANCING CURRENT
External VMON/CFET Protection Mechanisms
When there is a single charge/discharge path, a blocking
diode is required in the ISL9216 VMON to P- path. See D1 in
Figure 8. This diode is to protect against a negative voltage
on the VMON pin that can occur when the FETs are off and
the charger connects to the pack. This diode is not needed
when there is a separate charge and discharge path,
because the voltages on P- (discharge) are likely always
positive.
For the cascaded combination of ISL9216 and ISL9217, a
zener diode (D2 in Figure 8) needs to be in the ISL9216
VMON path to the P- pin to protect the ISL9216 from an
overvoltage condition when the FETs open due to a short
circuit or overcurrent condition.
With the single set of charge/discharge FETs, the ISL9216
CFET pin needs to be protected in the event of an overcurrent or short circuit shut-down. When this happens, the
FET opens suddenly. The flyback voltage from the motor
windings will likely exceed the maximum input voltage on the
CFET pin. So, when operating in this configuration, an
additional external series diode must be placed between the
CFET pin of the ISL9216 and the gate of the Charge FET.
25
CELL
BALANCE
REG
PACK+
ISL9217
PACKD1
D2
VMON
10M
ISL9216
D4
1M
D3
CFET
DFET
FIGURE 8. USE OF A DIODES FOR PROTECTING THE
CFET AND VMON PINS.
FN6488.1
November 2, 2007
ISL9216, ISL9217
User Flags
The ISL9216 and ISL9217 each contain four flags in the
register area that the microcontroller can use for general
purpose indicators. These bits are designated UFLG3, UFLG2,
UFLG1, and UFLG0. The microcontroller can set or reset these
bits by writing into the appropriate register.
The user flag bits are battery backed up, so the contents
remain even after a sleep mode. However, if the mirocontroller
sets the POR bit to force a power on reset, all of the user flags
will also be reset. In addition, if the voltage on cell1 ever drops
below the POR voltage, the contents of the user flags (as well
as all other register values) could be lost.
Serial Interface
INTERFACE CONVENTIONS
The device supports a bi-directional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter, and the receiving device as the
receiver. The device controlling the transfer is called the
master and the device being controlled is called the slave.
The master always initiates data transfers, and provides the
clock for both transmit and receive operations. Therefore,
the ISL9216 and ISL9217 devices operate as slaves in all
applications.
When sending or receiving data, the convention is the most
significant bit (MSB) is sent first. So, the first address bit sent
is bit 7.
CLOCK AND DATA
SCL
SDA
START
STOP
FIGURE 10. I2C START AND STOP BITS
ACKNOWLEDGE
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, releases the bus after transmitting 8-bits.
During the ninth clock cycle, the receiver pulls the SDA line
LOW to acknowledge that it received the 8-bits of data. See
Figure 11.
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM
TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
FIGURE 11. ACKNOWLEDGE RESPONSE FROM RECEIVER
Data states on the SDA line can change only while SCL is
LOW. SDA state changes during SCL HIGH are reserved for
indicating start and stop conditions. See Figure 9.
SCL
SDA
DATA
STABLE
condition is only issued after the transmitting device has
released the bus. See Figure 10.
DATA
CHANGE
DATA
STABLE
FIGURE 9. VALID DATA CHANGES ON I2C BUS
START CONDITION
All commands are preceded by the start condition, which is a
HIGH to LOW transition of SDA when SCL is HIGH. The
device continuously monitors the SDA and SCL lines for the
start condition and will not respond to any command until
this condition has been met. See Figure 10.
STOP CONDITION
All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA when SCL is
HIGH. The stop condition is also used to place the device
into the Standby power mode after a read sequence. A stop
26
The device responds with an acknowledge after recognition
of a start condition and the correct slave byte. If a write
operation is selected, the device responds with an
acknowledge after the receipt of each subsequent 8-bits.
The device acknowledges all incoming data and address
bytes, except for the slave byte when the contents do not
match the devices internal pattern.
In the read mode, the device transmits 8-bits of data,
releases the SDA line, then monitors the line for an
acknowledge. If an acknowledge is detected and no stop
condition is generated by the master, the device will
continues to transmit data. The device terminates further
data transmissions if an acknowledge is not detected. The
master must then issue a stop condition to return the device
to Standby mode and place the device into a known state.
WRITE OPERATIONS
For a write operation, the device requires a slave byte and an
address byte. The slave byte specifies which of the devices (in
a cascade configuration) the master is writing to. The address
specifies one of the registers in that device. After receipt of
each byte, the device responds with an acknowledge, and
awaits the next 8-bits from the master. After the acknowledge,
following the transfer of data, the master terminates the transfer
by generating a stop condition. See Figure 12.
FN6488.1
November 2, 2007
SIGNALS
FROM THE
MASTER
ISL9216, ISL9217
S
T
A
R
T
REGISTER
ADDRESS
S
T
O
P
DATA
ISL9216 SLAVE BYTE
0
1
0
1
0
0
0
X
ISL9217 SLAVE BYTE
0
1
0
1
0
0
1
X
FIGURE 14. DEVICE SLAVE BYTES
0 1 0 1 0 0 x 0
SIGNALS
FROM THE
SLAVE
SDA BUS
SLAVE
BYTE
A
C
K
A
C
K
A
C
K
ISL9216
ISL9217
HVI2C
RGO
ISL9216: x = 0 [SLAVE BYTE = 50H]
ISL9217: x = 1 [SLAVE BYTE = 52H]
SCL
LEVEL
SHIFT
FIGURE 12. WRITE SEQUENCE
1010 000x
When receiving data from the master, the value in the data
byte is transferred into the register specified by the address
byte on the falling edge of the clock following the 8th data bit.
After receiving the acknowledge after the data byte, the device
automatically increments the address. So, before sending the
stop bit, the master may send additional data to the device
without re-sending the slave and address bytes. After writing to
address 0AH, the address “wraps around’ to address 0.
SCL
1010 001x
I2C
BLOCK
LEVEL
SHIFT
SDA
SCLHV
LEVEL
SHIFT
SDAOHV
I2C
BLOCK
SDAI
SDAIHV
SDAO
FIGURE 15. I2C CASCADED INTERFACE
Read Operations
Cascade Operation
Read operations are initiated in the same manner as write
operations with the host sending the address where the read
is to start (but no data). Then, the host sends an ACK, a
repeated start and the slave byte with the LSB = 1. After the
device acknowledges the slave byte, the device sends out
one bit of data for each master clock. After the slave sends 8
bits to the master, the master sends a NACK (Not
acknowledge) to the device to indicate that the data transfer
is complete, then the master sends a stop bit. See Figure 13.
When devices are cascaded, the lower device has the I2C
slave address of 0101 000x and the upper device has the
address 0101 001x (See Figure 14), but the operation of
cascaded devices is transparent to the microcontroller
master device.
The serial interface between cascaded ISL9216 and
ISL9217 devices has one clock and two data lines. There is
also a high voltage reference for this commication link. See
Figure 15. The interface lines are:
After sending the eighth data bit to the master, the device
automatically increments its internal address pointer.
Therefore, the master, instead of sending a NACK and the
stop bit, can send additional clocks to read the contents of
the next register - without sending another slave and
address byte.
• SCLHV, which is a level shifted clock from the lower
device (ISL9216) to the upper device (ISL9217);
• SDAOHV and SDAO, which send level shifted data out of
the ISL9216 and ISL9217 (respectively); and
• SDAIHV and SDAI, which are level shifted inputs into the
ISL9216 and ISL9217 (respectively).
If the last address read or written is known, the master can
initiate a current address read. In this case, only the slave byte
is sent before data is returned. See Figure 13.
• HVI2C (ISL9216), which is a reference voltage for the level
shifted interface. This connects to the ISL9217 RGO pin.
SIGNALS
FROM THE
MASTER
RANDOM READ
SIGNALS
FROM THE
SLAVE
SDA BUS
S
T
A
R
T
SLAVE
BYTE
S
T
A
R
T
REGISTER
ADDRESS
CURRENT ADDRESS READ
N
A
C
K
SLAVE
BYTE
S
T
O
P
A
C
K
A
C
K
N
A
C
K
SLAVE
BYTE
S
T
O
P
0 1 0 1 0 0 0 1
0 1 0 1 0 0 0 1
0 1 0 1 0 0 0 0
S
T
A
R
T
A
C
K
DATA
A
C
K
DATA
ISL9208: SLAVE BYTE = 010100xH
FIGURE 13. READ SEQUENCE
27
FN6488.1
November 2, 2007
ISL9216, ISL9217
When data is clocked into the ISL9216 through the I2C port, it
is immediately transferred to the serial cascade port, so both
the ISL9216 and ISL9217 see the slave byte at the same
time. After the 8th slave bit, the device that receives the
correct slave byte sends an acknowledge, while the other
device ignores all subsequent data on the serial port until it
receives a stop bit. However, even though the ISL9216
ignores the data, it still passes it through to the ISL9217.
The SDAI and SDAO pins of the ISL9217 need to have pullup resistors of approximately 4.7kΩ, since the output drivers
are open-drain devices.
Register Protection
The Discharge Set, Charge Set, and Feature Set
configuration registers are write protected on initial powerup. In order to write to these registers it is necessary to set a
bit to enable each one. These write enable bits are in the
Write Enable register (Address 08H).
Write the FSETEN bit (Addr 8:bit 7) to “1” to change the data
in the Feature Set register (Address 7).
Write the CHSETEN bit (Addr 8:bit 6) to “1” to change the
data in the Feature Set register (Address 6).
Write the DISSETEN bit (Addr 8:bit 5) to “1” to change the
data in the Feature Set register (Address 5).
The microcontroller can reset these bits back to zero to
prevent inadvertent writes that change the operation of the
pack.
Operation State Machine
Figure 16 shows a device state machine which defines how
the ISL9216 and ISL9217 respond to various conditions.
Power Fails and one of the supplies, VCC, VCELL1, VCELL2,
and VCELL3 do not meet minimum voltage requirements
POWER-DOWN STATE
I2C interface is disabled. Biasing is disabled.
All registers set to default values (All “0”)
Power is applied and all of the supplies, VCC, VCELL1,
VCELL2, and VCELL3 meet minimum voltage requirements
POWER-UP STATE
I2C interface is enabled. Biasing is enabled.
Voltage Regulator is enabled.
MAIN OPERATING STATE
SLEEP STATE
Voltage Regulator is ON
Voltage Regulator is OFF
Logic and registers are powered by RGO
CFET, DFET, Cell balancing outputs are all off.
(Require external command to turn on)
Charge and discharge current protection
circuits and temperature protection circuits are
active (Default). Overcurrent conditions force
power FETs to turn off. Over-temperature
conditions force power FETs and cell balance
outputs to turn off.
Voltage and temperature monitoring circuits
are awaiting external control.
Biasing is OFF
SLEEP bit is set to ‘1’
Logic and registers are powered by VCELL1
CFET, DFET, Cell balancing outputs are all off.
WKUP goes above or below
threshold (edge triggered).
[ISL9217 wake-up requires µC
command to ISL9216].
Or, SLEEP bit is set to ‘0’
Charge and discharge current protection
circuits all off.
Voltage and temperature monitoring circuits
are off.
I2C communication is active (if VCELL1 voltage
is high enough to operate with external
device.)
FIGURE 16. DEVICE OPERATION STATE MACHINE
28
FN6488.1
November 2, 2007
ISL9216, ISL9217
Applications Circuits
The following application circuits are ideas to consider when developing a battery pack implementation. There are many more
ways that the pack can be designed.
P+
ISL9217
VC7/VCC
CB7
VCELL6
SCL
CB6
SDAI
VCELL5
SDAO
500
CB5
WKUP
VCELL4
CB4
RGC
VCELL3
RGO
CB3
VCELL2
CB2
4.7µF
VCELL1
CB1
VSS
AO
VSS2
ISL9216
VC7/VCC
1.2M
SDAIHV
HVI2C
SDAOHV
VCELL6
SCLHV
WKUPR
SCL
10M
500
SDA
VCELL5
WKUP
CB5
RGC
VCELL4
RGO
1µF
µC
CB4
THERM
VCELL3
TEMP3V
RESET
TEMPI
GP
I/O
AO
SCL
SDA
INT
A/D INPUT
CB3
VCELL2
CB2
VCELL1
4.7µF
VMON
CB1
CFET
VSS
DFET
DSENSE
DSREF
CSENSE
MAXMIZE GAUGE
OPTIONAL
LEDs
RESISTORS
CHRG
100
I/O
3.6V
10M
MINIMIZE LENGTH
VCC
24V
SINGLE WIRE
INTERFACE
NEEDED DURING
DISCHARGE
250k
16V
PB-
FIGURE 17. 12-CELL CASCADED APPLICATION CIRCUIT WITH INTEGRATED CHARGE/DISCHARGE
29
FN6488.1
November 2, 2007
ISL9216, ISL9217
P+
ISL9217
VC7/VCC
CB7
1.2M
VCELL6
SCL
CB6
SDAI
VCELL5
SDAO
500
CB5
WKUP
VCELL4
CB4
RGC
VCELL3
RGO
CB3
VCELL2
CB2
4.7µF
VCELL1
CB1
VSS
AO
VSS2
ISL9216
SDAIHV
HVI2C
VC7/VCC
SDAOHV
VCELL6
SCLHVL
WKUPR
SCL
10M
500
SDA
VCELL5
WKUP
CB5
RGC
VCELL4
RGO
1µF
CB4
THERM
VCELL3
TEMP3V
VCC
RESET
TEMPI
GP
I/O
AO
SCL
SDA
INT
A/D INPUT
CB3
VCELL2
4.7µF
µC
CB2
VCELL1
VMON
CB1
CFET
VSS
DFET
OPTIONAL
DSENSE
DSREF
CSENSE
24V
MAXMIZE GAUGE
CHRG
100
I/O
3.6V
10M
MINIMIZE LENGTH
OPTIONAL
LEDs
RESISTORS
SINGLE WIRE
INTERFACE NOT
NEEDED DURING
DISCHARGE
250k
OPTIONAL
16V
CHG
P-
B-
FIGURE 18. 12-CELL CASCADED APPLICATION CIRCUIT WITH SEPARATE CHARGE/DISCHARGE
30
FN6488.1
November 2, 2007
ISL9216, ISL9217
P+
ISL9217
VC7/VCC
SW
CB7
VCELL6
SCL
CB6
SDAI
VCELL5
SDAO
500
CB5
WKUP
VCELL4
CB4
RGC
VCELL3
RGO
CB3
1.6M
VCELL2
CB2
4.7µF
VCELL1
CB1
VSS
AO
VSS2
16V
ISL9216
SDAIHV
HVI2C
VC7/VCC
SDAOHV
VCELL6
SCLHV
WKUPR
SCL
500
SDA
VCELL5
WKUP
CB5
RGC
VCELL4
RGO
1µF
CB4
THERM
VCELL3
TEMP3V
RESET
GP
I/O
AO
SCL
SDA
INT
A/D INPUT
VCELL2
CB2
VCELL1
VMON
CB1
CFET
VSS
DFET
10M
OPTIONAL
DSENSE
DSREF
CHRG
100
3.6V
SINGLE WIRE INTERFACE
NOT NEEDED DURING
DISCHARGE
24V
MAXMIZE GAUGE
OPTIONAL
LEDs
RESISTORS
I/O
CSENSE
MINIMIZE LENGTH
VCC
TEMPI
CB3
4.7µF
µC
OPTIONAL
16V
CHG
P-
B-
FIGURE 19. 12-CELL CASCADED APPLICATION CIRCUIT WITH SEPARATE CHARGE/DISCHARGE AND SWITCH WAKE-UP
31
FN6488.1
November 2, 2007
ISL9216, ISL9217
Package Outline Drawing
L24.4x4D
24 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 10/06
4X 2.5
4.00
A
20X 0.50
B
PIN 1
INDEX AREA
PIN #1 CORNER
(C 0 . 25)
24
19
1
4.00
18
2 . 50 ± 0 . 15
13
0.15
(4X)
12
7
0.10 M C A B
0 . 07
24X 0 . 23 +- 0
. 05 4
24X 0 . 4 ± 0 . 1
TOP VIEW
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
C
0 . 90 ± 0 . 1
BASE PLANE
( 3 . 8 TYP )
SEATING PLANE
0.08 C
SIDE VIEW
(
2 . 50 )
( 20X 0 . 5 )
C
0 . 2 REF
5
( 24X 0 . 25 )
0 . 00 MIN.
0 . 05 MAX.
( 24X 0 . 6 )
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
32
FN6488.1
November 2, 2007
ISL9216, ISL9217
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L32.5x5B
32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VHHD-2 ISSUE C
MILLIMETERS
SYMBOL
MIN
NOMINAL
MAX
NOTES
A
0.80
0.90
1.00
-
A1
-
-
0.05
-
A2
-
-
1.00
A3
b
0.18
D
0.23
9
0.30
5,8
5.00 BSC
D1
D2
9
0.20 REF
-
4.75 BSC
3.15
3.30
9
3.45
7,8
E
5.00 BSC
-
E1
4.75 BSC
9
E2
3.15
e
3.30
3.45
7,8
0.50 BSC
-
k
0.25
-
-
-
L
0.30
0.40
0.50
8
L1
-
-
0.15
10
N
32
2
Nd
8
3
Ne
8
3
P
-
-
0.60
9
θ
-
-
12
9
Rev. 1 10/02
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
33
FN6488.1
November 2, 2007
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