DATASHEET

ISL94201
IGNS
E W DES
N
R
O
F
T
N DED
ACEM EN
COMME
ED REPL Center at
N OT R E
D
N
E
M
E C OM
S u p p o rt
c 3, 2008
Data
Sheet
NO R
chnical .intersil.com/tsJuly
e
T
r
u
o
t
contac ERSIL or www
T
1-888-IN
Multi-Cell Li-ion Battery Pack Analog
Front-End
Features
• Four Battery-Backed Software Controlled Flags
The ISL94201 is an analog front end for a microcontroller in
a multi-cell Li-ion battery pack. The ISL94201 supports
battery pack configurations consisting of 4-cells to 7-cells in
series and 1 or more cells in parallel. The ISL94201 provides
an internal 3.3V voltage regulator, and cell voltage monitor
level shifters.
Using an internal analog multiplexer the ISL94201 provides
monitoring of each cell voltage plus internal and external
temperature by a separate microcontroller with an A/D
converter. Software on this microcontroller implements all
battery pack control functionality.
PACKAGE
(Pb-free)
942 01IRTZ
• Monitored Cell Voltage Output Stable In 100µs
• Simple I2C Host Interface
• Sleep Operation With Programmable Negative Edge or
Positive Edge Wake-Up
• <10µA Sleep Mode
• Pb-Free (RoHS compliant)
24 Ld 4x4 QFN
PKG.
DWG. #
L24.4x4D
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
• Power Tools
• Battery Backup Systems
• E-Bikes
• Portable Test Equipment
• Medical Systems
• Hybrid Vehicle
• Military Electronics
Pinout
1
SCL
SDA
WKUP
RGC
RGO
TEMP3V
ISL94201
(24 LD QFN)
TOP VIEW
24
23
22
21
20
19
2
17
AO
VCELL6
3
16
NC
VCELL5
4
15
NC
NC
5
14
NC
VCELL4
6
13
VSS
7
8
9
10
11
12
VSS
VC7/VCC
VSS
TEMPI
VSS
18
VCELL1
1
VCELL2
NC
VCELL3
ISL94201IRZ
PART
MARKING
• 10% Accurate 3.3V Voltage Regulator (Minimum 25mA
Out With External NPN Transistor Having Current Gain
of 70)
Applications
Ordering Information
PART NUMBER
(Note)
FN6719.0
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL94201
Functional Diagram
SCL SDA
I2C I/F
VC7/VCC
CELL
VOLTAGES
VCELL6
2
7
VCELL5
MUX
POWER
CONTROL
LEVEL
SHIFTERS
VCELL4
REGISTERS
3.3VDC
REGULATOR
VCELL3
VCELL2
CONTROL
LOGIC
VCELL1
OSC
WKUP
RGC
RGO
TEMPERATURE
SENSOR, INT/EXT
COMPARATOR
EXT TEMP
ENABLE
BACKUP
SUPPLY
VSS
TEMPI TEMP3V
AO
Pin Descriptions
SYMBOL
DESCRIPTION
VC7/VCC
Battery cell 7 voltage input/VCC supply. This pin is used to monitor the voltage of this battery cell externally at pin AO. This pin also
provides the operating voltage for the IC circuitry.
VCELLN
Battery cell N voltage input. This pin is used to monitor the voltage of this battery cell externally at pin AO. VCELLN connects to the
positive terminal of CELLN and the negative terminal of CELLN + 1.
VSS
Ground. This pin connects to the most negative terminal in the battery string.
AO
Analog multiplexer output. The analog output pin is used by an external microcontroller to monitor the cell voltages and temperature
sensor voltages. The microcontroller selects the specific voltage being applied to the output by writing to a control register.
TEMP3V
Temperature monitor output control. This pin outputs a voltage to be used in a divider that consists of a fixed resistor and a
thermistor. The thermistor is located in close proximity to the cells. The TEMP3V output is connected internally to the RGO voltage
through a PMOS switch only during a measurement of the temperature, otherwise the TEMP3V output is off. The TEMP3V output can
be turned on continuously with a special control bit.
Microcontroller wake up control.
TEMPI
Temperature monitor input. This pin inputs the voltage across a thermistor to determine the temperature of the cells. When this input
drops below TEMP3V/13, an external over-temperature condition exists. The TEMPI voltage is also fed to the AO output pin through
an analog multiplexer so the temperature of the cells can be monitored by the microcontroller.
RGO
Regulated output voltage. This pin connects to the emitter of an external NPN transistor and works in conjunction with the RGC pin
to provides a regulated 3.3V. The voltage at this pin provides feedback for the regulator and power for many of the ISL94201internal
circuits as well as providing the 3.3V output voltage for the microcontroller and other external circuits.
RGC
Regulated output control. This pin connects to the base of an external NPN transistor and works in conjunction with the RGO pin to
provide a regulated 3.3V. The RGC output provides the control signal for the external transistor to provide the 3.3V regulated voltage
on the RGO pin.
WKUP
Wake up Voltage. This input wakes up the part when the voltage crosses a turn-on threshold (wake up is edge triggered). The
condition of the pin is reflected in the WKUP bit (The WKUP bit is level sensitive.)
WKPOL bit = ”1”: the device wakes up on the rising edge of the WKUP pin. Also, the WKUP bit is HIGH only when the WKUP pin
voltage > threshold.
WKPOL bit = ”0”, the device wakes up on the falling edge of the WKUP pin. Also, the WKUP bit is HIGH only when the WKUP pin
voltage < threshold.
SDA
Serial Data. This is the bidirectional data line for an I2C interface.
SCL
Serial Clock. This is the clock input for an I2C communication link.
2
FN6719.0
July 3, 2008
ISL94201
Absolute Maximum Ratings
Thermal Information
Power Supply Voltage, VCC . . . . . . . . . .VSS - 0.5V to VSS + 36.0V
Cell voltage, VCELL
VCELLN - (VCELLN - 1), VCELL1 - VSS . . . . . . . . . . . -0.5V to 5V
Terminal Voltage, VTERM1
(SCL, SDA, TEMPI, RGO, AO, TEMP3V)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS - 0.5 to VRGO + 0.5V
Terminal Voltage, VTERM3 (WKUP)
. . . . . . . . . . . . . . . . . . . . . . . . . . . VSS - 0.5V to VCC (VCC <27V)
Terminal Voltage, VTERM4 (RGC) . . . . . . . . . . . . . VSS - 0.5V to 5V
Terminal Voltage, VTERM5, (all other pins)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS - 0.5V to VCC + 0.5V
Thermal Resistance (Typical, Notes 1, 2) JA (°C/W) JC (°C/W)
24 Ld QFN . . . . . . . . . . . . . . . . . . . . . .
32
2
Continuous Package Power Dissipation . . . . . . . . . . . . . . . . .400mW
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . -55 to +125°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage Range (Typical). . . . . . . . . . . . . . . . . . . . 5V to 10V
Operating Voltage:
VCC pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2V to 30.1V
VCELL1 - VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3V to 4.3V
VCELLN - (VCELLN-1) . . . . . . . . . . . . . . . . . . . . . . . 2.3V to 4.3V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Operating Specifications Over the recommended operating conditions unless otherwise specified. Parameters with MIN and/or MAX
limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested
PARAMETER
SYMBOL
Operating Voltage
TEST CONDITION
VCC
MIN
TYP
MAX
UNIT
30.1
V
4
9.2
V
1.7
2.3
V
9.2
Power-Up Condition 1
VPORVCC VCC voltage (Note 3)
Power-Up Condition 2 Threshold
VPOR123 VCELL1 - VSS and VCELL2 - VCELL1 and
VCELL3 - VCELL2 (rising) (Note 3)
Power-Up Condition 2 Hysteresis
VPORhys VCELL1 - VSS and VCELL2 - VCELL1 and
VCELL3 - VCELL2 (falling) (Note 3)
1.1
70
mV
3.3V Regulated Voltage
VRGO
0µA < IRGC < 350µA
3.0
3.3
3.6
V
3.3VDC Voltage Regulator Control
Current Limit
IRGC
(Control current at output of RGC.
Recommend NPN with gain of 70+)
0.35
0.50
VCC Supply Current
IVCC1
Power-up defaults, WKUP pin = 0V.
400
510
µA
RGO Supply Current
IRGO1
Power-up defaults, WKUP pin = 0V.
300
410
µA
VCC Supply Current
IVCC2
LDMONEN bit = 1, WKPOL bit = 1,
VWKUP = 10V, [AO3:AO0] bits = 03H.
500
700
µA
RGO Supply Current
IRGO2
LDMONEN bit = 1, WKPOL bit = 1,
VWKUP = 10V, [AO3:AO0] bits = 03H.
450
650
µA
VCC Supply Current
IVCC3
Default register settings, except
SLEEP bit = 1. WKUP pin = VCELL1
10
µA
RGO Supply Current
IRGO3
Default register settings, except
SLEEP bit = 1. WKUP pin = VCELL1
1
µA
mA
VCELL Input Current (VCELL1)
IVCELL1
AO3:AO0 bits = 0000H
14
µA
VCELL Input Current (VCELLN)
IVCELLN AO3:AO0 bits = 0000H
10
µA
3
FN6719.0
July 3, 2008
ISL94201
Operating Specifications Over the recommended operating conditions unless otherwise specified. Parameters with MIN and/or MAX
limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested (Continued)
PARAMETER
SYMBOL
TEST CONDITION
MIN
TYP
MAX
UNIT
OVER-TEMPERATURE PROTECTION SPECIFICATIONS
Internal Temperature Shutdown
Threshold
TINTSD
Internal Temperature Hysteresis
THYS
Internal Over-temperature Turn On
Delay Time
tITD
External Temperature Output Current
IXT
External Temperature Limit Threshold
TXTF
Temperature drop needed to restore
operation after over-temperature
shutdown.
125
°C
20
°C
128
ms
Current output capability at TEMP3V pin
1.2
mA
Voltage at VTEMPI; Relative to falling
edge V TEMP3V
-20
0
+20
mV
60
110
160
mV
------------------------------
13
External Temperature Limit Hysteresis
TXTH
Voltage at VTEMPI.
External Temperature Monitor Delay
tXTD
Delay between activating the external
sensor and the internal over-temperature
detection.
1
ms
TEMP3V is ON (3.3V)
5
ms
635
ms
External Temperature Autoscan
On-Time
tXTAON
External Temperature Autoscan
Off-Time
tXTAOFF TEMP3V output is off.
ANALOG OUTPUT SPECIFICATIONS
Cell Monitor Analog Output Voltage
Accuracy
VAOC
[VCELLN - (VCELLN-1)]/2 - AO
-15
Cell Monitor Analog Output External
Temperature Accuracy
VAOXT
External temperature monitoring accuracy.
Voltage error at AO when monitoring
TEMPI voltage (measured with
TEMPI = 1V)
-10
Internal Temperature Monitor Output
Voltage Slope
Internal Temperature Monitor Output
AO Output Stabilization Time
VINTMON Internal temperature monitor voltage
change
TINT25
tVSC
Output at +25°C
4
30
mV
10
mV
-3.5
mV/°C
1.31
V
From SCL falling edge at data bit 0 of
command to AO output stable within 0.5%
of final value. AO voltage steps from 0V to
2V. (CAO = 10pF) (Note 7)
0.1
ms
6.5
V
WAKE UP/SLEEP SPECIFICATIONS
Device WKUP Pin Voltage Threshold VWKUP1 WKUP pin rising edge (WKPOL = 1)
Device wakes up and sets WKUP flag
(WKUP Pin Active High - Rising Edge)
HIGH.
Device Wkup Pin Hysteresis
(WKUP Pin Active High)
3.5
VWKUP1H WKUP pin falling edge hysteresis
(WKPOL = 1) sets WKUP flag LOW (does
not automatically enter sleep mode)
Input Resistance On WKUP
RWKUP
Device WKUP Pin Active Voltage
Threshold (WKUP Pin Active Low Falling Edge)
VWKUP2 WKUP pin falling edge (WKPOL = 0)
Device wakes up and sets WKUP flag
HIGH.
4
Resistance from WKUP pin to VSS
(WKPOL = 1)
5.0
100
130
VCELL1 - 2.6
230
mV
330
k
VCELL1 - 2.0 VCELL1 - 1.2
V
FN6719.0
July 3, 2008
ISL94201
Operating Specifications Over the recommended operating conditions unless otherwise specified. Parameters with MIN and/or MAX
limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested (Continued)
PARAMETER
SYMBOL
Device Wkup Pin Hysteresis
(WKUP Pin Active Low)
TEST CONDITION
MIN
tWKUP
Delay after voltage on WKUP pin crosses
the threshold (rising or falling) before
activating the WKUP bit.
MAX
UNIT
200
VWKUP2H WKUP pin rising edge hysteresis
(WKPOL = 0) sets WKUP flag LOW (does
not automatically enter sleep mode).
Device Wake-up Delay
TYP
20
40
mV
60
ms
100
kHz
SERIAL INTERFACE CHARACTERISTICS
SCL Clock Frequency
fSCL
Pulse Width Suppression Time at
SDA and SCL Inputs
tIN
Any pulse narrower than the max spec is
suppressed.
50
ns
SCL Falling Edge to SDA Output Data
Valid
tAA
From SCL falling crossing VIH(min), until
SDA exits the VIL(max) to VIH(min)
window.
3.5
µs
Time the Bus Must Be Free Before
Start of New Transmission
tBUF
SDA crossing VIH(min) during a STOP
condition to SDA crossing VIH(min) during
the following START condition.
4.7
µs
Clock Low Time
tLOW
Measured at the VIL(max) crossing.
4.7
µs
Clock High Time
tHIGH
Measured at the VIH(min) crossing.
4.0
µs
Start Condition Setup Time
tSU:STA
SCL rising edge to SDA falling edge. Both
crossing the VIH(min) level.
4.7
µs
Start Condition Hold Time
tHD:STA
From SDA falling edge crossing VIL(max)
to SCL falling edge crossing VIH(min).
4.0
µs
Input Data Setup Time
tSU:DAT
From SDA exiting the VIL(max) to VIH(min)
window to SCL rising edge crossing
VIL(min).
250
ns
Input Data Hold Time
tHD:DAT
From SCL falling edge crossing VIH(min) to
SDA entering the VIL(max) to VIH(min)
window.
300
µs
Stop Condition Setup Time
tSU:STO
From SCL rising edge crossing VIH(min) to
SDA rising edge crossing VIL(max).
4.0
µs
Stop Condition Hold Time
tHD:STO From SDA rising edge to SCL falling edge.
Both crossing VIH(min).
4.0
µs
0
ns
Data Output Hold Time
tDH
From SCL falling edge crossing VIL(max)
until SDA enters the VIL(max) to VIH(min)
window. (Note 4)
SDA and SCL Rise Time
tR
From VIL(max) to VIH(min).
1000
ns
SDA and SCL Fall Time
tF
From VIH(min) to VIL(max).
300
ns
Capacitive Loading Of SDA Or SCL
(Note 5)
Cb
Total on-chip and off-chip
400
pF
SDA and SCL Bus Pull-up ResistorOff-Chip (Note 5)
ROUT
Input Leakage Current (SCL, SDA)
ILI
Input Buffer Low Voltage (SCL, SDA)
VIL
5
Maximum is determined by tR and tF.
For CB = 400pF, max is about 2k~ 2.5k
For CB = 40pF, max is about 15k to 20k
Voltage relative to VSS of the device.
1
k
-10
10
µA
-0.3
VRGO x 0.3
V
FN6719.0
July 3, 2008
ISL94201
Operating Specifications Over the recommended operating conditions unless otherwise specified. Parameters with MIN and/or MAX
limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested (Continued)
PARAMETER
SYMBOL
TEST CONDITION
Input Buffer High Voltage (SCL, SDA)
VIH
Voltage relative to VSS of the device.
Output Buffer Low Voltage (SDA)
VOL
IOL = 1mA
SDA and SCL Input Buffer Hysteresis I2CHYST Sleep bit = 0
(Note 5)
MIN
TYP
VRGO x 0.7
MAX
UNIT
VRGO + 0.1
V
0.4
V
0.05 * VRGO
V
NOTES:
3. Power-up of the device requires all VCELL1, VCELL2, VCELL3, and VCC to be above the limits specified.
4. The device provides an internal hold time of at least 300ns for the SDA signal to bridge the unidentified region of the falling edge of SCL.
5. Limits should be considered typical and are not production tested.
6. Typical 5 ±2, based on characterization data.
7. Maximum output capacitance = 15pF.
Wake up timing (WKPOL = 0)
<tWKUP
VWKUP2H
VWKUP2
<tWKUP
WKUP PIN
tWKUP
tWKUP
WKUP BIT
Wake up timing (WKPOL = 1)
<tWKUP
VWKUP1
VWKUP1H
WKUP PIN
<tWKUP
tWKUP
tWKUP
WKUP BIT
Change in Voltage Source
SCL
BIT
3
SDA
BIT
2
BIT
1
BIT
0
BIT
1
BIT
0
DATA
AO
tVSC
6
tVSC
FN6719.0
July 3, 2008
ISL94201
Automatic Temperature Scan
AUTO TEMP CONTROL
(INTERNAL ACTIVATION)
635ms
MONITOR TIME = 5ms
3.3V
HIGH IMPEDANCE
TEMP3V PIN
EXTERNAL
TEMPERATURE
OVER-TEMPERATURE
THRESHOLD
TMP3V/13
DELAY TIME = 1ms
DELAY TIME = 1ms
MONITOR TEMP DURING THIS
TIME PERIOD
XOT BIT
Serial Interface Timing Diagrams
Bus Timing
tF
tHIGH
tLOW
tR
SCL
tSU:STA
tSU:DAT
tHD:STA
tHD:DAT
tSU:STO
SDA
(INPUT TIMING)
tAA
tBUF
tDH
SDA
(OUTPUT TIMING)
Symbol Table
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
WILL BE
STEADY
MAY CHANGE
FROM LOW
TO HIGH
WILL CHANGE
FROM LOW
TO HIGH
MAY CHANGE
FROM HIGH
TO LOW
WILL CHANGE
FROM HIGH
TO LOW
7
WAVEFORM
INPUTS
OUTPUTS
DON’T CARE:
CHANGES
ALLOWED
CHANGING:
STATE NOT
KNOWN
N/A
CENTER LINE
IS HIGH
IMPEDANCE
FN6719.0
July 3, 2008
ISL94201
Registers
TABLE 1. REGISTERS
ADDR
REGISTER
READ/WRITE
7
6
5
4
3
2
1
0
00H
Config/Op
Status
Read only
Reserved
Reserved
SA
Single AFE
WKUP
WKUP pin
Status
Reserved
Reserved
Reserved
Reserved
01H
Operating
Status
Read only
Reserved
Reserved
XOT
Ext over
temp
IOT
Int over
Temp
Reserved
Reserved
Reserved
Reserved
02H
Not Used
Read/Write
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
03H
Analog Out
Read/Write
Reserved
Reserved
AO3
AO2
AO1
AO0
(Note 10)
UFLG1
UFLG0
User Flag 1 User Flag 0
Analog output select bits
04H
Control
Read/Write
SLEEP
Force
Sleep
(Note 11)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
05H
Not Used
Read/Write
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
06H
Not Used
Read/Write
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
07H
Feature Set
Read/Write
(Write only if
FSETEN
bit set)
DIS3
ATMPOFF
Turn off Disable 3.3V
automatic reg. (device
requires
external
external
temp scan
3.3V)
TMP3ON
Turn on
Temp3V
Reserved
Reserved
POR
DISWKUP
Force POR Disable
WKUP pin
WKPOL
Wake Up
Polarity
08H
Write Enable
Read/Write
FSETEN
Enable
Feature
Set writes
09H:FFH
Reserved
NA
Reserved
Reserved
UFLG3
UFLG2
Reserved
User Flag 3 User Flag 2
Reserved
Reserved
RESERVED
NOTES:
8. A “1” written to a control or configuration bit causes the action to be taken. A “1” read from a status bit indicates that the condition exists.
9. “Reserved” indicates that the bit or register is reserved for future expansion. When writing to addresses 2, 3, 4, and 8: write a reserved bit with
the value “0”. Do not write to reserved registers at addresses 09H through FFH. Ignore reserved bits that are returned in a read operation.
10. These status bits are automatically cleared when the register is read. All other status bits are cleared when the condition is cleared.
11. This SLEEP bit is cleared on initial power up, by the WKUP pin going high (when WKPOL = ”1”) or by the WKUP pin going low (when
WKPOL = ”0”), and by writing a “0” to the location with an I2C command.
Status Registers
TABLE 2. CONFIG/OP STATUS REGISTER (ADDR: 00H)
BIT
FUNCTION
DESCRIPTION
7
RESERVED
Reserved for future expansion.
6
RESERVED
Reserved for future expansion.
5
SA
Single AFE
Indicates the device is an ISL94201. This bit is set in the chip and cannot be changed.
4
WKUP
This bit is set and reset by hardware.
Wakeup pin status When ‘WKPOL’ is HIGH:
’WKUP’ HIGH = WKUP pin > Threshold voltage
‘WKUP’ LOW = WKUP pin < Threshold voltage
When ‘WKPOL’ is LOW:
’WKUP’ HIGH = WKUP pin < Threshold voltage
‘WKUP’ LOW = WKUP pin > Threshold voltage
3
RESERVED
Reserved for future expansion.
8
FN6719.0
July 3, 2008
ISL94201
TABLE 2. CONFIG/OP STATUS REGISTER (ADDR: 00H) (Continued)
BIT
FUNCTION
DESCRIPTION
2
RESERVED
Reserved for future expansion.
1
RESERVED
Reserved for future expansion.
0
RESERVED
Reserved for future expansion.
TABLE 3. OPERATING STATUS REGISTER (ADDR: 01H)
BIT
FUNCTION
DESCRIPTION
7
RESERVED
Reserved for future expansion.
6
RESERVED
Reserved for future expansion.
5
XOT
Ext Over-temp
This bit is set to “1” when the external thermistor indicates an over-temperature condition. If the temperature
condition has cleared, this bit is reset when the register is read.
4
IOT
Int Over-temp
This bit is set to “1” when the internal thermistor indicates an over-temperature condition. If the temperature condition
has cleared, this bit is reset when the register is read.
3
RESERVED
Reserved for future expansion.
2
RESERVED
Reserved for future expansion.
1
RESERVED
Reserved for future expansion.
0
RESERVED
Reserved for future expansion.
Control Registers
TABLE 4. ANALOG OUT CONTROL REGISTER (ADDR: 03H)
BITS
FUNCTION
DESCRIPTION
7
UFLG1
User Flag 1
General purpose flag usable by microcontroller software. This bit is battery backed up, even
when RGO turns off.
6
UFLG0
User Flag 0
General purpose flag usable by microcontroller software. This bit is battery backed up, even
when RGO turns off.
5:4
RESERVED
Reserved for future expansion
BIT 3
AO3
BIT 2
AO2
BIT 1
AO1
BIT 0
AO0
0
0
0
0
No Output (low power state)
0
0
0
1
VCELL1
0
0
1
0
VCELL2
0
0
1
1
VCELL3
0
1
0
0
VCELL4
0
1
0
1
VCELL5
0
1
1
0
VCELL6
0
1
1
1
VCELL7
1
0
0
0
External Temperature
1
0
0
1
Internal Temperature
1
x
1
x
RESERVED
1
1
x
x
RESERVED
9
OUTPUT VOLTAGE
FN6719.0
July 3, 2008
ISL94201
Configuration Registers
The device is configured for specific application
requirements using the Configuration Registers. The
configuration registers consist of SRAM memory.
This memory is powered by the RGO output. In a sleep
condition, an internal switch converts power for the contents
of these registers from RGO to the VCELL1 input.
TABLE 5. CONTROL REGISTER (ADDR: 04H)
BIT
FUNCTION
DESCRIPTION
7
SLEEP
Force Sleep
Setting this bit to “1” forces the device to go into a sleep condition. This turns off the voltage
regulator. The SLEEP bit is automatically reset to “0” when the device wakes up. This bit does
not reset the AO3:AO0 bits.
6:0
RESERVED
Reserved for future expansion.
TABLE 6. FEATURE SET CONFIGURATION REGISTER (ADDR: 07H)
BIT
FUNCTION
DESCRIPTION
7
ATMPOFF
When set to ‘1’ this bit disables the automatic temperature scan. When set to ‘0’, the temperature
Turn off automatic external temp scan is turned on for 5ms in every 640ms.
6
DIS3
Disable 3.3V regulator
Setting this bit to “1” disables the internal 3.3V regulator. Setting this bit to “1” requires that there
be an external 3.3V regulator connected to the RGO pin.
5
TMP3ON
Turn on Temp 3.3V
Setting this bit to “1” turns ON the TEMP3V output to the external temperature sensor. The
output will remain on as long as this bit remains “1”.
4
RESERVED
Reserved for future expansion.
3
RESERVED
Reserved for future expansion.
2
POR
Force POR
Setting this bit to “1” forces a POR condition. This resets all internal registers to zero.
1
DISWKUP
Disable WKUP pin
Setting this bit to “1” disables the WKUP pin function.
CAUTION: Setting this pin to ‘1’ prevents a wake up condition. If the device then goes to sleep,
it cannot be waken without a communication link that resets this bit, or by power cycling the
device.
0
WKPOL
Wake Up Polarity
Setting this bit to “1” sets the device to wake up on a rising edge at the WKUP pin.
Setting this bit to “0” sets the device to wake up on a falling edge at the WKUP pin.
.
TABLE 7. WRITE ENABLE REGISTER (ADDR: 08H)
BIT
FUNCTION
DESCRIPTION
7
FSETEN
When set to “1”, allows writes to the Feature Set register. When set to “0”, prevents writes to the Feature
Enable discharge set writes Set register (Addr: 07H). Default on initial power up is “0”.
6
RESERVED
Reserved for future expansion.
5
RESERVED
Reserved for future expansion.
4
UFLG3
User Flag 3
General purpose flag usable by microcontroller software. This bit is battery backed up, even when RGO
turns off.
3
UFLG2
User Flag 3
General purpose flag usable by microcontroller software. This bit is battery backed up, even when RGO
turns off.
2
RESERVED
Reserved for future expansion.
1
RESERVED
Reserved for future expansion.
0
RESERVED
Reserved for future expansion.
10
FN6719.0
July 3, 2008
ISL94201
Device Description
Battery Connection
Design Theory
Instructed by the microcontroller, the ISL94201 performs cell
voltage and temperature monitoring.
The ISL94201supports packs of 5 to 7 series connected
Li-ion cells. Connection guidelines for each cell combination
are shown in Figure 1.
7 CELLS
6 CELLS
5 CELLS
4 CELLS
VCELL7
VCELL7
VCELL7
VCELL7
VCELL6
VCELL6
VCELL6
VCELL6
VCELL5
VCELL5
VCELL5
VCELL5
VCELL4
VCELL4
VCELL4
VCELL4
VCELL3
VCELL3
VCELL3
VCELL3
VCELL2
VCELL2
VCELL2
VCELL2
VCELL1
VCELL1
VCELL1
VCELL1
VSS
VSS
VSS
VSS
Note: Multiple cells can be connected in parallel
FIGURE 1. BATTERY CONNECTION OPTIONS
System Power-Up/Power-Down
The ISL94201 powers up when the voltages on VCELL1,
VCELL2, VCELL3 and VCC all exceed their POR threshold.
At this time, the ISL94201 wakes up and turns on the RGO
output.
RGO provides a regulated 3.3VDC ±10% voltage at pin
RGO. It does this by using a control voltage on the RGC pin
to drive an external NPN transistor (see Figure 2.) The
transistor should have a beta of at least 70 to provide ample
current to the device and external circuits and should have a
VCE of greater than 30V (preferably 50V). The voltage at the
emitter of the NPN transistor is monitored and regulated to
3.3V by the control signal RGC. RGO also powers most of
the ISL94201internal circuits. A 500 resistor is
recommended in the collector of the NPN transistor to
minimize initial current surge when the regulator turns on.
Once powered up, the device remains in a wake up state
until put to sleep by the microcontroller (typically when the
cells drop too low in voltage) or until the VCELL1, VCELL2,
VCELL3 or VCC voltages drop below their POR threshold.
11
VCC
500
RGC
RGO
3.3V
VSS
GND
FIGURE 2. VOLTAGE REGULATOR CIRCUITS
WKUP Pin Operation
There are two ways to design a wake up of the ISL94201. In
an active LOW connection (WKPOL = “0” - default), the
device wakes up when a charger is connected to the pack.
This pulls the WKUP pin low when compared to a reference
based on the VCELL1 voltage. In an active HIGH connection
(WKPOL = ‘1’) the device wakes up when the WKUP pin is
pulled high by a connection through an external switch.
FN6719.0
July 3, 2008
ISL94201
point to the external temperature, the TEMP3V output
remains on.
ISL94201
WKUP
WKUP
(STATUS)
5V
230k*
WAKE UP
CIRCUITS
WKPOL
(CONTROL)
VCELL1
VSS
* Internal resistor
only connected when
WKPOL=1.
FIGURE 3. WAKE UP CONTROL CIRCUITS
Protection Functions
In the default recommended condition, the
ISL94201automatically detects internal over-temperature,
and external over-temperature conditions. The designer
programs the microcontroller to respond to the
over-temperature indications.
OVER-TEMPERATURE SAFETY FUNCTIONS
External Temperature Monitoring
The external temperature is monitored by using a voltage
divider consisting of a fixed resistor and a thermistor. This
divider is powered by the ISL94201TEMP3V output. This
output is normally controlled so it is on for only short periods
to minimize current consumption.
Because of the manual scan of the temperature, it may be
desired to turn off the automatic scan, although they can be
used at the same time without interference. To turn off the
automatic scan, set the ATMPOFF bit.
The microcontroller can over-ride both the automatic
temperature scan and the microcontroller controlled
temperature scan by setting the TEMP3ON configuration bit.
This turns on the TEMP3V output to keep the temperature
control voltage on all the time, for a continuous monitoring of
an over-temperature condition. This likely will consume a
significant amount of current, so this feature is usually used
for special or test purposes.
Analog Multiplexer Selection
The ISL94201devices can be used to externally monitor
individual battery cell voltages and temperatures. Each
quantity can be monitored at the analog output pin (AO). The
desired voltage is selected using the I2C interface and the
AO3:AO0 bits. See Figure 5.
VOLTAGE MONITORING
Since the voltage on each of the Li-ion Cells are normally
higher than the regulated supply voltage, and since the
voltages on the upper cells is much higher than is tolerated
by a microcontroller, it is necessary to both level shift and
divide the voltage before it can be monitored by the
microcontroller or an external A/D converter. To get into the
voltage range required by the external circuits, the voltage
level shifter divides the cell voltage by 2 and references it to
VSS. Therefore, a Li-ion cell with a voltage of 4.2V becomes
a voltage of 2.1V on the AO pin.
TEMPERATURE MONITORING
Without microcontroller intervention, and in the default state,
the ISL94201provides an automatic temperature scan. This
scan circuit repeatedly turns on TEMP3V output (and the
external temperature monitor) for 5ms out of every 640ms.
In this way, the external temperature is monitored even if the
microcontroller is asleep.
The voltage representing the external temperature applied at
the TEMPI terminal is directed to the AO terminal through a
MUX, as selected by the AO control bits (see Figures 4
and 5). The external temperature voltage is not divided by 2
as are the cell voltages. Instead it is a direct reflection of the
voltage at the TEMPI pin.
When the TEMP3V output turns on, the ISL94201waits 1ms
for the temperature reading to stabilize, then compares the
external temperature voltage with an internal voltage divider
that is set to TEMP3V/13. When the thermistor voltage is
below the reference threshold after the delay, an external
temperature fail condition exists. To set the external
over-temperature limit, set the value of RX resistor to 12x the
resistance of the thermistor at the over-temp threshold.
A similar operation occurs when monitoring the internal
temperature through the AO output, except there is no
external “calibration” of the voltage associated with the
internal temperature. For the internal temperature
monitoring, the voltage at the output is linear with respect to
temperature. See “Operating Specifications” for information
about the output voltage at +25°C and the output slope
relative to temperature on page 4.
The TEMP3V output pin also turns on when the
microcontroller sets the AO3:AO0 bits to select that the
external temperature voltage. This causes the TEMPI
voltage to be placed on AO and activates (after 1ms) the
over-temperature detection. As long as the AO3:AO0 bits
12
FN6719.0
July 3, 2008
ISL94201
User Flags
4ms
I2C
OSC
ISL94201
REGISTERS
The ISL94201contains four flags in the register area that the
microcontroller can use for general purpose indicators.
These bits are designated UFLG3, UFLG2, UFLG1, and
UFLG0. The microcontroller can set or reset these bits by
writing into the appropriate register.
508ms
I2C
ATMPOFF
TMP3ON
RGO
AO3:AO0
TO
µ
DECODE
EXT TEMP
VSS (ON)
MUX
AO
12R
TEMP3V
RX
TEMPI
R
1ms
DELAY
EXTERNAL
TEMP
MONITOR
XOT
VSS
TEMP FAIL
INDICATOR
FIGURE 4. EXTERNAL TEMPERATURE MONITORING
AND CONTROL
The user flag bits are battery backed up, so the contents
remain even after exiting a sleep mode. However, if the
microcontroller sets the POR bit to force a power on reset, all
of the user flags will also be reset. In addition, if the voltage
on cell1 ever drops below the POR voltage, the contents of
the user flags (as well as all other register values) could be
lost.
Serial Interface
INTERFACE CONVENTIONS
The device supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter, and the receiving device as the
receiver. The device controlling the transfer is called the
master and the device being controlled is called the slave.
The master always initiates data transfers, and provides the
clock for both transmit and receive operations. Therefore,
the ISL94201devices operate as slaves in all applications.
When sending or receiving data, the convention is the most
significant bit (MSB) is sent first. So, the first address bit sent
is Bit 7.
CLOCK AND DATA
SCL
SDA
LEVEL
SHIFT
I2C
VC7/VCC
START CONDITION
LEVEL
SHIFT
VCELL6
LEVEL
SHIFT
VCELL2
LEVEL
SHIFT
VCELL1
REGS
AO3:AO0
DECODE
AO
Data states on the SDA line can change only while SCL is
LOW. SDA state changes during SCL HIGH are reserved for
indicating start and stop conditions. See Figure 6.
2
MUX
STOP CONDITION
VSS
EXT TEMP.
TEMPI
INT
TEMP
MUX
FIGURE 5. ANALOG OUTPUT MONITORING DIAGRAM
13
All commands are preceded by the start condition, which is a
HIGH to LOW transition of SDA when SCL is HIGH. The
device continuously monitors the SDA and SCL lines for the
start condition and will not respond to any command until
this condition has been met. See Figure 7.
All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA when SCL is
HIGH. The stop condition is also used to place the device
into the Standby power mode after a read sequence. A stop
condition is only issued after the transmitting device has
released the bus. See Figure 7.
ACKNOWLEDGE
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, releases the bus after transmitting eight
bits. During the ninth clock cycle, the receiver pulls the SDA
line LOW to acknowledge that it received the eight bits of
data. See Figure 8.
FN6719.0
July 3, 2008
ISL94201
In the read mode, the device transmits eight bits of data,
releases the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no stop
condition is generated by the master, the device will
continues to transmit data. The device terminates further
data transmissions if an acknowledge is not detected. The
master must then issue a stop condition to return the device
to Standby mode and place the device into a known state.
SCL
SDA
DATA
STABLE
DATA
CHANGE
DATA
STABLE
FIGURE 6. VALID DATA CHANGES ON I2C BUS
.
WRITE OPERATIONS
For a write operation, the device requires a slave byte and
an address byte. The slave byte specifies the particular
device on the I2C bus that the master is writing to. The
address specifies one of the registers in that device. After
receipt of each byte, the device responds with an
acknowledge, and awaits the next eight bits from the master.
After the acknowledge, following the transfer of data, the
master terminates the transfer by generating a stop
condition. See Figure 9.
When receiving data from the master, the value in the data
byte is transferred into the register specified by the address
byte on the falling edge of the clock following the 8th data bit.
After receiving the acknowledge after the data byte, the
device automatically increments the address. So, before
sending the stop bit, the master may send additional data to
the device without re-sending the slave and address bytes.
After writing to address 0AH, the address “wraps around” to
address 0. Do not continue to write to addresses higher than
address 08H, since these addresses access registers that
are reserved. Writing to these locations can result in
unexpected device operation.
SIGNALS
FROM THE
MASTER
The device responds with an acknowledge after recognition
of a start condition and the correct slave byte. If a write
operation is selected, the device responds with an
acknowledge after the receipt of each subsequent eight bits.
The device acknowledges all incoming data and address
bytes, except for the slave byte when the contents do not
match the device’s internal slave address.
SIGNALS
FROM THE
SLAVE
SDA BUS
SCL
SDA
S
T
A
R
T
SLAVE
BYTE
REGISTER
ADDRESS
S
T
O
P
DATA
0 1 0 1 0 0 0 0
A
C
K
A
C
K
A
C
K
ISL94201: SLAVE BYTE = 50H
START
FIGURE 9. WRITE SEQUENCE
STOP
FIGURE 7. I2C START AND STOP BITS
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM
TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
FIGURE 8. ACKNOWLEDGE RESPONSE FROM RECEIVER
14
FN6719.0
July 3, 2008
ISL94201
After sending the eighth data bit to the master, the device
automatically increments its internal address pointer. So the
master, instead of sending a NACK and the stop bit, can
send additional clocks to read the contents of the next
register - without sending another slave and address byte.
Read Operations
Read operations are initiated in the same manner as write
operations with the host sending the address where the read
is to start (but no data). Then, the host sends an ACK, a
repeated start, and the slave byte with the LSB = 1. After the
device acknowledges the slave byte, the device sends out
one bit of data for each master clock. After the slave sends
eight bits to the master, the master sends a NACK (Not
acknowledge) to the device, to indicate the data transfer is
complete, then the master sends a stop bit. See Figure 10.
If the last address read or written is known, the master can
initiate a current address read. In this case, only the slave
byte is sent before data is returned. See Figure 10.
.
SIGNALS
FROM THE
MASTER
RANDOM READ
SLAVE
BYTE
S
T
A
R
T
REGISTER
ADDRESS
N
A
C
K
SLAVE
BYTE
S
T
O
P
A
C
K
A
C
K
A
C
K
S
T
A
R
T
N
A
C
K
SLAVE
BYTE
S
T
O
P
0 1 0 1 0 0 0 1
0 1 0 1 0 0 0 1
0 1 0 1 0 0 0 0
SIGNALS
FROM THE
SLAVE
SDA BUS
S
T
A
R
T
CURRENT ADDRESS READ
DATA
A
C
K
DATA
ISL94201: SLAVE BYTE = 010100xH
FIGURE 10. READ SEQUENCE
Register Protection
The Feature Set configuration register is write protected on
initial power up. In order to write to these registers it is
necessary to set a bit to enable each one. These write
enable bits are in the Write Enable register (Address 08H).
Write the FSETEN bit (Addr 8:bit 7) to “1” to enable changes
to the data in the Feature Set register (Address 7).
The microcontroller can reset this bits back to zero to
prevent inadvertent writes that change the operation of the
pack.
Operation State Machine
Figure 11 shows a device state machine which defines how
the ISL94201responds to various conditions.
15
FN6719.0
July 3, 2008
ISL94201
POWER FAILS AND ONE OR MORE OF THE SUPPLIES, VCC, VCELL1, VCELL2,
AND VCELL3 DO NOT MEET MINIMUM VOLTAGE REQUIREMENTS
POWER DOWN STATE
I2C INTERFACE IS DISABLED. BIASING IS
DISABLED. ALL REGISTERS SET TO DEFAULT
VALUES (ALL “0”)
Power is applied and all of the supplies, VCC, VCELL1, VCELL2,
and VCELL3 meet minimum voltage requirements
POWER UP STATE
I2C INTERFACE IS ENABLED. BIASING IS
ENABLED. VOLTAGE REGULATOR IS
ENABLED.
MAIN OPERATING STATE
SLEEP STATE
VOLTAGE REGULATOR IS ON
VOLTAGE REGULATOR IS OFF
LOGIC AND REGISTERS ARE POWERED
BY RGO
SLEEP bit is set to ‘1’
TEMPERATURE MONITOR CIRCUITS ARE
ACTIVE (DEFAULT).
VOLTAGE AND TEMPERATURE
MONITORING CIRCUITS ARE AWAITING
EXTERNAL CONTROL.
WKUP goes above or below
threshold (edge triggered).
Or, SLEEP bit is set to ‘0’
BIASING IS OFF
LOGIC AND REGISTERS ARE POWERED
BY VCELL1
VOLTAGE AND TEMPERATURE
MONITORING CIRCUITS ARE OFF.
I2C COMMUNICATION IS ACTIVE (IF
VCELL1 VOLTAGE IS HIGH ENOUGH TO
OPERATE WITH THE EXTERNAL DEVICE.)
FIGURE 11. DEVICE OPERATION STATE MACHINE
16
FN6719.0
July 3, 2008
ISL94201
Applications Circuits
The following application circuits are ideas to consider when
developing a battery pack implementation. There are many
more ways that the pack can be designed.
Also refer to the ISL9208 or ISL9216 application guide for
additional circuit design guidelines.
P+
ISL94201
0.1µ
1.8M
500
VC7/VCC
1.2M
VCELL6
SCL
VCELL5
SDA
WKUP
VCELL4
RGC
RGO
1µF
VCELL3
TEMP3V
THERM
TEMPI
µF
RESET
VCELL2
SCL
SDA
4.7µF
VCELL1
AO
VCC
GP
I/O
I/O
A/D INPUT
OPTIONAL
LEDS/
RESISTORS
100
CHRG
MINIMIZE LENGTH
MAXIMIZE GAUGE
VSS
200k
P-
FIGURE 12. 7-CELL APPLICATION CIRCUIT INTEGRATED CHARGE/DISCHARGE
17
FN6719.0
July 3, 2008
ISL94201
ISL94201
0.1µF
825k
SW
VC7/VCC
10V
500
VCELL6
SCL
VCELL5
SDA
WKUP
VCELL4
RGC
RGO
VCELL3
TEMP3V
THERM
TEMPI
1µF
µF
VCC
RESET
VCELL2
SCL
SDA
4.7µF
VCELL1
AO
GP
I/O
I/O
OPTIONAL
LEDS
RESISTORS
100
A/D INPUT
CHRG
MINIMIZE LENGTH
MAXIMIZE GAUGE
VSS
P-
FIGURE 13. 7-CELL APPLICATION CIRCUIT WITH SWITCH WAKE-UP
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
18
FN6719.0
July 3, 2008
ISL94201
Package Outline Drawing
L24.4x4D
24 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 10/06
4.00
4X 2.5
A
20X 0.50
B
PIN 1
INDEX AREA
PIN #1 CORNER
(C 0 . 25)
24
19
1
18
4.00
2 . 50 ± 0 . 15
13
0.15
(4X)
12
7
0.10 M C A B
0 . 07
24X 0 . 23 +- 0
. 05 4
24X 0 . 4 ± 0 . 1
TOP VIEW
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
C
0 . 90 ± 0 . 1
BASE PLANE
( 3 . 8 TYP )
SEATING PLANE
0.08 C
SIDE VIEW
(
2 . 50 )
( 20X 0 . 5 )
C
0 . 2 REF
5
( 24X 0 . 25 )
0 . 00 MIN.
0 . 05 MAX.
( 24X 0 . 6 )
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
19
FN6719.0
July 3, 2008
Similar pages