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DATASHEET
SMBus Interfaced Battery Charger with Internal FETs
ISL95871C
Features
The ISL95871C is a highly integrated Lithium-ion battery charger
controller, programmable over the System Management Bus
(SMBus) with internal switching FETs. High efficiency is achieved
with a DC/DC synchronous-rectifier buck converter, equipped with
diode emulation for enhanced light load efficiency and system bus
boosting prevention. The ISL95871C charges one to four
Lithium-ion series cells, and delivers up to 8A charge current.
Integrated MOSFETs and bootstrap diode result in fewer
components and smaller implementation area. Low offset
current-sense amplifiers provide high accuracy with 10m sense
resistors. The ISL95871C provides 0.5% battery voltage accuracy.
• Internal Synchronous Buck Output Stage Power FETs
The ISL95871C also provides a digital output that indicates the
presence of the AC-adapter as well as an analog output which
indicates the adapter current within 4% accuracy.
• 0.5% Battery Voltage Accuracy
• 3% Adapter Current Limit Accuracy
• 3% Charge Current Accuracy
• SMBus 2-Wire Serial Interface
• Battery Short Circuit Protection
• Fast Response for Pulse-Charging
• Fast System-Load Transient Response
• Monitor Outputs
- Adapter Current (3% Accuracy)
- AC-Adapter Detection
• 11-Bit Battery Voltage Setting
Applications
• 6 Bit Charge Current/Adapter Current Setting
• Notebook Computers
• 8A Maximum Battery Charger Current
• Tablet PCs
• 11A Maximum Adapter Current
• Portable Equipment with Rechargeable Batteries
• +8V to +22V Adapter Voltage Range
• Pb-Free (RoHS Compliant)
Related Literature
• See AN1590, ISL95871C Evaluation Board User Guide
100
9
95
8
85
2 CELL
80
3 CELL
CHARGE CURRENT (A)
EFFICIENCY (%)
90
4 CELL
75
1 CELL
70
65
60
7
1 CELL
6
4 CELL
5
3 CELL
4
3
2 CELL
2
1
0
1
2
5
3
4
6
CHARGE CURRENT (A)
7
8
FIGURE 1. EFFICIENCY vs CHARGE CURRENT AND BATTERY
VOLTAGE (EFFICIENCY DCIN = 20V)
June 8, 2011
FN6856.2
1
0
0
25
50
75
100
AMBIENT TEMPERATURE (°C)
125
150
FIGURE 2. DERATING CURVE WITH NATURAL AIR FLOW
(MEASURED ON 10cm x 10cm EVALUATION BOARD)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2010, 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL95871C
Pin Configuration
ICM
NC
VCOMP
ICOMP
VREF
49
SCL
VDDSMB
50
SDA
NC
ISL95871C
(50 LD 5x7 QFN)
TOP VIEW
48
47
46
45
44
43
42
AGND 1
41 AGND
ACOK 2
40 ACIN
39 NC
VFB 3
AGND
51
CSON 4
38 CSIP
CSOP 5
37 AGND
DCIN 6
36 CSIN
NC 7
35 VDD
34 BOOT
AGND 8
VDDP 9
33 UGATE
DCIN3
UGATE
49
53
VDDP
52
VDDP 10
32 UGATE
31 VIN
PHASE 11
PGND 12
30 VIN
PHASE
54
PHASE7
PGND 13
VIN
55
29 VIN
PGND 14
28 VIN
PGND 15
27 VIN
26 VIN
17
18
19
20
21
22
23
24
25
PHASE
PHASE
PHASE
PHASE
NC
VIN
VIN
VIN
VIN
PGND 16
Pin Descriptions
PIN NUMBER
SYMBOL
DESCRIPTION
1, 8, 37, 51
AGND
Analog Ground. Connect directly to the backside paddle. Connect to PGND and the system ground plane under
the IC.
2
ACOK
AC-Adapter Detection Output. This open drain output is high impedance when ACIN is greater than 3.2V. The
ACOK output remains low when the ISL95871C is powered down. Connect a 10k pull-up resistor from ACOK
to VDDSMB. Range: 0V to 5V.
3
VFB
4
CSON
Charge Current-Sense Negative Input. Range: zero to battery voltage.
5
CSOP
Charge Current-Sense Positive Input. Range: zero to battery voltage.
6
DCIN
Charger Bias Supply Input. Bypass DCIN with a 0.1µF capacitor to AGND. Range: zero to adapter voltage.
7, 21, 39, 45, 50
NC
9, 10, 52
VDDP
Linear Regulator Output. VDDP is the output of the 5.2V linear regulator supplied from DCIN. VDDP also
directly supplies the LFET gate driver and the BOOT strap diode. Bypass with a 1µF ceramic capacitor from
VDDP to PGND. Range: zero to 5.3V.
11, 17, 18, 19, 20, 54
PHASE
Output inductor connection. Connected to the source of the internal high-side N-Channel MOSFET Source and
low-side N-Channel MOSFET Drain. Range: 1 diode drop below ground to 1 diode drop above adapter voltage.
12, 13, 14, 15, 16
PGND
Power Ground. Connect PGND to the source of the low side MOSFET and to the system ground plane.
Battery Voltage Remote Sense. Connect to the battery pack positive terminal.
No Connection. Pins 7, 21, 39, 45 and 50 are not connected.
2
FN6856.2
June 8, 2011
ISL95871C
Pin Descriptions (Continued)
PIN NUMBER
SYMBOL
DESCRIPTION
22, 23, 24, 25, 26, 27,
28, 29, 30, 55
VIN
Power input to the switching FETs connected to the drain of internal upper FET. A very low ESR capacitor should
be place from the VIN pins to the PGND pins. Range: Min battery voltage to adapter voltage.
32, 33, 53
UGATE
Upper Gate of the internal power FET. A 4700pF cap must be placed between UGATE and PHASE. Range: 1
diode drop below ground to 5.3V above adapter voltage.
34
BOOT
High-Side Power MOSFET Driver Power-Supply Connection. Connect a 0.1µF capacitor from BOOT to PHASE.
Range: 1 diode drop below ground to 5.3V above adapter voltage.
35
VDD
Power input for internal analog circuits. Connect a 4.7 resistor from VDD to VDDP and a 1µF ceramic
capacitor from VDD to AGND. Range: 0V to 5.3V.
36
CSIN
Input Current-Sense Negative Input. Range: battery voltage to adapter voltage.
38
CSIP
Input Current-Sense Positive Input. Range: battery voltage to adapter voltage.
40
ACIN
AC-Adapter Detection Input. Connect to a resistor divider from the AC-adapter output. Output switching is
disabled when ACIN is below it threshold. The divider should be designed to pull ACIN above its threshold when
the adapter voltage is above battery voltage. Range: 0V to 5V.
42
VREF
3.2V internal reference voltage. Place a 0.1µF ceramic capacitor from VREF to AGND pin close to the IC.
43
ICOMP
Compensation Point for the charging current and adapter current regulation Loop. Connect 0.01µF to AGND.
See the “Charge Current Control Loop” on page 21 for details of selecting the ICOMP capacitor. Range: 0V to
5.3V.
44
VCOMP
Compensation Point for the voltage regulation loop. Connect a resistor in series with a small ceramic capacitor
to AGND, typically 4.7k in series with 0.01µF. See “Voltage Control Loop” on page 22 for details on selecting
VCOMP components. Range: 0V to 5V.
46
ICM
Input Current Monitor Output. ICM voltage equals 20 x (VCSIP - VCSIN). Range: 0V to 5V.
47
SDA
SMBus Data I/O. Open-drain Output. Connect an external pull-up resistor according to SMBus specifications.
Range: 0V to 5V.
48
SCL
SMBus Clock Input. Connect an external pull-up resistor according to SMBus specifications. Range: 0V to 5V.
49
VDDSMB
51, 52, 53, 54, 55
SMBus interface Supply Voltage Input. Bypass with a 0.1µF capacitor to AGND. Range: 0V to 5V.
Back Side Paddles 5 terminals on the back side of the package provide additional electrical and thermal connection to
ISL95871C AGND, VDDP, UGATE, PHASE and VIN. PHASE and VIN paddles are the lowest thermal resistance
from the switching MOSFETs and should relatively large areas of copper to have low thermal resistance from
the FETs to the PCB and the ambient air. The AGND paddle is the lowest thermal resistance from the control
IC and should be connected to a relatively large area of copper to have low thermal resistance from the FETs
to the PCB and the ambient air.
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
ISL95871CHRZ
ISL 95871CHRZ
TEMP RANGE
(°C)
-10 to +100
PACKAGE
(Pb-Free)
50 Ld 5x7 QFN
PKG.
DWG. #
L50.5x7
NOTES:
1. Add “-T*” suffix for Tape and Reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate
plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL95871C. For more information on MSL please see techbrief TB363.
3
FN6856.2
June 8, 2011
ISL95871C
11
VDDSMB
6
SDA
SMBUS
SCL
DCIN
DACV
DACI
6
VDDP REG
VDDP
REFERENCE
VREF
DACS
EN
VDDP
ICM
CSIP
-
CSIN
+
VREF
20X
DACS
ACIN
+
ACOK
-
20X
CSON
-
GMS
+
MIN
CURRENT
BUFFER
-
CSOP
DACI
ACOK
+
VDDP
BOOT
EN
GMI
VIN
+
ICOMP
FEED
FORWARD
PULSE
WIDTH
MODULATOR VDDP
MIN
VOLTAGE
BUFFER
VCOMP
UGATE
PHASE
500k
VFB
DACV
100k
PGND
GMV
+
GND
FIGURE 3. FUNCTIONAL BLOCK DIAGRAM
AC-ADAPTER
TO SYSTEM
RS1
CSIP
CSIN
VIN
ACIN
DCIN
AGND
IN-RUSH
LIMIT
CIRCUIT
PHASE
RS2
ISL95871C
BOOT
SMART
BATTERY
UGATE
CSOP
CSON
VFB
AGND
ICOMP
VCOMP
VDDP
CICOMP
PGND
VDD
AGND
CVCOMP
ACOK
ICM
SDA
SCL
VDDSMB
AGND
SDA
SCL
HOST
VREF
RVCOMP
PGND
PGND
FIGURE 4. TYPICAL APPLICATION CIRCUIT
4
FN6856.2
June 8, 2011
ISL95871C
Table of Contents
Absolute Maximum Ratings.............................................................. 6
Thermal Information .......................................................................... 6
Recommended Operating Conditions ............................................. 6
SMBus Timing Specification ............................................................. 8
Typical Operating Performance.........................................................9
CSOP, CSON, CSIP and CSIN Pins ............................................
DCIN Pin.......................................................................................
Copper Size for the Phase Node ..............................................
Identify the Power and Signal Ground ....................................
Clamping Capacitor for Switching MOSFET............................
24
24
24
24
24
Revision History ................................................................................ 25
Products ............................................................................................. 25
Package Outline Drawing ............................................................... 26
Theory of Operation ......................................................................... 12
Introduction ................................................................................. 12
PWM Control................................................................................ 12
AC-Adapter Detection................................................................. 12
Current Measurement................................................................ 12
VDDP Regulator .......................................................................... 12
VDDSMB Supply .......................................................................... 12
Short Circuit Protection and 0V Battery Charging ................. 12
Undervoltage Detect and Battery Trickle Charging ............... 12
Over-Temperature Protection ................................................... 12
Overvoltage Protection .............................................................. 12
The System Management Bus.................................................. 13
General SMBus Architecture..................................................... 13
Data Validity ................................................................................ 13
START and STOP Conditions............................................................. 13
Acknowledge........................................................................................ 13
SMBus Transactions........................................................................... 14
Byte Format ................................................................................. 14
ISL95871C and SMBus.............................................................. 14
Battery Charger Registers ......................................................... 14
Enabling and Disabling Charging ............................................. 14
Setting Charge Voltage .............................................................. 15
Setting Charge Current .............................................................. 17
Setting Input-Current Limit........................................................ 18
Charger Timeout ......................................................................... 19
ISL95871C Data Byte Order ..................................................... 19
Writing to the Internal Registers .............................................. 19
Reading from the Internal Registers ....................................... 19
Application Information................................................................... 19
Inductor Selection....................................................................... 19
Output Capacitor Selection ....................................................... 19
Snubber Design........................................................................... 20
Input Capacitor Selection .......................................................... 20
Loop Compensation Design ...................................................... 20
Transconductance Amplifiers GMV, GMI and GMS................ 20
PWM Gain Fm ............................................................................. 20
Charge Current Control Loop .................................................... 21
Adapter Current Limit Control Loop......................................... 21
Voltage Control Loop.................................................................. 22
Output LC Filter Transfer Functions ......................................... 22
Compensation Break Frequency Equations ........................... 23
PCB Layout Considerations............................................................. 23
Power and Signal Layers Placement on the PCB ........................ 23
Component Placement.............................................................. 23
Signal Ground and Power Ground Connection....................... 23
AGND and VDD Pin ..................................................................... 24
PGND Pins.................................................................................... 24
PHASE Pins.................................................................................. 24
BOOT Pin ...................................................................................... 24
5
FN6856.2
June 8, 2011
ISL95871C
Absolute Maximum Ratings
Thermal Information
DCIN, CSIP, CSIN, CSOP, CSON, VIN to PGND . . . . . . . . . . . . . . . -0.3V to +28V
DCIN, CSIP, CSIN, VIN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +28V
CSOP, CSON, VFB to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +28V
CSIP-CSIN, CSOP-CSON, PGND-AGND . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
PHASE-PGND and VIN-PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . -6V to +28V
UGATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PHASE - 0.3V to BOOT + 0.3V
BOOT to PGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V
BOOT to PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V
ICOMP, VCOMP, VREF, to AGND. . . . . . . . . . . . . . . . . . . .-0.3V to VDD + 0.3V
VDDSMB, SCL, SDA, ACIN, ACOK to AGND . . . . . . . . . . . . . . . . -0.3V to +6V
VDD to AGND, VDDP to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
50 Ld 5x7 QFN Package (Notes 4, 5) . . . . . .
32
2
Operating Junction Temperature Range . . . . . . . . . . . . . .-10°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Ambient Temperature (see Figure 11). . . . . . . . . . . . . . . .-10°C to +100°C
Supply Voltage DCIN and VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V to 22V
VDDSMB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
VIN = DCIN = VCSIP = VCSIN = 19V, VCSOP = VCSON = 12V, VDDP = 5.1V, VBOOT - VPHASE = 5V,
AGND = PGND = 0V, VDDSMB = 5V. All typical specifications TA = +25°C. Boldface limits apply over the junction temperature range, -10°C to
+125°C.
PARAMETER
CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6) UNITS
16.716
16.8
16.884
V
0.5
%
CHARGE VOLTAGE REGULATION
Battery Full Charge Voltage and Accuracy
ChargeVoltage = 0x41A0
-0.5
ChargeVoltage = 0x3130
12.529 12.592 12.655
-0.5
ChargeVoltage = 0x20D0
8.358
8.4
-0.5
ChargeVoltage = 0x1060
4.163
4.192
-0.7
Battery Trickle Charge Threshold
VFB rising
V
0.5
%
8.442
V
0.5
%
4.221
V
0.7
%
2.55
2.7
2.85
V
100
200
400
mV
78.22
80.64
83.06
mV
RS2 = 10m (see Figure 4)
ChargeCurrent = 0x1F80
CSON from 0V to 19.2V
7.822
8.064
8.306
A
3
%
RS2 = 10m (see Figure 4)
ChargeCurrent = 0x0F80
CSON from 0V to 19.2V
3.849
4.087
A
3
%
RS2 = 10m (see Figure 4)
ChargeCurrent = 0x0080
CSON from 0V to 19.2V
64
220
mA
Based on charge current = 128mA and 8.064A
-1.6
1.4
%
Battery Trickle Charge Threshold Hysteresis
CHARGE CURRENT REGULATION
CSOP to CSON Full-Scale Current-Sense Voltage
Charge Current and Accuracy
Charge Current Gain Error
6
-3
3.968
-3
128
FN6856.2
June 8, 2011
ISL95871C
Electrical Specifications
VIN = DCIN = VCSIP = VCSIN = 19V, VCSOP = VCSON = 12V, VDDP = 5.1V, VBOOT - VPHASE = 5V,
AGND = PGND = 0V, VDDSMB = 5V. All typical specifications TA = +25°C. Boldface limits apply over the junction temperature range, -10°C to
+125°C. (Continued)
PARAMETER
CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6) UNITS
Adapter present, not charging,
ICSOP + ICSON + IPHASE + IFB
VPHASE = VCSON = VCSOP = VDCIN = 19V, VACIN = 5V
0.1
2
µA
Adapter Absent
ICSOP + ICSON + IPHASE + ICSIP + ICSIN + IFB
VPHASE = VCSON = VCSOP = 19V, VDCIN = 0V
0.1
2
µA
Adapter Quiescent Current
IDCIN + ICSIP + ICSIN
Vadapter = 8V to 22V
2.5
5
mA
VIN Leakage Current
PHASE = 0V, VIN = 22V
0.3
1.5
µA
110.08
113.3
mV
Battery Quiescent Current
INPUT CURRENT REGULATION
CSIP to CSIN Full-Scale Current-Sense Voltage
VCSIP = 19V
Input Current Accuracy
RS1 = 10m (see Figure 4)
Adapter Current = 11008mA or 3584mA
-3
3
%
RS1 = 10m (see Figure 4)
Adapter Current = 2048mA
-5
5
%
Based on InputCurrent = 1024mA and 11008mA
-2
2
%
-1
1
mV
Input Current Limit Gain Error
Input Current Limit Offset
ICM Gain
VCSIP-VCSIN = 110mV
ICM Accuracy
VCSIP-VCSIN = 110mV
106.7
19.9
-2.5
2.5
%
VCSIP-VCSIN = 55mV or 35mV
-4
4
%
VCSIP-VCSIN = 20mV
-8
8
%
10
mV
5.1
5.23
V
35
100
mV
VCSIP-VCSIN = 0.1V,
ICM load from zero to 500µA
ICM Load regulation
V/V
SUPPLY AND LINEAR REGULATOR
VDDP Output Voltage
8.0V < VDCIN < 22V, no load
VDDP Load Regulation
0 < IVDDP < 30mA
4.95
VDDSMB UVLO Rising
2.3
2.5
2.61
V
VDDSMB UVLO Falling
2.2
2.4
2.5
V
VDDSMB UVLO Hysteresis
100
mV
VDD UVLO Rising
4.25
4.5
4.65
V
VDD UVLO Hysteresis
150
280
400
mV
20
27
µA
3.168
3.2
3.232
V
2
8
VDDSMB Quiescent Current
VDDP = SCL = SDA = 5.5V
VOLTAGE REFERENCE
VREF Output Voltage
0 < IVREF < 300µA
ACOK
ACOK Sink Current
VACOK = 0.4V, ACIN = 1.5V
ACOK Leakage Current
VACOK = 5.5V, ACIN = 2.5V
mA
1
µA
ACIN
ACIN Rising Threshold
ACIN Threshold Hysteresis
ACIN Input Leakage Current
ACIN = 3.7V
7
3.15
3.2
3.28
V
40
60
90
mV
1
µA
FN6856.2
June 8, 2011
ISL95871C
Electrical Specifications
VIN = DCIN = VCSIP = VCSIN = 19V, VCSOP = VCSON = 12V, VDDP = 5.1V, VBOOT - VPHASE = 5V,
AGND = PGND = 0V, VDDSMB = 5V. All typical specifications TA = +25°C. Boldface limits apply over the junction temperature range, -10°C to
+125°C. (Continued)
PARAMETER
CONDITIONS
MIN
(Note 6)
TYP
330
400
MAX
(Note 6) UNITS
SWITCHING REGULATOR
Frequency
Dead Time
440
50
kHz
ns
ERROR AMPLIFIERS
GMV Amplifier Transconductance
200
250
300
µA/V
GMI Amplifier Transconductance
40
50
60
µA/V
GMS Amplifier Transconductance
40
50
60
µA/V
GMI/GMS Saturation Current
15
20
25
µA
GMV Saturation Current
10
17
30
µA
200
300
400
mV
0.8
V
0.25V < VICOMP, VVCOMP < 3.5V
ICOMP, VCOMP Clamp Voltage
LOGIC LEVELS
SDA/SCL Input Low Voltage
VDDSMB = 2.7V to 5.5V
SDA/SCL Input High Voltage
VDDSMB = 2.7V to 5.5V
SDA/SCL Input Bias Current
VDDSMB = 2.7V to 5.5V
SDA, Output Sink Current
VSDA = 0.4V
2
V
1
7
15
µA
mA
NOTE:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
SMBus Timing Specification
VDDSMB = 2.7V to 5.5V
PARAMETERS
SMBus Frequency
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
100
kHz
FSMB
10
tBUF
4.7
µs
Start Condition Hold Time from SCL
THD:STA
4
µs
Start Condition Setup Time from SCL
TSU:STA
4.7
µs
Stop Condition Setup Time from SCL
TSU:STO
4
µs
SDA Hold Time from SCL
THD:DAT
300
ns
SDA Setup Time from SCL
TSU:DAT
250
ns
SCL Low Timeout (Note 7)
tTIMEOUT
22
SCL Low Period
tLOW
4.7
µs
SCL High Period
tHIGH
4
µs
Bus Free Time
Maximum Charging Period Without a SMBus Write to
ChargeVoltage or ChargeCurrent Register
140
25
175
30
220
ms
s
NOTES:
7. If SCL is low for longer than the specified time, the charger is disabled.
8. Limits established by characterization and are not production tested.
8
FN6856.2
June 8, 2011
ISL95871C
Typical Operating Performance DCIN = 19V, 3S2P Li-Battery, TA = +25C, unless otherwise noted.
5.15
3.0
12.5
5.05
5.00
4.95
2.5
12.0
BATTERY VOLTAGE (V)
2.0
11.5
1.5
11.0
1.0
CHARGE CURRENT
10.5
4.90
0
10
20
30
40
50
60
70
80
VDDP LOAD CURRENT (mA)
90
100
CHARGE CURRENT (A)
BATTERY VOLTAGE (V)
5.10
VDDP (V)
3.5
13.0
0.5
10.0
0
20
40
60
80
100
120
0.0
160
140
TIME (MINUTES)
FIGURE 6. TYPICAL CHARGING VOLTAGE AND CURRENT
FIGURE 5. VDDP LOAD REGULATION
100
15
95
90
EFFICIENCY (%)
ICM ACCURACY(%)
10
5
0
-5
1 CELL
60
0
1
2
3
4
6
5
ADAPTER CURRENT (A)
7
0
8
1
2
3
4
5
6
7
8
CHARGE CURRENT (A)
FIGURE 8. EFFICIENCY vs CHARGE CURRENT AND BATTERY
VOLTAGE (EFFICIENCY DCIN = 20V)
4
0.5
3
CHARGE VOLTAGE ACCURACY (%)
CHARGE CURRENT ACCURACY(%)
75
65
FIGURE 7. ICM ACCURACY vs AC-ADAPTER CURRENT
CHARGE CURRENT = 2.048A
2
1
CHARGE CURRENT = 4.096A
0
CHARGE CURRENT = 8.064A
-1
CHARGE CURRENT = 6.016A
-2
-3
-4
4 CELL
3 CELL
2 CELL
80
70
-10
-15
85
2
4
6
8
10
12
14
BATTERY VOLTAGE (V)
FIGURE 9. CHARGE CURRENT ACCURACY
9
16
18
0.4
0.3
0.2
0.1
2 CELL
0
-0.1
3 CELL
-0.2
1 CELL
4 CELL
-0.3
-0.4
-0.5
0
1
2
3
4
5
CHARGE CURRENT (A)
6
7
8
FIGURE 10. CHARGE VOLTAGE ACCURACY
FN6856.2
June 8, 2011
ISL95871C
9
9
8
8
7
CHARGE CURRENT (A)
CHARGE CURRENT (A)
Typical Operating Performance DCIN = 19V, 3S2P Li-Battery, TA = +25C, unless otherwise noted. (Continued)
1 CELL
6
4 CELL
5
4
3 CELL
3
2 CELL
2
7
6
4
0
0
50
75
100
AMBIENT TEMPERATURE (°C)
125
150
FIGURE 11. DERATING CURVE WITH NATURAL AIR FLOW
(MEASURED ON 10cm x 10cm EVALUATION BOARD)
1 CELL
2
1
25
3 CELL
3
1
0
4 CELL
5
2 CELL
0
25
50
75
100
AMBIENT TEMPERATURE (°C)
125
150
FIGURE 12. DERATING CURVE WITH 200LFM AIR FLOW
(MEASURED ON 10cm x 10cm EVALUATION BOARD)
PHASE
PHASE
UGATE-PHASE
UGATE-PHASE
INDUCTOR CURRENT
INDUCTOR CURRENT
FIGURE 13. SWITCHING WAVEFORMS IN DIODE EMULATION MODE
VCOMP
ICOMP
SDA
FIGURE 14. SWITCHING WAVEFORMS IN CC MODE
VCOMP
ICOMP
SDA
CHARGE CURRENT
CHARGE CURRENT
FIGURE 15. CHARGE ENABLE: WRITE 1F80 (8.064A) TO
CHARGECURRENT REGISTER
10
FIGURE 16. CHARGE DISABLE: WRITE 0000 (0A) TO
CHARGECURRENT REGISTER
FN6856.2
June 8, 2011
ISL95871C
Typical Operating Performance DCIN = 19V, 3S2P Li-Battery, TA = +25C, unless otherwise noted. (Continued)
VCOMP
ICOMP
ICOMP
VCOMP
CSON
CSON
CHARGE CURRENT
CHARGE CURRENT
FIGURE 18. BATTERY INSERTION
FIGURE 17. BATTERY REMOVAL
ADAPTER CURRENT
SYSTEM CURRENT
CHARGE CURRENT
CSON VOLTAGE
FIGURE 19. SYSTEM LOAD TRANSIENT RESPONSE
11
FN6856.2
June 8, 2011
ISL95871C
Theory of Operation
AC-Adapter Detection
Introduction
Connect the AC-adapter voltage through a resistor divider to ACIN
to detect when AC power is available, as shown in Figure 4. ACOK
is an open-drain output and is active low when ACIN is less than
ACIN falling threshold, and high when ACIN is above ACIN rising
threshold. The ACIN rising threshold is 3.2V (typ) with 57mV
hysteresis.
The ISL95871C includes all of the functions necessary to charge
1- to 4-cell Li-ion and Li-polymer batteries. A high efficiency
synchronous buck converter is used to control the charging
voltage up to 19.2V and charging current up to 8A. The
ISL95871C also has input current limiting up to 11A. The Input
current limit, charge current limit and charge voltage limit are set
by internal registers written with SMBus. The ISL95871C “Typical
Application Circuit” is shown in Figure 4.
The ISL95871C charges the battery with constant charge current,
set by the ChargeCurrent register, until the battery voltage rises to
a voltage set by the ChargeVoltage register. The charger will then
operate at a constant voltage. The adapter current is monitored
and if the adapter current rises to the limit set by the InputCurrent
register, battery charge current is reduced so the charger does not
reduce the adapter current available to the system.
The ISL95871C features a voltage regulation loop (VCOMP) and 2
current regulation loops (ICOMP). The VCOMP voltage regulation
loop monitors VFB to limit the battery charge voltage. The ICOMP
current regulation loop limits the battery charging current
delivered to the battery to ensure that it never exceeds the
current set by the ChargeCurrent register. The ICOMP current
regulation loop also limits the input current drawn from the
AC-adapter to ensure that it never exceeds the limit set by the
InputCurrent register, and to prevent a system crash and
AC-adapter overload.
PWM Control
The ISL95871C employs a fixed frequency PWM control
architecture with a feed-forward function. The feed-forward
function maintains a constant modulator gain of 11 to achieve fast
line regulation as the input voltage changes.
The duty cycle of the buck regulator is controlled by the lower of the
voltages on ICOMP and VCOMP. The voltage on ICOMP and VCOMP
are inputs to a Lower Voltage Buffer (LVB) whose output is the lower
of the 2 inputs. The output of the LVB is compared to an internal
400kHz ramp to produce the Pulse Width Modulated signal that
controls the UFET and LFET gate drivers. An internal clamp holds the
higher of the 2 voltages (0.3V) above the lower voltage. This speeds
the transition from voltage loop control to current loop control or vice
versa.
Current Measurement
Use ICM to monitor the adapter current being sensed across CSIP
and CSIN. The output voltage range is 0V to 2.5V. The voltage of
ICM is proportional to the voltage drop across CSIP and CSIN, and
is given by Equation 1:
V ICM = 20  I INPUT  R S1 = 20   V CSIP – V CSIN 
(EQ. 1)
where IINPUT is the DC current drawn from the AC-adapter. It is
recommended to have an RC filter at the ICM output for
minimizing the switching noise.
VDDP Regulator
VDDP provides a 5.2V supply voltage from the internal LDO
regulator from DCIN and can deliver up to 30mA of continuous
current. The MOSFET drivers are powered by VDDP. VDDP also
supplies power to VDD through a low pass filter as shown in
Figure 4 on page 4. Bypass VDDP and VDD with a 1µF capacitor.
VDDSMB Supply
The VDDSMB input provides power to the SMBus interface. Connect
VDDSMB to VDD, or apply an external supply to VDDSMB to keep the
SMBus interface active while the supply to DCIN is removed. When
VDDSMB is biased, the internal registers are maintained. Bypass
VDDSMB to AGND with a 0.1µF or greater ceramic capacitor.
Short Circuit Protection and 0V Battery
Charging
Since the battery charger will regulate the charge current to the
limit set by the ChargeCurrent register, it automatically has short
circuit protection and is able to provide the charge current to
wake up an extremely discharged battery. Undervoltage trickle
charge folds back current if there is a short circuit on the output.
Undervoltage Detect and Battery Trickle
Charging
The ISL95871C can operate up to 99.6% duty cycle if the input
voltage drops close to or below the battery charge voltage (drop
out mode). The DC/DC converter has a timer to prevent the
frequency from dropping into the audible frequency range.
If the voltage at VFB falls below 2.5V, ISL95871C reduces the
charge current limit to 128mA to trickle charge the battery.
When the voltage rises above 2.7V, the charge current reverts to
the programmed value in the ChargeCurrent register.
To prevent boosting of the system bus voltage, the battery
charger drives the lower FET in a way that prevents negative
inductor current.
Over-Temperature Protection
An adaptive gate drive scheme is used to control the dead time
between two switches. The dead time control circuit monitors the
LFET gate driver output and prevents the upper side MOSFET
from turning on until 20ns after the LFET gate driver falls below
1V VGS, preventing cross-conduction and shoot-through. The
same occurs for LFET turn on.
12
If the die temperature exceeds +150°C, it stops charging. Once
the die temperature drops below +125°C, charging will start-up
again.
Overvoltage Protection
ISL95871C has an Overvoltage Protection circuit that limits the
output voltage when the battery is removed or disconnected by a
pulse charging circuit. If CSON exceeds the output voltage set
FN6856.2
June 8, 2011
ISL95871C
point in the charge voltage register by more than 300mV, an
internal comparator pulls VCOMP down and turns off both upper
and lower FETs of the buck as in Figure 20. There is a delay of
approximately 1µs between VOUT exceeding the OVP trip point
and pulling VCOMP, LGATE and UGATE low. After UGATE and
LGATE are turned OFF, inductor current continues to flow through
the body diode of the lower FET and VOUT continues to rise until
inductor current reaches zero.
VOUT
INDUCTOR CURRENT
Data Validity
The data on the SDA line must be stable during the HIGH period
of the SCL, unless generating a START or STOP condition. The
HIGH or LOW state of the data line can only change when the
clock signal on the SCL line is LOW. Refer to Figure 22.
SDA
SCL
DATA LINE CHANGE
STABLE
OF DATA
DATA VALID ALLOWED
FIGURE 22. DATA VALIDITY
START and STOP Conditions
As shown in Figure 23, START condition is a HIGH-to-LOW transition
of the SDA line while SCL is HIGH.
The STOP condition is a LOW-to-HIGH transition on the SDA line
while SCL is HIGH. A STOP condition must be sent before each
START condition.
PHASE
BATTERY CURRENT
SDA
FIGURE 20. OVERVOLTAGE PROTECTION IN ISL88731C
SCL
The System Management Bus
The System Management Bus (SMBus) is a 2-wire bus that
supports bidirectional communications. The protocol is described
briefly here. More detail is available from www.smbus.org.
General SMBus Architecture
SMBUS SLAVE
INPUT
SCL
CONTROL
CPU
SDA
STATE
SCL
MACHINE,
OUTPUT CONTROL
INPUT
INPUT
REGISTERS,
MEMORY,
SDA
ETC
OUTPUT CONTROL
OUTPUT
P
STOP
CONDITION
FIGURE 23. START AND STOP WAVEFORMS
Acknowledge
VDDSMB
SMBUS MASTER
S
START
CONDITION
INPUT
Each address and data transmission uses 9-clock pulses. The ninth
pulse is the acknowledge bit (ACK). After the start condition, the
master sends 7-slave address bits and a R/W bit during the next 8clock pulses. During the ninth clock pulse, the device that recognizes
its own address holds the data line low to acknowledge. The
acknowledge bit is also used by both the master and the slave to
acknowledge receipt of register addresses and data (see Figure 24).
SCL
CONTROL OUTPUT
1
SMBUS SLAVE
INPUT
SCL
OUTPUT CONTROL
SDA
SCL
INPUT
TO OTHER
SLAVE DEVICES
STATE
MACHINE,
SDA
9
MSB
MEMORY,
ETC
8
SDA
REGISTERS,
OUTPUT CONTROL
2
START
ACKNOWLEDGE
FROM SLAVE
FIGURE 24. ACKNOWLEDGE ON THE I2C BUS
FIGURE 21.
13
FN6856.2
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ISL95871C
SMBus Transactions
Read address = 0b00010011 (0X13) and
All transactions start with a control byte sent from the SMBus
master device. The control byte begins with a Start condition,
followed by 7-bits of slave address (0001001 for the ISL95871C)
followed by the R/W bit. The R/W bit is 0 for a write or 1 for a read. If
any slave devices on the SMBus bus recognize their address, they
will Acknowledge by pulling the serial data (SDA) line low for the last
clock cycle in the control byte. If no slaves exist at that address or
are not ready to communicate, the data line will be 1, indicating a
Not Acknowledge condition.
Write address = 0b00010010 (0X12).
Once the control byte is sent, and the ISL95871C acknowledges
it, the 2nd byte sent by the master must be a register address
byte such as 0x14 for the ChargeCurrent register. The register
address byte tells the ISL95871C which register the master will
write or read. See Table 1 for details of the registers. Once the
ISL95871C receives a register address byte it responds with an
acknowledge.
Byte Format
Every byte put on the SDA line must be eight bits long and must
be followed by an acknowledge bit. Data is transferred with the
most significant bit first (MSB) and the least significant bit last
(LSB).
ISL95871C and SMBus
The ISL95871C receives control inputs from the SMBus interface.
The serial interface complies with the SMBus protocols as
documented in the System Management Bus Specification V1.1,
which can be downloaded from www.smbus.org. The ISL95871C
uses the SMBus Read-Word and Write-Word protocols (see Figure
25) to communicate with the smart battery. The ISL95871C is an
SMBus slave device and does not initiate communication on the
bus. It responds to the addresses in the following.
In addition, the ISL95871C has two identification (ID) registers: a
16-bit device ID register and a 16-bit manufacturer ID register.
The data (SDA) and clock (SCL) pins have Schmitt-trigger inputs
that can accommodate slow edges. Choose pull-up resistors for
SDA and SCL to achieve rise times according to the SMBus
specifications. The ISL95871C is controlled by the data written to
the registers described in Table 1.
Battery Charger Registers
The ISL95871C supports five battery-charger registers that use
either Write-Word or Read-Word protocols, as summarized in
Table 1. ManufacturerID and DeviceID are “read only” registers
and can be used to identify the ISL95871C. On the ISL95871C,
ManufacturerID always returns 0x0049 (ASCII code for “I” for
Intersil) and DeviceID always returns 0x0001.
Enabling and Disabling Charging
After applying power to ISL95871C, the internal registers contain
their POR values (see Table 1). The POR values for charge current
and charge voltage are 0x0000. These values disable charging.
To enable charging, the ChargeCurrent register must be written
with a number >0x007F and the ChargeVoltage register must be
written with a number >0x000F. Charging can be disabled by
writing 0x0000 to either of these registers.
TABLE 1. BATTERY CHARGER REGISTER SUMMARY
REGISTER
ADDRESS
REGISTER NAME
READ/WRITE
DESCRIPTION
POR STATE
0x14
ChargeCurrent
Read or Write
6-bit Charge Current Setting
0x0000
0x15
ChargeVoltage
Read or Write
11-bit Charge Voltage Setting
0x0000
0x3F
InputCurrent
Read or Write
6-bit Charge Current Setting
0x0080
0xFE
ManufacturerID
Read Only
Manufacturer ID
0x0049
0xFF
DeviceID
Read Only
Device ID
0x0001
14
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June 8, 2011
ISL95871C
Write To A Register
S
SLAVE
ADDR + W
A
REGISTER
ADDR
A
LO BYTE
DATA
A
HI BYTE
DATA
A
A
LO BYTE
DATA
P
Read From A Register
S
SLAVE
ADDR + W
A
REGISTER
ADDR
A
P
S
SLAVE
ADDR + R
A
HI BYTE
DATA
N
S
START
A
ACKNOWLEDGE
DRIVEN BY THE MASTER
P
STOP
N
NO ACKNOWLEDGE
DRIVEN BY ISL95871C
P
FIGURE 25. SMBus/ISL95871C READ AND WRITE PROTOCOL
Setting Charge Voltage
Charge voltage is set by writing a valid 16-bit number to the
ChargeVoltage register. This 16-bit number translates to a
65.535V full-scale voltage. The ISL95871C ignores the first 4
LSBs and uses the next 11 bits to set the voltage DAC. The
charge voltage range of the ISL95871C is 1.024V to 19.200V.
Numbers requesting charge voltage greater than 19.200V result
in a ChargeVoltage of 19.200V. All numbers requesting charge
voltage below 1.024V result in a voltage set point of zero, which
terminates charging. Upon initial power-up or reset, the
ChargeVoltage and ChargeCurrent registers are reset to 0 and
the charger remains shut down until valid numbers are sent to
the ChargeVoltage and ChargeCurrent registers. Use the
Write-Word protocol (see Figure 25) to write to the ChargeVoltage
register. The register address for ChargeVoltage is 0x15. The
16-bit binary number formed by D15–D0 represents the charge
voltage set point in mV. However, the resolution of the
ISL95871C is 16mV because the D0–D3 bits are ignored as
shown in Table 2. The D15 bit is also ignored because it is not
needed to span the 1.024V to 19.2V range. Table 2 shows the
mapping between the charge-voltage set point and the 16-bit
number written to the ChargeVoltage register. The ChargeVoltage
register can be read back to verify its contents.
15
FN6856.2
June 8, 2011
ISL95871C
TABLE 2. CHARGEVOLTAGE (REGISTER 0x15)
BIT
BIT NAME
DESCRIPTION
0
Not used.
1
Not used.
2
Not used.
3
Not used.
4
Charge Voltage, DACV 0
0 = Adds 0mV of charger voltage, 1024mV min.
1 = Adds 16mV of charger voltage.
5
Charge Voltage, DACV 1
0 = Adds 0mV of charger voltage, 1024mV min.
1 = Adds 32mV of charger voltage.
6
Charge Voltage, DACV 2
0 = Adds 0mV of charger voltage, 1024mV min.
1 = Adds 64mV of charger voltage.
7
Charge Voltage, DACV 3
0 = Adds 0mV of charger voltage, 1024mV min.
1 = Adds 128mV of charger voltage.
8
Charge Voltage, DACV 4
0 = Adds 0mV of charger voltage, 1024mV min.
1 = Adds 256mV of charger voltage.
9
Charge Voltage, DACV 5
0 = Adds 0mV of charger voltage, 1024mV min.
1 = Adds 512mV of charger voltage.
10
Charge Voltage, DACV 6
0 = Adds 0mA of charger voltage.
1 = Adds 1024mV of charger voltage.
11
Charge Voltage, DACV 7
0 = Adds 0mV of charger voltage.
1 = Adds 2048mV of charger voltage.
12
Charge Voltage, DACV 8
0 = Adds 0mV of charger voltage.
1 = Adds 4096mV of charger voltage.
13
Charge Voltage, DACV 9
0 = Adds 0mV of charger voltage.
1 = Adds 8192mV of charger voltage.
14
Charge Voltage, DACV 10
0 = Adds 0mV of charger voltage.
1 = Adds 16384mV of charger voltage, 19200mV max.
15
Not used. Normally a 32768mV weight.
16
FN6856.2
June 8, 2011
ISL95871C
Setting Charge Current
ISL95871C has a 16-bit ChargeCurrent register that sets the
battery charging current. ISL95871C controls the charge current
by controlling the CSOP-CSON voltage. The register’s LSB
translates to 10µV at CSON-CSOP. With a 10m charge current
sensing resistor (RS2 in Figure 4 on page 4), the LSB translates to
1mA charge current. The ISL95871C ignores the first 7 LSBs and
uses the next 6 bits to control the current DAC. The
charge-current range of the ISL95871C is 0A to 8.064A (using a
10m current-sense resistor). All numbers requesting charge
current above 8.064A result in a current setting of 8.064A. All
numbers requesting charge current between 0mA to 128mA
result in a current setting of 0mA. The default charge current
setting at Power-On Reset (POR) is 0mA. To stop charging, set
ChargeCurrent to 0. Upon initial power-up, the ChargeVoltage and
ChargeCurrent registers are reset to 0 and the charger is
disabled. To start the charger, write valid numbers to the
ChargeVoltage and ChargeCurrent registers. The ChargeCurrent
register uses the Write-Word protocol (see Figure 25). The
register code for ChargeCurrent is 0x14 (0b00010100). Table 3
shows the mapping between the charge current set point and the
ChargeCurrent number. The ChargeCurrent register can be read
back to verify its contents.
The ISL95871C includes a fault limiter for low battery conditions.
If the battery voltage is less than 2.5V, the charge current is
temporarily set to 128mA. The ChargeCurrent register is
preserved and becomes active again when the battery voltage is
higher than 2.7V. This function effectively provides a foldback
current limit, which protects the charger during short circuit and
overload.
TABLE 3. CHARGECURRENT (REGISTER 0x14) (10m SENSE RESISTOR, RS2)
BIT
BIT NAME
DESCRIPTION
0
Not used.
1
Not used.
2
Not used.
3
Not used.
4
Not used.
5
Not used.
6
Not used.
7
Charge Current, DACI 0
0 = Adds 0mA of charger current.
1 = Adds 128mA of charger current.
8
Charge Current, DACI 1
0 = Adds 0mA of charger current.
1 = Adds 256mA of charger current.
9
Charge Current, DACI 2
0 = Adds 0mA of charger current.
1 = Adds 512mA of charger current.
10
Charge Current, DACI 3
0 = Adds 0mA of charger current.
1 = Adds 1024mA of charger current.
11
Charge Current, DACI 4
0 = Adds 0mA of charger current.
1 = Adds 2048mA of charger current.
12
Charge Current, DACI 5
0 = Adds 0mA of charger current.
1 = Adds 4096mA of charger current, 8064mA max.
13
Not used.
14
Not used.
15
Not used.
17
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June 8, 2011
ISL95871C
Setting Input-Current Limit
The total power from an AC-adapter is the sum of the power
supplied to the system and the power into the charger and battery.
When the input current exceeds the set input current limit, the
ISL95871C decreases the charge current to provide priority to
system load current. As the system load rises, the available charge
current drops linearly to zero. Thereafter, the total input current
can increase to the limit of the AC-adapter.
The internal amplifier compares the differential voltage between
CSIP and CSIN to a scaled voltage set by the InputCurrent
register. The total input current is the sum of the device supply
current, the charger input current, and the system load current.
The total input current can be estimated as shown in Equation 2.
I INPUT = I SYSTEM +   I CHARGE  V BATTERY    V IN    
(EQ. 2)
Where  is the efficiency of the DC/DC converter (typically 85%
to 95%).
The ISL95871C has a 16-bit InputCurrent register that translates
to a 2mA LSB and a 131.071A full scale current using a 10m
current-sense resistor (RS1 in Figure 4 on page 4). Equivalently,
the 16-bit InputCurrent number sets the voltage across CSIP and
CSIN inputs in 20µV per LSB increments. To set the input current
limit use the SMBus to write a 16-bit InputCurrent register using
the data format listed in Table 4. The InputCurrent register uses
the Write-Word protocol (see Figure 25). The register code for
InputCurrent is 0x3F (0b00111111). The InputCurrent register
can be read back to verify its contents.
The ISL95871C ignores the first 7 LSBs and uses the next 6 bits to
control the input-current DAC. The input-current range of the
ISL95871C is from 256mA to 11.004A. All 16-bit numbers
requesting input current above 11.004A result in an input-current
setting of 11.004A. All 16-bit numbers requesting input current
between 0mA to 256mA result in an input-current setting of 0mA.
The default input-current-limit setting at POR is 256mA. When
choosing the current-sense resistor RS1, carefully calculate its
power rating. Take into account variations in the system’s load
current and the overall accuracy of the sense amplifier. Note that
the voltage drop across RS1 contributes additional power loss,
which reduces efficiency. System currents normally fluctuate as
portions of the system are powered up or put to sleep. Without
input current regulation, the input source must be able to deliver
the maximum system current and the maximum charger-input
current. By using the input-current-limit circuit, the output-current
capability of the AC wall adapter can be lowered, reducing system
cost.
TABLE 4. INPUTCURRENT (REGISTER 0x3F) (10m SENSE RESISTOR, RS1)
BIT
BIT NAME
DESCRIPTION
0
Not used.
1
Not used.
2
Not used.
3
Not used.
4
Not used.
5
Not used.
6
Not used.
7
Input Current, DACS 0
0 = Adds 0mA of input current.
1 = Adds 256mA of input current.
8
Input Current, DACS 1
0 = Adds 0mA of input current.
1 = Adds 512mA of input current.
9
Input Current, DACS 2
0 = Adds 0mA of input current.
1 = Adds 1024mA of input current.
10
Input Current, DACS 3
0 = Adds 0mA of input current.
1 = Adds 2048mA of input current.
11
Input Current, DACS 4
0 = Adds 0mA of input current.
1 = Adds 4096mA of input current.
12
Input Current, DACS 5
0 = Adds 0mA of input current.
1 = Adds 8192mA of input current, 11004mA max.
13
Not used.
14
Not used.
15
Not used.
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June 8, 2011
ISL95871C
Charger Timeout
The ISL95871C includes 2 timers to insure the SMBus master is
active and to prevent overcharging the battery. ISL95871C will
terminate charging if the charger has not received a write to the
ChargeVoltage or ChargeCurrent register within 175s or if the
SCL line is low for more than 25ms. If a time-out occurs, either
ChargeVoltage or ChargeCurrent registers must be written to
re-enable charging.
ISL95871C Data Byte Order
Each register in ISL95871C contains 16-bits or 2-, 8-bit bytes. All
data sent on the SMBus is in 8 bit bytes and 2 bytes must be
written or read from each register in ISL95871C. The order in
which these bytes are transmitted appears reversed from the
way they are normally written. The LOW byte is sent first and the
HI byte is sent second. For example, When writing 0x41A0, 0xA0
is written first and 0x41 is sent second.
Writing to the Internal Registers
In order to set the charge current, charge voltage or input current,
valid 16-bit numbers must be written to ISL95871C’s internal
registers via the SMBus.
To write to a register in the ISL95871C, the master sends a
control byte with the R/W bit set to 0, indicating a write. If it
receives an Acknowledge from the ISL95871C it sends a register
address byte setting the register to be written (i.e., 0x14 for the
ChargeCurrent register). The ISL95871C will respond with an
Acknowledge. The master then sends the lower data byte to be
written into the desired register. The ISL95871C will respond with
an Acknowledge. The master then sends the higher data byte to
be written into the desired register. The ISL95871C will respond
with an Acknowledge. The master then issues a Stop condition,
indicating to the ISL95871C that the current transaction is
complete. Once this transaction completes the ISL95871C will
begin operating at the new current or voltage.
The ISL95871C does not support writing more than one register
per transaction.
Reading from the Internal Registers
The ISL95871C has the ability to read from 5 internal registers.
Prior to reading from an internal register, the master must first
select the desired register by writing to it and sending the registers
address byte. This process begins by the master sending a control
byte with the R/W bit set to 0, indicating a write. Once it receives
an Acknowledge from the ISL95871C it sends a register address
byte representing the internal register it wants to read. The
ISL95871C will respond with an Acknowledge. The master must
then respond with a Stop condition. After the Stop condition, the
master follows with a new Start condition then sends a new
control byte with the ISL95871C slave address and the R/W bit set
to 1, indicating a read. The ISL95871C will Acknowledge then send
the lower byte stored in that register. After receiving the byte, the
master Acknowledges by holding SDA low during the 9th clock
pulse. ISL95871C then sends the higher byte stored in the register.
After the second byte neither device holds SDA low (No
Acknowledge). The master will then produce a Stop condition to
end the read transaction.
19
The ISL95871C does not support reading more than 1 register
per transaction.
Application Information
The following battery charger design refers to the “Typical
Application Circuit” (see Figure 4 on page 4), where typical
battery configuration of 3S2P is used. This section describes how
to select the external components including the inductor, input
and output capacitors, switching MOSFETs and current sensing
resistors.
Inductor Selection
The inductor selection has trade-offs between cost, size,
crossover frequency and efficiency. For example, the lower the
inductance, the smaller the size, but ripple current is higher. This
also results in higher AC losses in the magnetic core and the
windings, which decreases the system efficiency. On the other
hand, the higher inductance results in lower ripple current and
smaller output filter capacitors, but it has higher DCR (DC
resistance of the inductor) loss, lower saturation current and has
slower transient response. Thus, the practical inductor design is
based on the inductor ripple current being ±15% to ±20% of the
maximum operating DC current at maximum input voltage.
Maximum ripple is at 50% duty cycle or VBAT = VIN,MAX/2. The
required inductance for ±15% ripple current can be calculated
from Equation 3:
V IN MAX
L = ------------------------------------------------------4  F SW  0.3  I L MAX
(EQ. 3)
Where VIN,MAX is the maximum input voltage, FSW is the
switching frequency and IL,MAX is the max DC current in the
inductor.
For VIN,MAX = 20V, VBAT = 12.6V, IBAT,MAX = 4.5A, and
fs = 400kHz, the calculated inductance is 9.3µH. Choosing the
closest standard value gives L = 10µH. Ferrite cores are often the
best choice since they are optimized at 400kHz to 600kHz
operation with low core loss. The core must be large enough not
to saturate at the peak inductor current IPeak in Equation 4:
1
I PEAK = I L MAX + ---  I RIPPLE
2
(EQ. 4)
Inductor saturation can lead to cascade failures due to very high
currents. Conservative design limits the peak and RMS current in
the inductor to less than 90% of the rated saturation current.
Crossover frequency is heavily dependent on the inductor value.
FCO should be less than 20% of the switching frequency and a
conservative design has FCO less than 10% of the switching
frequency. The highest FCO is in voltage control mode with the
battery removed and may be calculated (approximately) from
Equation 5:
5  11  R S2
F CO = -----------------------------2  L
(EQ. 5)
Output Capacitor Selection
The output capacitor in parallel with the battery is used to absorb
the high frequency switching ripple current and smooth the
FN6856.2
June 8, 2011
ISL95871C
output voltage. The RMS value of the output ripple current IRMS
is given by Equation 6:
V IN MAX
I RMS1 = ----------------------------------  D   1 – D 
12  L  F SW
(EQ. 6)
(EQ. 7)
For VIN,MAX = 19V, VBAT = 16.8V, L = 10µH, and fs = 400kHz, the
maximum RMS current is 0.19A. A typical 20µF ceramic
capacitor is a good choice to absorb this current and also has
very small size. Organic polymer capacitors have high
capacitance with small size and have a significant equivalent
series resistance (ESR). Although ESR adds to ripple voltage, it
also creates a high frequency zero that helps the closed loop
operation of the buck regulator.
EMI considerations usually make it desirable to minimize ripple
current in the battery leads. Beads may be added in series with
the battery pack to increase the battery impedance at 400kHz
switching frequency. Switching ripple current splits between the
battery and the output capacitor depending on the ESR of the
output capacitor and battery impedance. If the ESR of the output
capacitor is 10m and battery impedance is raised to 2 with a
bead, then only 0.5% of the ripple current will flow in the battery.
Snubber Design
ISL95871C's buck regulator operates in discontinuous current
mode (DCM) when the load current is less than half the
peak-to-peak current in the inductor. After the low-side FET turns
off, the phase voltage rings due to the high impedance with both
FETs off. This can be seen in Figure 15 on page 10. Adding a
snubber (resistor in series with a capacitor) from the phase node
to ground can greatly reduce the ringing. In some situations a
snubber can improve output ripple and regulation.
The snubber capacitor should be approximately twice the
parasitic capacitance on the phase node. This can be estimated
by operating at very low load current (100mA) and measuring the
ringing frequency.
CSNUB and RSNUB can be calculated from Equations 8 and 9:
2
C SNUB = -----------------------------------2
 2F ring   L
R SNUB =
(EQ. 10)
IN
Where the duty cycle D is the ratio of the output voltage (battery
voltage) over the input voltage for continuous conduction mode
which is typical operation for the battery charger. During the
battery charge period, the output voltage varies from its initial
battery voltage to the rated battery voltage. Thus, the duty cycle
varies from 0.53 for the minimum battery voltage of 7.5V
(2.5V/Cell) to 0.88 for the maximum battery voltage of 12.6V.
The maximum RMS value of the output ripple current occurs at
the duty cycle of 0.5 and is expressed as Equation 7:
V IN MAX
I RMS1  max  = -----------------------------------------4  12  L  F SW
V OUT  V IN – V OUT 
I RMS2 = I BAT  -------------------------------------------------V
where IBAT is the battery charging current. This RMS ripple
current must be smaller than the rated RMS current in the
capacitor datasheet. Non-tantalum chemistries (ceramic,
aluminum, or OSCON) are preferred due to their resistance to
power-up surge currents when the AC-adapter is plugged into the
battery charger. For Notebook battery charger applications, it is
recommended that ceramic capacitors or polymer capacitors
from Sanyo be used due to their small size and reasonable cost.
Loop Compensation Design
ISL95871C has three closed loop control modes. One, controls
the output voltage when the battery is fully charged or absent. A
second, controls the current into the battery when charging and
the third, limits current drawn from the adapter. The charge
current and input current control loops are compensated by a
single capacitor on the ICOMP pin. The voltage control loop is
compensated by a network on the VCOMP pin. Descriptions of
these control loops and guidelines for selecting compensation
components will be given in the following sections. Which loop
controls the output is determined by the minimum current buffer
and the minimum voltage buffer shown in the “Functional Block
Diagram” on page 4. These three loops will be described
separately.
Transconductance Amplifiers GMV, GMI and
GMS
ISL95871C uses several transconductance amplifiers (also
known as gm amps). Most commercially available op amps are
voltage controlled voltage sources with gain expressed as
A = VOUT/VIN. gm amps are voltage controlled current sources
with gain expressed as gm = IOUT/VIN. gm will appear in some of
the equations for poles and zeros in the compensation.
PWM Gain Fm
The Pulse Width Modulator in the ISL95871C converts voltage at
VCOMP to a duty cycle by comparing VCOMP to a triangle wave
(duty = VCOMP/VP-P RAMP). The low-pass filter formed by L and
CO convert the duty cycle to a DC output voltage
(Vo = VDCIN*duty). In ISL95871C, the triangle wave amplitude is
proportional to VDCIN. Making the ramp amplitude proportional
to DCIN makes the gain from VCOMP to the PHASE output a
constant 11 and is independent of DCIN. For small signal AC
analysis, the battery is modeled by its internal resistance. The
total output resistance is the sum of the sense resistor and the
internal resistance of the MOSFETs, inductor and capacitor.
Figure 26 shows the small signal model of the pulse width
modulator (PWM), power stage, output filter and battery.
(EQ. 8)
2L
----------------C SNUB
(EQ. 9)
Input Capacitor Selection
The input capacitor absorbs the ripple current from the
synchronous buck converter, which is given by Equation 10:
20
FN6856.2
June 8, 2011
ISL95871C
11
RAMP GEN
VRAMP = VIN/11
+
S

CO
PWM
INPUT
0.25
+
-
CA2
GMI
+
DACI
CICOMP
L
11
RL_DCR
PWM
INPUT
CO
RBAT
FIGURE 26. SMALL SIGNAL AC MODEL
In most cases, the battery resistance is very small (<200m)
resulting in a very low Q in the output filter. This results in a
frequency response from the input of the PWM to the inductor
current with a single pole at the frequency calculated in
Equation 11:
(EQ. 11)
The output capacitor creates a pole at a very high frequency due
to the small resistance in parallel with it. The frequency of this
pole is calculated in Equation 12:
1
F POLE2 = -----------------------------------2  C o  R BAT
(EQ. 12)
Charge Current Control Loop
When the battery is less than fully charged, the voltage error
amplifier goes to its maximum output (limited to 0.3V above
ICOMP) and the ICOMP voltage controls the loop through the
minimum voltage buffer. Figure 28 shows the charge current
control loop.
The compensation capacitor (CICOMP) gives the error amplifier
(GMI) a pole at a very low frequency (<<1Hz) and a zero at FZ1.
FZ1 is created by the 0.25*CA2 output added to ICOMP. The
frequency can be calculated from Equation 13:
4  gm2
F ZERO = ------------------------------------ 2  C ICOMP 
gm2 = 50A  V
CO
RS2
RBAT
RESR
1.5  4   50A  V   L
C ICOMP = ----------------------------------------------------------------------------------- R S2 + r DS  ON  + R DCR + R BAT 
RESR
 R S2 + r DS  ON  + R DCR + R BAT 
F POLE1 = -----------------------------------------------------------------------------------2  L
CF2
FIGURE 27. CHARGE CURRENT LIMIT LOOP
RS2
RFET_RDSON
RF2
CSOP
+
20X
CSON
ICOMP
PWM
GAIN=11
RL_DCR
RFET_RDSON
L
DRIVERS
-
L
PHASE
VIN
(EQ. 13)
(EQ. 14)
A filter should be added between RS2 and CSOP and CSON to
reduce switching noise. The filter roll-off frequency should be
between the crossover frequency and the switching frequency
(~100kHz). RF2 should be small (<10 to minimize offsets due
to leakage current into CSOP. The filter cutoff frequency is
calculated using Equation 15:
1
F FILTER = ---------------------------------------- 2  C F2  R F2 
(EQ. 15)
The crossover frequency is determined by the DC gain of the
modulator and output filter and the pole in Equation 12. The DC
gain is calculated in Equation 16 and the crossover frequency is
calculated with Equation 17. The Bode plot of the loop gain, the
compensator gain and the power stage gain is shown in
Figure 28.
11  R S2
A DC = ----------------------------------------------------------------------------------- R S2 + r DS  ON  + R DCR + R BAT 
(EQ. 16)
11  R S2
F CO = A DC  F POLE = ---------------------2  L
(EQ. 17)
Adapter Current Limit Control Loop
If the combined battery charge current and system load current
draws current that equals the adapter current limit set by the
InputCurrent register, ISL95871C will reduce the current to the
battery and/or reduce the output voltage to hold the adapter
current at the limit. Above the adapter current limit, the
minimum current buffer equals the output of GMS and ICOMP
controls the charger output. Figure 29 shows the adapter current
limit control loop.
Placing this zero at a frequency equal to the pole calculated in
Equation 12 will result in maximum gain at low frequencies and
phase margin near 90°. If the zero is at a higher frequency
(smaller CICOMP), the DC gain will be higher but the phase
margin will be lower. Use a capacitor on ICOMP that is equal to or
greater than the value calculated in Equation 14. The factor of
1.5 is to ensure the zero is at a frequency lower than the pole
including tolerance variations.
21
FN6856.2
June 8, 2011
ISL95871C
60
COMPENSATOR
MODULATOR
LOOP
FZERO
40
GAIN (dB)
20
across the internal battery resistance decreases. As battery
current decreases, the 2 current error amplifiers (GMI and GMS)
output their maximum current and charge the capacitor on
ICOMP to its maximum voltage (limited to 0.3V above VCOMP).
With high voltage on ICOMP, the minimum voltage buffer output
equals the voltage on VCOMP.
The voltage control loop is shown in Figure 30.
0
L
PHASE
11
-20
RL_DCR
RFET_RDSON
FPOLE1
FFILTER
-40
FPOLE2
-60
10
100
1k
10k
100k
1M

S
CA2
+
0.25
-
FREQUENCY (Hz)
VCOMP
DCIN
RS1
0.25
CA2
+
ICOMP
CF2
RS2
CSON
+
RESR
FIGURE 30. VOLTAGE CONTROL LOOP
RF2
CSOP
+
20X
-
-
CSSN
CSSP
R4
DACV
CF1
-
RBAT
CO
RVCOMP
RL_DCR
RFET_RDSON
S
RS2
R3
GMV
+
CVCOMP
L
11
RF1

CF2
CSON
FIGURE 28. CHARGE CURRENT LOOP BODE PLOTS
PHASE
RF2
CSOP
+
20x
-
20
CO
CA1
RBAT
RESR
GMS
+
DACS
CICOMP
FIGURE 29. ADAPTER CURRENT LIMIT LOOP
The loop response equations, bode plots and the selection of
CICOMP are the same as the charge current control loop with loop
gain reduced by the duty cycle and the ratio of RS1/RS2. In other
words, if RS1 = RS2 and the duty cycle D = 50%, the loop gain will
be 6dB lower than the loop gain in Figure 29. This gives lower
crossover frequency and higher phase margin in this mode. If
RS1/RS2 = 2 and the duty cycle is 50% then the adapter current
loop gain will be identical to the gain in Figure 29.
A filter should be added between RS1 and CSIP and CSIN to
reduce switching noise. The filter roll off frequency should be
between the crossover frequency and the switching frequency
(~100kHz).
Voltage Control Loop
When the battery is charged to the voltage set by ChargeVoltage
register the voltage error amplifier (GMV) takes control of the
output (assuming that the adapter current is below the limit set
by ACLIM). The voltage error amplifier (GMV) discharges the cap
on VCOMP to limit the output voltage. The current to the battery
decreases as the cells charge to the fixed voltage and the voltage
22
Output LC Filter Transfer Functions
The gain from the phase node to the system output and battery
depend entirely on external components. Typical output LC filter
response is shown in Figure 31. Transfer function ALC(s) is shown
in Equation 18:
s 
 1 – ------------
 ESR
A LC = -------------------------------------------------------- s2

s
 ----------- + ----------------------- + 1



Q


 DP

LC
1
 ESR = ---------------------------- R ESR  C o 
1
 LC = ---------------------- L  Co 
(EQ. 18)
L
Q = R o  -----Co
The resistance RO is a combination of MOSFET rDS(ON), inductor
DCR, RS2 and the internal resistance of the battery (normally
between 50m and 200m). The worst case for voltage mode
control is when the battery is absent. This results in the highest Q
of the LC filter and the lowest phase margin.
The compensation network consists of the voltage error amplifier
GMV and the compensation network RVCOMP, CVCOMP which give
the loop very high DC gain, a very low frequency pole and a zero at
FZERO1. Inductor current information is added to the feedback to
create a second zero FZERO2. The low pass filter RF2, CF2 between
RS2 and ISL95871C add a pole at FFILTER. R3 and R4 are internal
divider resistors that set the DC output voltage. For a 3-cell battery,
R3 = 500k and R4 = 100k. The equations following relate the
compensation network’s poles, zeros and gain to the components
in Figure 30. Figure 32 shows an asymptotic Bode plot of the
DC/DC converter’s gain vs frequency. It is strongly recommended
that FZERO1 is approximately 30% of FLC and FZERO2 is
approximately 70% of FLC.
FN6856.2
June 8, 2011
ISL95871C
10
GAIN (dB)
0
NO BATTERY
-20
-30
RBATTERY = 200mΩ
-40
RBATTERY = 50mΩ
1
F ESR = ---------------------------------------- 2  C o  R ESR 
(EQ. 24)
Choose RVCOMP equal or lower than the value calculated from
Equation 25.
-60
 R 3 + R 4
5
R VCOMP =  0.7  F LC    2  C o  R S2    ------------   --------------------
 gm1  R
4 
-20
PHASE (°)
(EQ. 23)
-10
-50
-40
-60
-80
-100
(EQ. 25)
Next, choose CVCOMP equal or higher than the value calculated
from Equation 26.
-120
-140
1
C VCOMP = --------------------------------------------------------------------- 0.3  F LC    2  R VCOMP 
-160
100 200
500
1k
2k
5k 10k 20k
50k 100k 200k
FIGURE 31. FREQUENCY RESPONSE OF THE LC OUTPUT FILTER
COMPENSATOR
MODULATOR
LOOP
FPOLE1
FLC
PCB Layout Considerations
Power and Signal Layers Placement on the PCB
As a general rule, power layers should be close together, either
on the top or bottom of the board, with signal layers on the
opposite side of the board. As an example, layer arrangement on
a 4-layer board is shown below:
60
40
(EQ. 26)
500k
FREQUENCY (Hz)
1. Top Layer: signal lines, or half board for signal lines and the
other half board for power lines
20
GAIN (dB)
1
F POLE1 = ------------------------------------- 2  R S2  C o 
2. Signal Ground
3. Power Layers: Power Ground
0
FFILTER
4. Bottom Layer: Power MOSFET, Inductors and other Power
traces
-20
-40
FZERO1
Separate the power voltage and current flowing path from the
control and logic level signal path. The controller IC will stay on
the signal layer, which is isolated by the signal ground to the
power signal traces.
FZERO2
FESR
-60
100
1k
10k
100k
1M
FREQUENCY (Hz)
FIGURE 32. ASYMPTOTIC BODE PLOT OF THE VOLTAGE CONTROL
LOOP GAIN
Compensation Break Frequency Equations
1
F ZERO1 = ---------------------------------------------------------------- 2  C VCOMP  R VCOMP 
 R VCOMP   R 4  gm1
F ZERO2 =  ---------------------------------   --------------------   ------------
 2  R S2  C o  R 4 + R 3  5 
(EQ. 19)
(EQ. 20)
1
F LC = ----------------------------- 2 L  C o 
(EQ. 21)
1
F FILTER = ---------------------------------------- 2  R F2  C F2 
(EQ. 22)
23
Component Placement
The highest priority for placement close to the IC are the high current
components. Place the VIN capacitors as close as possible to the VIN
and PGND pins. The power inductor, charge current sense resistor
and output caps are the second highest priority. A layer of power
ground under these components and high current pins on
ISL95871C (pins 9 through 33) will keep current loops small and
minimize EMI radiated from this high current loops.
Small signals such as current sense and compensation should be
placed near their connections to ISL95871C and have an area of
AGND “quiet ground”) on the adjacent layer. An area of quiet
ground should be on the layer under ISL95871C pins 1 through 8
and 34 through 50. The best tie-point between the signal ground
and the power ground is at the negative side of the output
capacitor on each side, where there is little noise; a noisy trace
beneath the IC is not recommended.
Signal Ground and Power Ground Connection
At minimum, a reasonably large area of copper, which will shield
other noise couplings through the IC, should be used as signal
FN6856.2
June 8, 2011
ISL95871C
ground beneath the IC. The best tie-point between the signal
ground and the power ground is at the negative side of the output
capacitor on each side, where there is little noise; a noisy trace
beneath the IC is not recommended.
AGND and VDD Pin
At least one high quality ceramic decoupling capacitor should be
used to cross these two pins. The decoupling capacitor can be
put close to the IC.
PGND Pins
PGND pin should be laid out to the negative side of the relevant
output capacitor with separate traces. The negative side of the
output capacitor must be close to the source node of the bottom
MOSFET. This trace is the return path of LFET gate drive.
PHASE Pins
Connect this pin to the output inductor. This trace should be
short, and positioned away from other weak signal traces. This
node has a very high dv/dt with a voltage swing from the input
voltage to ground. No trace should be in parallel with it.
BOOT Pin
This pin carries gate drive current and trace should be as short as
possible.
H IG H
CU R REN T
TR A CE
SEN SE
R E S IS T O R
H IG H
CU R REN T
TR A CE
K E L V I N C O N N E C T IO N T R A C E S
T O T H E L O W P A S S F IL T E R A N D
CSO P AN D CSO N
FIGURE 33. CURRENT SENSE RESISTOR LAYOUT
24
CSOP, CSON, CSIP and CSIN Pins
Accurate charge current and adapter current sensing is critical
for good performance. The current sense resistor connects to the
CSON and the CSOP pins through a low pass filter with the filter
capacitor very near the IC (see Figure 4 on page 4). Traces from
the sense resistor should start at the pads of the sense resistor
and should be routed close together, through the low pass filter
and to the CSOP and CSON pins (see Figure 33). The CSON pin is
also used as the battery voltage feedback. The traces should be
routed away from the high dv/dt and di/dt pins like PHASE, BOOT
pins. In general, the current sense resistor should be close to the
IC. These guidelines should also be followed for the adapter
current sense resistor and CSIP and CSIN. Other layout
arrangements should be adjusted accordingly.
DCIN Pin
This pin connects to AC-adapter output voltage, and should be
less noise sensitive.
Copper Size for the Phase Node
The capacitance of PHASE should be kept very low to minimize
ringing. It would be best to limit the size of the PHASE node
copper in strict accordance with the current and thermal
management of the application.
Identify the Power and Signal Ground
The input and output capacitors of the converters, the source
terminal of the bottom switching MOSFET PGND should connect
to the power ground. The other components should connect to
signal ground. Signal and power ground are tied together at one
point as close as possible to the ISL95871C.
Clamping Capacitor for Switching MOSFET
It is recommended that ceramic capacitors be used closely
connected to VIN and PGND (the drain of the high-side MOSFET
and the source of the low-side MOSFET). This capacitor reduces
the noise and the power loss of the MOSFETs.
FN6856.2
June 8, 2011
ISL95871C
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest Rev.
DATE
REVISION
CHANGE
5/27/11
FN6856.2
On page 7 in the “Electrical Specifications” table:
Removed “ICM Gain” limits
Removed “ICM Offset” specs
9/28/10
FN6856.1
Corrected max limit of “ACIN Rising Threshold” on page 7 from 3.25V to 3.28V
9/20/10
FN6856.0
Initial Release.
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25
FN6856.2
June 8, 2011
ISL95871C
Package Outline Drawing
L50.5x7
50 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 1/10
3.50
B
PIN 1
INDEX AREA
5.00
36X 0.40
A
2X 3.20
42
50
1
41
PIN #1
IDENTIFICATION
46X 0.40
2.575
7.00
2X 6.00
4 50X 0.20
0.10 M C A B
0.35
0.45
0.62
0.35
1.8749
2X 0.60
2X 1.00
0.35
1.275
1.7299
1.725
2.525
26
16
0.10
2X
25
0.296
6X 0.15
17
1.40
0.5885
1.40
6X 0.1950
TOP VIEW
BOTTOM VIEW
(3.50)
(2X 3.20)
PACKAGE OUTLINE
SEE DETAIL "X"
(46X 0.40)
PIN ONE
MAX. 1.0
(36X 0.60)
(50X 0.20)
(2X 7.4)
0.10 C
C
SEATING PLANE
0.05 C
SIDE VIEW
(2.575)
(0.35)
(0.45)
(0.62)
(2X 6.0)
(1.7299)
(1.275)
(1.725)
(0.7885)
(1.8749)
(0.35)
(0.35)
C
(2.725)
0 . 2 REF
5
0-0.05
(0.496)
DETAIL "X"
(6X 0.395)
(1.40)
(1.40)
(4.20)
(5.40)
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.10
Angular ±2.50°
4.
Dimension applies to the metallized terminal and is measured
between 0.015mm and 0.30mm from the terminal tip.
5.
Tiebar shown (if present) is a non-functional feature.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
26
FN6856.2
June 8, 2011
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