5962-0720601VXC

REVISIONS
LTR
DESCRIPTION
DATE (YR-MO-DA)
APPROVED
REV
SHEET
REV
SHEET
15
16
17
18
19
REV STATUS
REV
OF SHEETS
SHEET
PMIC N/A
PREPARED BY
RICK OFFICER
STANDARD
MICROCIRCUIT
DRAWING
THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
AMSC N/A
1
2
3
4
5
DRAWING APPROVAL DATE
08-04-22
REVISION LEVEL
8
9
10
11
12
13
MICROCIRCUIT, DIGITAL-LINEAR, 14-BIT,
105 MSPS, ANALOG-TO-DIGITAL CONVERTER,
MONOLITHIC SILICON
SIZE
CAGE CODE
A
67268
SHEET
DSCC FORM 2233
APR 97
7
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
http://www.dscc.dla.mil
CHECKED BY
RAJESH PITHADIA
APPROVED BY
ROBERT M. HEBER
6
1 OF
5962-07206
19
5962-E013-08
14
1. SCOPE
1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M)
and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or
Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN.
1.2 PIN. The PIN is as shown in the following example:
5962
-
07206
Federal
stock class
designator
\
RHA
designator
(see 1.2.1)
01
V
X
C
Device
type
(see 1.2.2)
Device
class
designator
(see 1.2.3)
Case
outline
(see 1.2.4)
Lead
finish
(see 1.2.5)
/
\/
Drawing number
1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are
marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A
specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.
1.2.2 Device type(s). The device type(s) identify the circuit function as follows:
Device type
01
Generic number
Circuit function
ADS5424M
14 bit, 105 MSPS, analog to digital converter
1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as
follows:
Device class
Device requirements documentation
M
Vendor self-certification to the requirements for MIL-STD-883 compliant, nonJAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A
Q or V
Certification and qualification to MIL-PRF-38535
1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:
Outline letter
X
Descriptive designator
Terminals
See figure 1
52
Package style
Quad flat pack with non-conductive tie bar
1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535,
appendix A for device class M.
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REVISION LEVEL
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1.3 Absolute maximum ratings. 1/
Supply voltage :
AVDD to GND ........................................................................................................ 6 V
DRVDD to GND ..................................................................................................... 5 V
Analog input to GND .................................................................................................. -0.3 V to AVDD + 0.3 V
Clock input to GND .................................................................................................... -0.3 V to AVDD + 0.3 V
CLK to CLK .............................................................................................................. ±2.5 V
Digital data output to GND ......................................................................................... -0.3 V to DRVDD + 0.3 V
Maximum junction temperature (TJ) .......................................................................... +150°C
Storage temperature range (TSTG) ........................................................................... -65°C to 150°C
Thermal resistance, junction-to-ambient (θJA) ........................................................... 21.81°C/W 2/
Thermal resistance, junction-to-case (θJC) ................................................................ 0.849°C/W 3/
1.4 Recommended operating conditions.
Supplies:
Analog supply voltage (AVDD) ............................................................................... 4.75 V to 5.25 V
Output driver supply voltage (DRVDD) ................................................................... 3 V to 3.6 V
Analog input:
Differential input range ........................................................................................... 2.2 VPP
Input common mode voltage (VCM) ....................................................................... 2.4 V
Digital output:
Maximum output load ............................................................................................ 10 pF
Clock input:
ADCLK input sample rate (sine wave) (1/tC) ......................................................... 30 MSPS to 105 MSPS
Clock amplitude, sine wave, differential ................................................................. 3 VPP
Clock duty cycle ..................................................................................................... 50 %
Operating case temperature range (TC) .................................................................... -55°C to +125°C
Estimated device life at elevated temperatures electromigration fail mode:
________
1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the
maximum levels may degrade performance and affect reliability.
2/ Heat slug connected to printed circuit board (PCB) thermal plane. Airflow is at 0 LFM (no airflow).
3/ Specified with the thermal bond pad on the backside of the package soldered to a 2 ounce CU plate PCB thermal plane.
STANDARD
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A
REVISION LEVEL
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2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part
of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the
solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARDS
MIL-STD-883 MIL-STD-1835 -
Test Method Standard Microcircuits.
Interface Standard Electronic Component Case Outlines.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103 MIL-HDBK-780 -
List of Standard Microcircuit Drawings.
Standard Microcircuit Drawings.
(Copies of these documents are available online at http://assist.daps.dla.mil/quicksearch/ or http://assist.daps.dla.mil or
from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of
this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The
modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for
device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified
herein.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in
MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M.
3.2.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1.
3.2.2 Terminal connections. The terminal connections shall be as shown in figure 2.
3.2.3 Block diagram. The block diagram shall be as shown in figure 3.
3.2.4 Timing waveforms. The timing waveforms shall be as shown in figure 4.
3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full
case operating temperature range.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical
tests for each subgroup are defined in table I.
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TABLE I. Electrical performance characteristics.
Test
Symbol
Conditions 1/
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Group A
subgroups
Device
type
Unit
Limits
Min
Max
Internal reference voltages section
Reference voltage
VREF
1,2,3
01
2.38
2.41
V
Dynamic accuracy section
Differential linearity
error
DNL
fIN = 10 MHz
4,5,6
01
-0.98
1.5
LSB
Integral linearity error
INL
fIN = 10 MHz
4,5
01
-5.0
+5.0
LSB
-6.9
+6.9
6
Offset error
4,5,6
01
-1.5
1.5
%FS
Gain error
4,5,6
01
-5
5
%FS
1,2,3
01
410
mA
1,2,3
01
55
mA
1,2,3
01
2.3
W
Power supply section
Analog supply current
IAVDD
FS = 105 MSPS,
VIN = full scale,
fIN = 70 MHz
Output buffer supply
current
IDRVDD
FS = 105 MSPS,
VIN = full scale,
fIN = 70 MHz
Power dissipation
PD
FS = 105 MSPS,
fIN = 70 MHz,
total power with 10 pF load
on each digital output to
ground
See footnote at end of table.
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TABLE I. Electrical performance characteristics – Continued.
Test
Symbol
Conditions 1/
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Group A
subgroups
Device
type
Unit
Limits
Min
Max
Dynamic AC characteristics section
Signal-to-noise ratio
Spurious free dynamic
range
SNR
SFDR
4,6
fIN = 10 MHz
71.0
fIN = 30 MHz
4,5,6
70.0
fIN = 70 MHz
4
68.2
5
67.0
6
68.0
4
fIN = 10 MHz
fIN = 70 MHz
SINAD
70.5
5
fIN = 30 MHz
Signal-to-noise plus
distortion
01
fIN = 30 MHz
fIN = 70 MHz
72.0
5,6
71.0
4
77.0
5
69.0
6
75.0
4
68.0
5
69.0
6
67.0
4
fIN = 10 MHz
01
01
dBc
dBc
68.6
5
68.3
6
68.2
4,6
69.4
5
67.0
4
65.8
5
64.6
6
65.0
dBc
See footnote at end of table.
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TABLE I. Electrical performance characteristics – Continued.
Test
Symbol
Conditions 1/
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Group A
subgroups
Device
type
Unit
Limits
Min
Max
Dynamic AC characteristics section - continued.
Second harmonic
HD2
4
fIN = 10 MHz
fIN = 30 MHz
fIN = 70 MHz
Third harmonic
HD3
fIN = 70 MHz
72.0
5,6
71.0
4
77.0
5
69.0
6
75.0
4
68.0
5
69.0
6
67.0
4
fIN = 10 MHz
fIN = 30 MHz
Worst other harmonic /
spur (other than
HD2 and HD3)
01
01
72.0
5,6
71.0
4
77.0
5
69.0
6
75.0
4
68.0
5
69.0
6
67.0
fIN = 10 MHz
4,5,6
fIN = 30 MHz
4,6
80.0
5
74.0
4,6
74.0
5
72.0
fIN = 70 MHz
01
dBc
dBc
75.0
dBc
See footnote at end of table.
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TABLE I. Electrical performance characteristics – Continued.
Test
Symbol
Conditions 1/
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Group A
subgroups
Device
type
Unit
Limits
Min
Max
Dynamic AC characteristics section - continued.
Total harmonic
distortion
THD
4
fIN = 10 MHz
70.0
4
75.0
5
68.0
6
73.8
4
67.4
5
67.2
6
66.4
fIN = 70 MHz
ENOB
4
fIN = 10 MHz
fIN = 30 MHz
71.0
5,6
fIN = 30 MHz
Effective number of bits
01
01
11.1
5,6
11.0
4,6
11.2
5
10.8
4
10.6
5
10.4
6
10.5
fIN = 70 MHz
dBc
Bits
See footnote at end of table.
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TABLE I. Electrical performance characteristics – Continued.
Test
Symbol
Conditions 1/
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Group A
subgroups
Device
type
Limits
Min
Digital characteristics
Unit
Max
2/
Digital outputs section
Low level output
voltage
High level output
voltage
Output data voltage
midpoint
VOL
CLOAD = 10 pF 3/
1,2,3
01
VOH
CLOAD = 10 pF 3/
1,2,3
01
2.6
1,2,3
01
1.65
1.8
V
DMID
0.6
V
V
Timing characteristics
Clock to data ready (DRY) section
Clock rising 50% to
data ready falling
50%
tDR
9,10,11
01
2.2
4.7
ns
Clock rising 50% to
data ready rising
50% with 50% duty
cycle clock
tC_DR50%
9,10,11
01
7.0
9.5
ns
Clock to DATA, over range (OVR) section 4/
Valid DATA 5/ to
clock 50% with
50% duty cycle
clock (setup time)
tsu(C)
9,10,11
01
1.8
ns
Clock 50% to invalid
DATA 5/
(hold time)
th(C)
9,10,11
01
2.6
ns
See footnotes at end of table.
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TABLE I. Electrical performance characteristics – Continued.
Test
Symbol
Conditions 1/
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Group A
subgroups
Device
type
Unit
Limits
Min
Max
Timing characteristics - continued.
Data ready (DRY) / DATA, over range (OVR) section 4/
Valid DATA 5/ to data
ready 50% with 50%
duty cycle clock
(setup time)
tsu(DR)_50%
9,10,11
01
0.9
ns
Data ready 50% to
invalid DATA 5/ with
50% duty cycle clock
(hold time)
th(DR)_50%
9,10,11
01
3.9
ns
1/
Unless otherwise specified, sampling rate = 105 MSPS, 50 % clock duty cycle, AVDD = 5 V, DRVDD = 3.3 V,
-1 dBFS differential input, and 3 VPP differential sinusoidal clock.
2/
Unless otherwise specified, AVDD = 5 V and DRVDD = 3.3 V.
3/
Equivalent capacitance to ground of ( load + parasitics of transmission lines ).
4/
Data is updated with clock rising edge or data ready (DRY) falling edge.
5/
See VOH and VOL levels.
3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be
marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer
has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be
marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be
in accordance with MIL-PRF-38535, appendix A.
3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in
MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A.
3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535
listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of
compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see
6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this
drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and
herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein.
3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for
device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing.
3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2
herein) involving devices acquired to this drawing is required for any change that affects this drawing.
3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acquiring activity retain the
option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made
available onshore at the option of the reviewer.
3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in
microcircuit group number 57 (see MIL-PRF-38535, appendix A).
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Case X
FIGURE 1. Case outline.
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Case X – continued.
Dimensions
Symbol
Inches
Min
Max
Min
Max
A1
---
0.090
---
2.29
A2
---
0.115
---
2.92
A3
0.002
0.014
0.05
0.36
A4
0.03 BSC
0.762 BSC
b
0.005
0.011
0.127
0.28
c
0.004
0.008
0.10
0.20
D1/E1
0.740
0.760
18.8
D2/E2
D3/E3
0.300 BSC
1.198
D4/E4
19.3
7.62 BSC
1.222
30.43
0.630 BSC
e
31.04
16.0 BSC
0.025 BSC
0.64 BSC
F
0.175
0.225
4.44
5.72
J
0.029
0.042
0.75
1.05
K
---
0.020
---
0.51
K1
---
0.018
---
0.46
L
1.980
2.024
50.29
51.40
N
NOTES:
1.
2.
3.
4.
5.
6.
Millimeters
52
Controlling dimensions are inches, millimeter dimensions are given for reference only.
Ceramic quad flatpack with flat leads brazed to non-conductive tie bar carrier.
This package is hermetically sealed with a metal lid.
The leads are gold plated and can be solder dipped.
All leads are not shown for clarity purposes.
Lid and heat sink are connected to GND leads.
FIGURE 1. Case outline – Continued.
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Device type
01
Case outline
X
Terminal number
Terminal
symbol
Terminal
number
Terminal
symbol
1
DRVDD
27
GND
2
GND
28
AVDD
3
VREF
29
GND
4
GND
30
AVDD
5
CLK
31
DNC
6
CLK
32
OVR
7
GND
33
DRVDD
8
AVDD
34
GND
9
AVDD
35
DMID
10
GND
36
D0 (LSB)
11
AIN
37
D1
12
AIN
38
D2
13
GND
39
D3
14
AVDD
40
D4
15
GND
41
D5
16
AVDD
42
GND
17
GND
43
DRVCC
18
AVDD
44
D6
19
GND
45
D7
20
C1
46
D8
21
GND
47
D9
22
AVDD
48
D10
23
GND
49
D11
24
C2
50
D12
25
GND
51
D13 (MSB)
26
AVDD
52
DRY
FIGURE 2. Terminal connections.
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Terminal
symbol
DRVDD
Description
3.3 V power supply, digital output stage only.
GND
Ground.
VREF
2.4 V reference.
Bypass to ground with 0.1 μF microwave chip capacitor.
CLK
Clock input. Conversion initiated on rising edge.
CLK
Complemented of CLK, differential input.
AVDD
5 V analog power supply.
AIN
Analog input.
AIN
Complement of AIN, differential analog input.
C1
Internal voltage reference.
Bypass to ground with a 0.1 μF chip capacitor.
C2
Internal voltage reference.
Bypass to ground with a 0.1 μF chip capacitor.
DNC
Do not connect.
OVR
Over range bit. A logic level high indicates the analog input
exceeds full scale.
DMID
Output data voltage midpoint.
Approximately equal to (DVCC) / 2.
D0 (LSB)
Digital output bit (least significant bit); twos complement.
D1 – D5,
D6 – D12
Digital output bits in two’s complement.
D13 (MSB)
DRY
Digital output bit (most significant bit); twos complement.
Data ready output.
FIGURE 2. Terminal connections – continued.
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FIGURE 3. Block diagram.
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FIGURE 4. Timing waveforms.
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4. VERIFICATION
4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with
MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan
shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in
accordance with MIL-PRF-38535, appendix A.
4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted
on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in
accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection.
4.2.1 Additional criteria for device class M.
a.
Burn-in test, method 1015 of MIL-STD-883.
(1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision
level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
method 1015.
(2) TA = +125°C, minimum.
b.
Interim and final electrical test parameters shall be as specified in table IIA herein.
4.2.2 Additional criteria for device classes Q and V.
a.
The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the
device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under
document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
method 1015 of MIL-STD-883.
b.
Interim and final electrical test parameters shall be as specified in table IIA herein.
c.
Additional screening for device class V beyond the requirements of device class Q shall be as specified in
MIL-PRF-38535, appendix B.
4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in
accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups
A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).
4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with
MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified herein. Quality conformance inspection for
device class M shall be in accordance with MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed
for device class M shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections
(see 4.4.1 through 4.4.4).
4.4.1 Group A inspection.
a.
Tests shall be as specified in table IIA herein.
b.
Subgroups 7 and 8 in table I, method 5005 of MIL-STD-883 shall be omitted.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-07206
A
REVISION LEVEL
SHEET
17
TABLE IIA. Electrical test requirements.
Test requirements
Interim electrical
parameters (see 4.2)
Final electrical
parameters (see 4.2)
Group A test
requirements (see 4.4)
Group C end-point electrical
parameters (see 4.4)
Group D end-point electrical
parameters (see 4.4)
Group E end-point electrical
parameters (see 4.4)
Subgroups
(in accordance with
MIL-PRF-38535, table III)
Subgroups
(in accordance with
MIL-STD-883,
method 5005, table I)
Device
class M
1
1
1
1,2,3,4,5,6, 1/
9,10,11
1,2,3,4,5,6,
9,10,11
1
1,2,3,
1/
4,5,6,9,10,11
1,2,3,4,5,6,
9,10,11
1
1,2,3, 1/ 2/
4,5,6,9,10,11
1,2,3,4,5,6,
9,10,11
1 2/
1
1
1
Device
class Q
---
Device
class V
---
---
1/ PDA applies to subgroup 1.
2/ Delta limits as specified in table IIB shall be required where specified, and the delta limits
shall be computed with reference to the zero hour electrical parameters.
TABLE IIB. Burn-in and operating life test. Delta parameters (+25°C).
Parameters 1/
Reference voltage
Output buffer supply current
Symbol
Delta limits
VREF
±10 mV
IDRVDD
±4 mA
1/ These parameters shall be recorded before and after the required
burn-in and life test to determine delta limits.
4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table IIA herein.
4.4.2.1 Additional criteria for device class M. Steady-state life test conditions, method 1005 of MIL-STD-883:
a.
Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level
control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of
MIL-STD-883.
b.
TA = +125°C, minimum.
c.
Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883.
4.4.2.2 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature,
or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The
test circuit shall be maintained under document revision level control by the device manufacturer's TRB in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MIL-STD883.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-07206
A
REVISION LEVEL
SHEET
18
4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table IIA herein.
4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured
(see 3.5 herein).
a.
End-point electrical parameters shall be as specified in table IIA herein.
b.
For device classes Q and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as
specified in MIL-PRF-38535 for the RHA level being tested. For device class M, the devices shall be subjected to
radiation hardness assured tests as specified in MIL-PRF-38535, appendix A for the RHA level being tested. All device
classes must meet the postirradiation end-point electrical parameter limits as defined in table I at
TA = +25°C ±5°C, after exposure, to the subgroups specified in table IIA herein.
5. PACKAGING
5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes
Q and V or MIL-PRF-38535, appendix A for device class M.
6. NOTES
6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications
(original equipment), design applications, and logistics purposes.
6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor
prepared specification or drawing.
6.1.2 Substitutability. Device class Q devices will replace device class M devices.
6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for
the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal.
6.3 Record of users. Military and industrial users should inform Defense Supply Center Columbus (DSCC) when a system
application requires configuration control and which SMD's are applicable to that system. DSCC will maintain a record of users
and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic
devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544.
6.4 Comments. Comments on this drawing should be directed to DSCC-VA, Columbus, Ohio 43218-3990, or telephone (614)
692-0547.
6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in
MIL-PRF-38535 and MIL-HDBK-1331.
6.6 Sources of supply.
6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535.
The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DSCC-VA and have agreed to
this drawing.
6.6.2 Approved sources of supply for device class M. Approved sources of supply for class M are listed in MIL-HDBK-103.
The vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been
submitted to and accepted by DSCC-VA.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-07206
A
REVISION LEVEL
SHEET
19
STANDARD MICROCIRCUIT DRAWING BULLETIN
DATE: 08-04-22
Approved sources of supply for SMD 5962-07206 are listed below for immediate acquisition information only and shall
be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised
to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate
of compliance has been submitted to and accepted by DSCC-VA. This information bulletin is superseded by the next
dated revision of MIL-HDBK-103 and QML-38535. DSCC maintains an online database of all current sources of
supply at http://www.dscc.dla.mil/Programs/Smcr/.
Standard
microcircuit drawing
PIN 1/
Vendor
CAGE
number
Vendor
similar
PIN 2/
5962-0720601VXC
01295
ADS5424MHFG-V
1/ The lead finish shown for each PIN representing
a hermetic package is the most readily available
from the manufacturer listed for that part. If the
desired lead finish is not listed contact the vendor
to determine its availability.
2/ Caution. Do not use this number for item
acquisition. Items acquired to this number may not
satisfy the performance requirements of this drawing.
Vendor CAGE
number
01295
Vendor name
and address
Texas Instruments, Inc.
Semiconductor Group
8505 Forest Lane
P.O. Box 660199
Dallas, TX 75243
Point of contact:
U.S. Highway 75 South
P.O. Box 84, M/S 853
Sherman, TX 75090-9493
The information contained herein is disseminated for convenience only and the
Government assumes no liability whatsoever for any inaccuracies in the
information bulletin.