5962-9866101VXA

REVISIONS
LTR
DESCRIPTION
DATE (YR-MO-DA)
APPROVED
A
Update boilerplate to MIL-PRF-38535 requirements. – LTG
01-03-23
Thomas M. Hess
B
Change AC limits in table I. – LTG
01-05-04
Thomas M. Hess
C
Add device type 02. Update boilerplate to current MIL-PRF-38535
requirements. – CFS
04-07-06
Thomas M. Hess
D
Update boilerplate to current MIL-PRF-38535 requirements. – CFS
08-11-12
Thomas M. Hess
E
Add case outline Y. - PHN
09-07-28
Thomas M. Hess
REV
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REV STATUS
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PMIC N/A
PREPARED BY
Larry T. Gauder
STANDARD
MICROCIRCUIT
DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
http://www.dscc.dla.mil
CHECKED BY
Thanh V. Nguyen
APPROVED BY
THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
Monica L. Poelking
DRAWING APPROVAL DATE
MICROCIRCUIT, DIGITAL, FLOATING-POINT
DIGITAL SIGNAL PROCESSOR, MONOLITHIC
SILICON
00-03-03
AMSC N/A
REVISION LEVEL
E
SIZE
CAGE CODE
A
67268
SHEET
DSCC FORM 2233
APR 97
1 OF
5962-98661
48
5962-E422-09
1. SCOPE
1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and
M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part
or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN.
1.2 PIN. The PIN is as shown in the following example:
5962
-
98661
Federal
stock class
designator
\
RHA
designator
(see 1.2.1)
01
Q
X
X
Device
type
(see 1.2.2)
Device
class
designator
(see 1.2.3)
Case
outline
(see 1.2.4)
Lead
finish
(see 1.2.5)
/
\/
Drawing number
1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are
marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A
specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.
1.2.2 Device type(s). The device type(s) identify the circuit function as follows:
Device type
Generic number
01
02
Circuit function
320C6701
320C6701
Floating-point digital signal processor
Floating-point digital signal processor
1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as
follows:
Device class
Device requirements documentation
M
Vendor self-certification to the requirements for MIL-STD-883 compliant, nonJAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A
Q or V
Certification and qualification to MIL-PRF-38535
1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:
Outline letter
X
Y
Descriptive designator
See figure 2
See figure 2
Terminals
Package style
429
429
Ball grid array
Land grid array
1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535,
appendix A for device class M.
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1.3 Absolute maximum ratings.
1/ 2/
Supply voltage range (CVDD) ...................................................................
Supply voltage range (DVDD) ...................................................................
Input voltage range (VIN)..........................................................................
Output voltage range (VOUT) ....................................................................
Storage temperature range .....................................................................
Maximum junction temperature (TJ).........................................................
Thermal resistance, junction-to-case (θJC)...............................................
Solder ball reflow condition (Peak temperature) ......................................
1.4 Recommended operating conditions.
-0.3 V dc to +2.3 V dc
-0.3 V dc to +4.0 V dc
-0.3 V dc to +4.0 V dc
-0.3 V dc to +4.0 V dc
-55°C to +150°C
+119°C at 140 MHz
3°C/W
+220°C ±10°C
3/
Supply voltage range (CVDD) ...................................................................
Supply voltage range (DVDD) ...................................................................
Supply ground (VSS) ................................................................................
High level input voltage (VIH) ...................................................................
Low level input voltage (VIL).....................................................................
High level output current (IOH) ..................................................................
Low level output current (IOL) ...................................................................
Case operating temperature range (TC):
Device type 01 .....................................................................................
Device type 02 .....................................................................................
+1.81 V dc to +1.99 V dc
+3.14 V dc to +3.46 V dc
+0.0 V dc
2.0 V
0.8 V
-12 mA
12 mA
-55°C to +115°C
-55°C to +125°C
FIGURE 1. Impact of elevated temperature on device life.
________
1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the
maximum levels may degrade performance and affect reliability.
2/ All voltage values are with respect to VSS.
3/ Extended use at maximum recommended operating temperature may result in reduction of overall device life. See figure 1
above for impact of elevated temperature on device life.
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REVISION LEVEL
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2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part
of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the
solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535 -
Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARDS
MIL-STD-883
MIL-STD-1835
-
Test Method Standard Microcircuits.
Interface Standard Electronic Component Case Outlines.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103 MIL-HDBK-780 -
List of Standard Microcircuit Drawings.
Standard Microcircuit Drawings.
(Copies of these documents are available online at http://assist.daps.dla.mil/quicksearch/ or from the Standardization
Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
2.2 Non-Government publications. The following documents form a part of this document to the extent specified herein.
Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract.
INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS (IEEE)
IEEE 1149.1
-
Standard Test Access Port and Boundary Scan Architecture.
(Applications for copies should be addressed to the Institute of Electrical and Electronics Engineers, 445 Hoes Lane,
Piscataway, NJ 08855-1331)
2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text
of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The
modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for
device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified
herein.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified
in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M.
3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein and figure 2.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 3.
3.2.3 Block diagram(s). The block diagram(s) shall be as specified on figure 4.
3.2.4 Boundary scan instruction codes. The boundary scan instruction codes shall be as specified on figure 5.
3.2.3 Timing waveforms. The timing waveforms shall be as specified on figure 6.
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3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full
case operating temperature range.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical
tests for each subgroup are defined in table I.
3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be
marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer
has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be
marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be
in accordance with MIL-PRF-38535, appendix A.
3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in
MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A.
3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535
listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of
compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see
6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this
drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and
herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein.
3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for
device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing.
3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2
herein) involving devices acquired to this drawing is required for any change that affects this drawing.
3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acquiring activity retain the
option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made
available onshore at the option of the reviewer.
3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in
microcircuit group number 105 (see MIL-PRF-38535, appendix A).
3.11 IEEE 1149.1 compliance. These devices shall be compliant to IEEE 1149.1.
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REVISION LEVEL
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TABLE I. Electrical performance characteristics.
Test
Symbol
Conditions
1/
unless otherwise specified
Group A
subgroups
Device
type
Limits
Min
Unit
Max
Low level output voltage
VOL
2/
DVDD = 3.14 V
IOL = 12 mA
1, 2, 3
All
High level output voltage
VOH
2/
DVDD = 3.14 V
IOH = -12 mA
1, 2, 3
All
Input current
IIN
3/ 2/
VIN = VSS to DVDD
1, 2, 3
All
±10
µA
Off-state output leakage
current
IOZH,
IOZL
2/
VOUT = DVDD or 0 V
1, 2, 3
All
±10
µA
Input capacitance
CIN
f = 1 MHz at 0 V
See 4.4.1b
4
All
10
15
pF
Output capacitance
COUT
f = 1 MHz at 0 V
See 4.4.1b
4
All
10
15
pF
7,8
All
Functional tests
2/
CVDD = 1.81 V to 1.99 V
DVDD = 3.14 V to 3.46 V
See 4.4.1c
0.6
V
2.4
V
See footnotes at end of table.
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TABLE I. Electrical performance characteristics – continued.
Test
Symbol
Conditions
1/
unless otherwise specified
Group A
subgroups
Device
type
Limits
Min
CLKIN TIMINGS
Unit
Max
4/
Cycle time, CLKIN
1
Pulse duration, CLKIN
high
2
Pulse duration, CLKIN
low
3
Transition time, CLKIN
4
2/
See figure 5
CLKMODE=x4
9, 10, 11
All
28.4
ns
7.1
ns
9, 10, 11
All
0.4C
ns
0.45C
ns
0.4C
ns
0.45C
ns
CLKMODE=x1
CLKMODE=x4
CLKMODE=x1
CLKMODE=x4
9, 10, 11
All
CLKMODE=x1
CLKMODE=x4
9, 10, 11
All
5.0
ns
0.6
ns
P – 0.7
P + 0.7
ns
P – 0.7
P + 0.7
ns
(P/2)
- 0.5
(P/2)
+ 0.5
ns
PH
- 0.5
PH
+ 0.5
ns
(P/2)
- 0.5
(P/2)
+ 0.5
ns
PL
- 0.5
PL
+ 0.5
ns
0.6
ns
0.6
ns
CLKMODE=x1
CLKOUT1 TIMINGS
5/
Cycle time, CLKOUT1
1
Pulse duration,
CLKOUT1 high
2
See figure 5
CLKMODE=x4
9, 10, 11
All
9, 10, 11
All
CLKMODE=x1
CLKMODE=x4
CLKMODE=x1
Pulse duration,
CLKOUT1 low
3
CLKMODE=x4
9, 10, 11
All
CLKMODE=x1
Transition time,
CLKOUT1
CLKOUT2 TIMINGS
4
CLKMODE=x4
9, 10, 11
All
CLKMODE=x1
5/
Cycle time, CLKOUT2
1
Pulse duration,
CLKOUT2 high
Pulse duration,
CLKOUT2 low
Transition time,
CLKOUT2
See figure 5
9, 10, 11
All
2P
- 0.7
2P
+ 0.7
ns
2
9, 10, 11
All
P – 0.7
P + 0.7
ns
3
9, 10, 11
All
P – 0.7
P + 0.7
ns
4
9, 10, 11
All
0.6
ns
See footnotes at end of table.
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TABLE I. Electrical performance characteristics – continued.
Test
Symbol
Conditions
1/
unless otherwise specified
SSCLK, SDCLK, and CLKOUT2 to CLKOUT1
Delay time, CLKOUT1
edge to SSCLK edge
Delay time, CLKOUT1
edge to SSCLK edge
(1/2 clockrate)
Delay time, CLKOUT1
edge to CLKOUT2
edge
Delay time, CLKOUT1
edge to SDCLK edge
1
2/
2
Device
type
Limits
Unit
Min
Max
5/
See figure 5
9, 10, 11
All
-0.8
3.4
ns
2/
9, 10, 11
All
-1.0
3.0
ns
3
2/
9, 10, 11
All
-1.5
2.5
ns
4
2/
9, 10, 11
All
-1.5
1.9
ns
9, 10, 11
All
-1.0
4.5
ns
4.5
ns
ASYNCHRONOUS MEMORY READ and WRITE TIMING
Delay time, CLKOUT1
high to CEx valid
Delay time, CLKOUT1
high to BEx valid
Delay time, CLKOUT1
high to BEx invalid
Delay time, CLKOUT1
high to EAx valid
Delay time, CLKOUT1
high to EAx invalid
Setup time, read EDx
valid before
CLKOUT1 high
Hold time, read EDx
valid after CLKOUT1
high
Delay time, CLKOUT1
high to AOE valid
Delay time, CLKOUT1
high to ARE valid
Setup time, ARDY
valid before
CLKOUT1 high
Hold time, ARDY
valid after CLKOUT1
high
Delay time, CLKOUT1
high to EDx valid
Delay time, CLKOUT1
high to EDx invalid
Delay time, CLKOUT1
high to AWE valid
Group A
subgroups
See figure 5
6/ 7/
1
2/
2
2/
9, 10, 11
All
3
2/
9, 10, 11
All
4
2/
9, 10, 11
All
5
2/
9, 10, 11
All
-1.0
ns
6
2/
9, 10, 11
All
4.8
ns
7
2/
9, 10, 11
All
1.5
ns
8
2/
9, 10, 11
All
-1.0
4.5
ns
9
2/
9, 10, 11
All
-1.0
4.5
ns
-1.0
ns
4.5
ns
10
2/
9, 10, 11
All
3.5
ns
11
2/
9, 10, 11
All
1.5
ns
12
2/
9, 10, 11
All
13
2/
9, 10, 11
All
-1.0
14
2/
9, 10, 11
All
-1.0
4.5
ns
ns
4.5
ns
See footnotes at end of table.
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TABLE I. Electrical performance characteristics – continued.
Test
Symbol
Conditions
1/
unless otherwise specified
Group A
subgroups
Device
type
Limits
Min
SBSRAM READ and WRITE TIMING (Full-Rate SSCLK)
Output setup time,
CEx valid before
SSCLK high
Output hold time,
CEx valid after
SSCLK high
Output setup time,
BEx valid before
SSCLK high
Output hold time,
BEx invalid after
SSCLK high
Output setup time,
EAx valid before
SSCLK high
Output hold time, EAx
invalid after SSCLK
high
Setup time, read EDx
valid before SSCLK
high
Hold time, read EDx
valid after SSCLK
high
Output setup time,
SSADS valid before
SSCLK high
Output hold time,
SSADS valid after
SSCLK high
Output setup time,
SSOE valid before
SSCLK high
Output hold time,
SSOE valid after
SSCLK high
Output setup time,
EDx valid before
SSCLK high
Output hold time, EDx
invalid after SSCLK
high
Output setup time,
SSWE valid before
SSCLK high
Output hold time,
SSWE valid after
SSCLK high
1
2/
2
See figure 5
Unit
Max
8/
9, 10, 11
All
0.5P-1.5
ns
2/
9, 10, 11
All
0.5P-2.5
ns
3
2/
9, 10, 11
All
0.5P-1.6
ns
4
2/
9, 10, 11
All
0.5P-2.5
ns
5
2/
9, 10, 11
All
0.5P-1.7
ns
6
2/
9, 10, 11
All
0.5P-2.5
ns
7
2/
9, 10, 11
All
2.6
ns
8
2/
9, 10, 11
All
1.5
ns
9
2/
9, 10, 11
All
0.5P-1.5
ns
10
2/
9, 10, 11
All
0.5P-2.5
ns
11
2/
9, 10, 11
All
0.5P-1.5
ns
12
2/
9, 10, 11
All
0.5P-2.5
ns
13
2/
9, 10, 11
All
0.5P-1.5
ns
14
2/
9, 10, 11
All
0.5P-2.5
ns
15
2/
9, 10, 11
All
0.5P-1.5
ns
16
2/
9, 10, 11
All
0.5P-2.5
ns
See footnotes at end of table.
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TABLE I. Electrical performance characteristics – continued.
Test
Symbol
Conditions
1/
unless otherwise specified
Group A
subgroups
Device
type
Limits
Min
SBSRAM READ and WRITE TIMING (Half-Rate SSCLK)
Output setup time,
CEx valid before
SSCLK high
Output hold time,
CEx valid after
SSCLK high
Output setup time,
BEx valid before
SSCLK high
Output hold time,
BEx invalid after
SSCLK high
Output setup time,
EAx valid before
SSCLK high
Output hold time,
EAx invalid after
SSCLK high
Setup time, read
EDx valid before
SSCLK high
Hold time, read
EDx valid after
SSCLK high
Output setup time,
SSADS valid before
SSCLK high
Output hold time,
SSADS valid after
SSCLK high
Output setup time,
SSOE valid before
SSCLK high
Output hold time,
SSOE valid after
SSCLK high
Output setup time,
EDx valid before
SSCLK high
Output hold time,
EDx invalid after
SSCLK high
Output setup time,
SSWE valid before
SSCLK high
Output hold time,
SSWE valid after
SSCLK high
1
2/
2
See figure 5
Unit
Max
9/
9, 10, 11
All
1.5P-5.5
ns
2/
9, 10, 11
All
0.5P-2.3
ns
3
2/
9, 10, 11
All
1.5P-5.5
ns
4
2/
9, 10, 11
All
0.5P-2.3
ns
5
2/
9, 10, 11
All
1.5P-5.5
ns
6
2/
9, 10, 11
All
0.5P-2.3
ns
7
2/
9, 10, 11
All
3.8
ns
8
2/
9, 10, 11
All
1.5
ns
9
2/
9, 10, 11
All
1.5P-5.5
ns
10
2/
9, 10,11
All
0.5P-2.3
ns
11
2/
9,10, 11
All
1.5P-5.5
ns
12
2/
9, 10, 11
All
0.5P-2.3
ns
13
2/
9, 10, 11
All
1.5P-5.5
ns
14
2/
9, 10, 11
All
0.5P-2.3
ns
15
2/
9, 10, 11
All
1.5P-5.5
ns
16
2/
9, 10, 11
All
0.5P-2.3
ns
See footnote at end of table.
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TABLE I. Electrical performance characteristics – continued.
Test
Conditions
1/
unless otherwise specified
Symbol
Group A
subgroups
Device
type
Limits
Min
SYNCHRONOUS DRAM TIMING
Output setup time,
CEx valid before
SDCLK high
Output hold time,
CEx valid after
SDCLK high
Output setup time
BEx valid before
SDCLK high
Output hold time,
BEx invalid after
SDCLK high
Output setup time,
EAx valid before
SDCLK high
Output hold time,
EAx invalid after
SDCLK high
Setup time, read
EDx valid before
SDCLK high
Hold time, read
EDx valid after
SDCLK high
Output setup time,
SDCAS valid before
SDCLK high
Output hold time,
SDCAS valid after
SDCLK high
Output setup time,
EDx valid before
SDCLK high
Output hold time,
EDx invalid after
SDCLK high
Output setup time,
SDWE valid before
DCLK high
Output hold time,
SDWE valid after
SDCLK high
Output setup time,
SDA10 valid before
SDCLK high
Output hold time,
SDA10 invalid after
SDCLK high
1
2/
2
Unit
Max
9/
See figure 5
9, 10, 11
All
1.5P-5.0
ns
2/
9, 10, 11
All
0.5P-1.9
ns
3
2/
9, 10, 11
All
1.5P-5.0
ns
4
2/
9, 10, 11
All
0.5P-1.9
ns
5
2/
9, 10, 11
All
1.5P-5.0
ns
6
2/
9, 10, 11
All
0.5P-1.9
ns
7
2/
9, 10, 11
All
2.0
ns
8
2/
9, 10, 11
All
3.0
ns
9
2/
9, 10, 11
All
1.5P-5.0
ns
10
2/
9, 10, 11
All
0.5P-1.9
ns
11
2/
9, 10, 11
All
1.5P-5.0
ns
12
2/
9, 10, 11
All
0.5P-1.9
ns
13
2/
9, 10, 11
All
1.5P-5.0
ns
14
2/
9, 10, 11
All
0.5P-1.9
ns
15
2/
9, 10, 11
All
1.5P-5.0
ns
16
2/
9, 10, 11
All
0.5P-1.9
ns
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-98661
A
REVISION LEVEL
E
SHEET
11
TABLE I. Electrical performance characteristics – continued.
Test
Symbol
Conditions
1/
unless otherwise specified
Group A
subgroups
Device
type
Limits
Min
SYNCHRONOUS DRAM TIMING-Continued
Output setup time,
SDRAS valid before
SDCLK high
Output hold time,
SDRAS valid after
SDCLK high
17
2/
18
2/
HOLD/HOLDA TIMING
10/ 11/
Setup time,
HOLD high before
CLKOUT1 high
Hold time,
HOLD low after
CLKOUT1 high
Response time,
HOLD low to EMIF
Bus high impedance
Response time, EMIF
Bus high impedance
to HOLDA low
Response time,
HOLD high to
HOLDA high
Delay time, CLKOUT1
high to HOLDA valid
Delay time, CLKOUT1
high to EMIF Bus
high impedance
Delay time, CLKOUT1
high to EMIF Bus low
impedance
Response time,
HOLD high to EMIF
Bus low impedance
1
2/
2
Unit
Max
9/
9, 10, 11
All
1.5P-5.0
ns
9, 10, 11
All
0.5P-1.9
ns
9, 10, 11
All
5.0
ns
2/
9, 10, 11
All
2.0
ns
3
2/
9, 10, 11
All
4P
ns
4
2/
9, 10, 11
All
5
2/
9, 10, 11
All
6
2/
9, 10, 11
7
8
9
See figure 5
See figure 5
2/
2P
ns
4P
7P
ns
All
1.0
8.0
ns
9, 10, 11
All
1.0
8.0
ns
9, 10, 11
All
1.0
12.0
ns
9, 10, 11
All
3P
6P
ns
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
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REVISION LEVEL
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SHEET
12
TABLE I. Electrical performance characteristics – continued.
Test
Symbol
Conditions
1/
unless otherwise specified
Group A
subgroups
Device
type
Limits
Min
Unit
Max
RESET TIMING
Width of the
RESET pulse
(PLL stable) 12/
Width of the
RESET pulse (PLL
needs to sync up) 13/
Response time to
change of value in
RESET signal
Delay time, CLKOUT1
high to CLKOUT2
invalid
Delay time, CLKOUT1
high to CLKOUT2
valid
Delay time, CLKOUT1
high to SDCLK
invalid
Delay time, CLKOUT1
high to SDCLK valid
Delay time, CLKOUT1
high to SSCLK
invalid
Delay time, CLKOUT1
high to SSCLK valid
Delay time, CLKOUT1
high to low group
invalid
Delay time, CLKOUT1
high to low group
valid
Delay time, CLKOUT1
high to high group
invalid
Delay time, CLKOUT1
high to high group
valid
Delay time, CLKOUT1
high to Z group high
impedance
Delay time, CLKOUT1
high to Z group valid
1
See figure 5
9, 10, 11
All
10
CLKOUT1
cycles
250
µs
2
9, 10, 11
All
1
CLKOUT1
cycles
3
9, 10, 11
All
-1.0
ns
4
9, 10, 11
All
5
9, 10, 11
All
6
9, 10, 11
All
7
9, 10, 11
All
8
9, 10, 11
All
9
9, 10, 11
All
10
9, 10, 11
All
11
9, 10, 11
All
12
9, 10, 11
All
13
9, 10, 11
All
14
9, 10, 11
All
10
ns
-1.0
ns
10
ns
-1.0
ns
10
ns
-1.0
ns
10
ns
-1.0
ns
10
ns
-1.0
ns
10
ns
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-98661
A
REVISION LEVEL
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SHEET
13
TABLE I. Electrical performance characteristics – continued.
Test
Symbol
Conditions
1/
unless otherwise specified
Group A
subgroups
Device
type
Limits
Min
INTERRUPT TIMING
Max
14/ 15/ 16/
Response time,
EXT_INTx high to
IACK high
Width of the interrupt
pulse low
Width of the interrupt
pulse high
Delay time, CLKOUT2
low to IACK valid.
1
4
Delay time, CLKOUT2
low to INUMx valid
Delay time, CLKOUT2
low to INUMx invalid
2/
See figure 5
9, 10, 11
All
9P
ns
2
9, 10, 11
All
2P
ns
3
9, 10, 11
All
2P
ns
2/
9, 10, 11
All
-0.5P
5
2/
9, 10, 11
All
6
2/
9, 10, 11
All
-0.5P
ns
9, 10, 11
All
4.0
ns
9, 10, 11
All
2.0
ns
3
9, 10, 11
All
2P
ns
4
9, 10, 11
All
2P
ns
HOST-PORT INTERFACE (HPI) READ and WRITE TIMING
Setup time, select
signals valid before
HSTROBE low
Hold time, select
signals valid after
HSTROBE low
Pulse duration
HSTROBE low
Pulse duration
HSTROBE high
between consecutive
accesses
Delay time,
HCS to HRDY
Delay time,
HSTROBE low to
HRDY high
Output hold time, HD
low impedance after
HSTROBE low for an
HPI read
Delay time, HD valid
HRDY low
Output hold time, HD
valid after HSTROBE
high
Setup time, select
signals valid before
HAS low
Unit
1
2/
2
2/
See figure 5
13-0.5P
ns
10-0.5P
ns
17/ 18/ 19/ 20/ 21/
5
2/
9, 10, 11
All
1.0
12.0
ns
6
2/
9, 10, 11
All
1.0
12.0
ns
7
9, 10, 11
All
4.0
8
9, 10, 11
All
P-3
P+3
ns
9, 10, 11
All
3.0
12.0
ns
9, 10, 11
All
4.0
9
10
2/
2/
ns
ns
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-98661
A
REVISION LEVEL
E
SHEET
14
TABLE I. Electrical performance characteristics – continued.
Test
Symbol
Conditions
1/
unless otherwise specified
Group A
subgroups
Device
type
Limits
Min
HOST-PORT INTERFACE (HPI) READ and WRITE TIMING
Hold time, select
signals valid after
HAS low
Setup time, host data
valid before
HSTROBE high
Hold time, host data
valid after HSTROBE
high
Hold time,
HSTROBE low after
HRDY low.
HSTROBE should
not be inactivated
until HRDY is active
(low): otherwise, HPI
writes will not
complete properly.
Delay time,
HSTROBE high to
HD high impedance
Delay time,
HSTROBE low to HD
valid
Delay time,
HSTROBE high to
HRDY high
Setup time,
HAS low before
HSTROBE low
Hold time,
HAS low after
HSTROBE low
11
2/
12
13
See figure 5
Unit
Max
17/ 18/ 19/ 20/ 21/ – continued
9, 10, 11
All
2.0
ns
2/
9, 10, 11
All
3.0
ns
2/
9, 10, 11
All
2.0
ns
14
9, 10, 11
All
1.0
ns
15
9, 10, 11
All
3.0
12.0
ns
16
2/
9, 10, 11
All
3.0
12.0
ns
17
2/
9, 10, 11
All
1.0
12.0
ns
18
9, 10, 11
All
2.0
ns
19
9, 10, 11
All
2.0
ns
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-98661
A
REVISION LEVEL
E
SHEET
15
TABLE I. Electrical performance characteristics – continued.
Test
Symbol
Conditions
1/
unless otherwise specified
MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING
Delay time, CLKS high
to CLKR/X high for
internal CLKR/X
generated from
CLKS input
Cycle time, CLKR/X
1
2/
See figure 5
2
CLKR/X (INT)
Group A
subgroups
Device
type
Limits
3
Hold time, external
FSR high after CLKR
low
Setup time, DR valid
before CLKR low
6
7
2/
Hold time, DR valid
after CLKR low
8
2/
Delay time, CLKX high
to internal FSX valid
9
CLKR/X (INT)
5
3.0
9, 10, 11
All
2P
9, 10, 11
All
C-1.0
9, 10, 11
All
-4.0
CLKR (INT)
9, 10, 11
All
13.0
CLKR (INT)
9, 10, 11
All
Hold time external
FSX high after CLKX
low
11
Disable time, DX high
impedance following
last data bit from
CLKX high
Delay time, CLKX high
to DX valid
12
Delay time, FSX high
to DX valid ONLY
applies when in data
delay 0 mode
(XDATDLY = 00b)
14
2/
CLKX (INT)
9, 10, 11
All
ns
4.0
9, 10, 11
All
-4.0
2/
5.0
2/
3.0
16.0
1.0
ns
4.0
9, 10, 11
All
ns
13.0
ns
4.0
2/
9, 10, 11
All
7.0
ns
3.0
2/
9, 10, 11
All
-3.0
2.0
2.0
9.0
9, 10, 11
All
-2.0
4.0
3.0
16.0
9, 10, 11
All
-2.0
4.0
2.0
10.0
CLKX (EXT)
FSX (INT)
ns
10.0
CLKX (EXT)
13
ns
All
CLKX (EXT)
CLKX (INT)
ns
9, 10, 11
CLKX (EXT)
CLKX (INT)
4.0
4.0 2/
CLKX (EXT)
CLKX (INT)
ns
7.0
CLKR (EXT)
CLKX (INT)
C+1.0
4.0
2/
CLKR (EXT)
CLKR (INT)
ns
P-1
CLKR (INT)
CLKR (INT)
ns
2P
CLKR (EXT)
10
15.0
All
CLKR (EXT)
Setup time, external
FSX high before
CLKX low
Max
9, 10, 11
CLKR/X (EXT)
4
Min
22/ 23/
CLKR/X (EXT)
Pulse duration,
CLKR/X high or
CLKR/X low
Delay time, CLKR high
to internal FSR valid
Setup time, external
FSR high before
CLKR low
Unit
FSX (EXT)
ns
ns
ns
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-98661
A
REVISION LEVEL
E
SHEET
16
TABLE I. Electrical performance characteristics – continued.
Test
Symbol
Conditions
1/
unless otherwise specified
Group A
subgroups
Device
type
Limits
Min
Unit
Max
FSR TIMING When GSYNC = 1
Setup time, FSR high
before CLKS high
Hold time, FSR high
after CLKS high
1
See figure 5
2
9, 10, 11
All
4.0
ns
9, 10, 11
All
4.0
ns
McBSP TIMING as SPI MASTER or SLAVE: CLKSTP = 10b, CLKXP = 0
Hold time, FSX low
after CLKX low
1
2/ 25/
Delay time, FSX low to
CLKX high
2
2/ 26/
Master
Delay time, CLKX high
to DX valid
3
Master
Setup time, DR valid
before CLKX low
4
Hold time, DR valid
after
CLKX low
Disable time, DX high
impedance following
last data bit from
CLKX
low
Disable time, DX high
impedance following
last data bit from
FSX
high
Delay time, FSX low to
DX valid
5
See figure 5
2/
Master
24/
27/
9, 10, 11
All
T-4
T+4
ns
27/
9, 10, 11
All
L-4
L+4
ns
27/
9, 10, 11
All
-4.0
4.0
ns
3P+1
5P+17
Slave
Slave
Slave
2/
Master
9, 10, 11
All
12.0
Slave
2/
2-3P
Master
9, 10, 11
All
4.0
Slave
6
Master
ns
ns
5+6P
27/
9, 10, 11
All
27/
9, 10, 11
All
L-2
L+3
P+4
3P+17
2P+1
4P+13
ns
Slave
7
Master
ns
Slave
8
2/
Master
27/
9, 10, 11
All
ns
Slave
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-98661
A
REVISION LEVEL
E
SHEET
17
TABLE I. Electrical performance characteristics – continued.
Test
Symbol
Conditions
1/
unless otherwise specified
Group A
subgroups
McBSP TIMING as SPI MASTER or SLAVE: CLKSTP = 11b, CLKXP = 0
Hold time, FSX low
after CLKX low
1
2/ 25/
Delay time, FSX low to
CLKX high
2
2/ 26/
Master
Delay time, CLKX low
to DX valid
3
Master
Setup time, DR valid
before CLKX high
4
Hold time, DR valid
after CLKX high
5
Disable time, DX high
impedance following
last data bit from
CLKX low
Delay time, FSX low to
DX valid
6
See figure 5
Master
Device
type
Limits
Unit
Min
Max
24/
27/
9, 10, 11
All
L-4
L+4
ns
27/
9, 10, 11
All
T-4
T+4
ns
27/
9, 10, 11
All
-4.0
4.0
ns
3P+1
5P+17
Slave
Slave
2/
Slave
2/
Master
9, 10, 11
All
12.0
Slave
2/
Master
9, 10, 11
All
4.0
Slave
Master
Master
27/
9, 10, 11
All
27/
9, 10, 11
All
Slave
McBSP TIMING as SPI MASTER or SLAVE: CLKSTP = 10b, CLKXP = 1
Hold time, FSX low
after CLKX high
1
2/ 25/
Delay time, FSX low
to CLKX low
2
2/ 26/
Master
Delay time, CLKX low
to DX valid
3
2/
Master
Setup time, DR valid
before CLKX high
4
2/
Hold time, DR valid
after CLKX high
5
2/
Disable time, DX high
impedance following
last data bit from
CLKX high
Disable time, DX high
impedance following
last data bit from
FSX high
Delay time, FSX low to
DX valid
6
See figure 5
Master
ns
5+6P
Slave
7
ns
2-3P
2.0
4.0
3P+4
5P+17
H-2
H+3
2/2P+1
2/4P+13
ns
ns
24/
27/
9, 10, 11
All
T-4
T+4
ns
27/
9, 10, 11
All
H-4
H+4
ns
27/
9, 10, 11
All
-4.0
4.0
ns
3P+1
5P+17
9, 10, 11
All
9, 10, 11
All
27/
9, 10, 11
All
27/
9, 10, 11
All
Slave
Slave
Slave
Master
12.0
Slave
2-3P
Master
4.0
Slave
Master
ns
ns
5+6P
H-2
H+3
P+4
3P+17
ns
Slave
7
Master
ns
Slave
8
2/
Master
27/
9, 10, 11
All
ns
Slave
2P+1
4P+13
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-98661
A
REVISION LEVEL
E
SHEET
18
TABLE I. Electrical performance characteristics – continued.
Test
Symbol
Conditions
1/
unless otherwise specified
Group A
subgroups
McBSP TIMING as SPI MASTER or SLAVE: CLKSTP = 11b, CLKXP = 1
Hold time, FSX low
after CLKX high
1
2/ 25/
Delay time, FSX low to
CLKX low
2
2/ 26/
Master
Delay time, CLKX high
to DX valid
3
Master
Setup time, DR valid
before CLKX low
4
Hold time, DR valid
after CLKX low
5
Disable time, DX high
impedance following
last data bit from
CLKX high
Delay time, FSX low
to DX valid
6
See figure 5
Master
Device
type
Limits
Unit
Min
Max
24/
27/
9, 10, 11
All
H-4
H+4
ns
27/
9, 10, 11
All
T-4
T+4
ns
27/
9, 10, 11
All
-4.0
4.0
ns
3P+1
5P+17
Slave
Slave
2/
Slave
2/
Master
9, 10, 11
All
12.0
Slave
2/
Master
9, 10, 11
All
4.0
Slave
Master
Master
ns
5+6P
27/
9, 10, 11
All
Slave
7
ns
2-3P
27/
9, 10, 11
All
Slave
-2.0
4.0
3P+4
5P+17
L-2
L+4
2P+1
2/
4P+13
2/
11.0
2/
ns
ns
DMAC TIMING
Delay time, CLKOUT1
high to DMAC valid
1
2/
See figure 5
9, 10, 11
All
2.0
ns
1
2/
See figure 5
9, 10, 11
All
2P
2
2/
9, 10, 11
All
1.0
10.0
ns
1
2/
See figure 5
9, 10, 11
All
1.0
9.0
ns
1 2/
Delay time, TCK low
2
to TDO valid
Setup time, TDI/TMS/
3 2/
TRST valid before
TCK high
Hold time, TDI/TMS/
4 2/
TRST valid after TCK
high
See footnotes on next page.
See figure 5
TIMER TIMING
Pulse duration, TINP
high or low
Delay time, CLKOUT1
high to TOUT valid
ns
POWER-DOWN TIMING
Delay time, CLKOUT1
high to PD valid
JTAG TEST-PORT TIMING
Cycle time, TCK
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
9, 10, 11
All
35.0
9, 10, 11
All
-3.0
ns
9, 10, 11
All
10.0
ns
9, 10, 11
All
9.0
ns
15.0
ns
SIZE
5962-98661
A
REVISION LEVEL
E
SHEET
19
TABLE I. Electrical performance characteristics – continued.
1/ Each input/output, as applicable, shall be tested at the specified temperature, for the specified limits, to the tests in table I
herein. Unless otherwise specified, the operating temperature range for device type 01 is -55°C to +115°C, and the
operating temperature range for device type 02 is -55°C to +125°C. Output terminals not designated shall be either high
level logic, low level logic, or open.
2/ Tested parameters.
3/ TMS and TDI are not included due to internal pullups.
4/ C = CLKIN cycle time in ns. For example, when CLKIN Frequency is 10 MHz, use C = 100 ns.
5/ P = 1/CPU clock frequency in ns. When running parts at 140 MHz, use P = 7.1 ns. PH is the high period of CLKIN in ns and
PL is the low period of CLKIN in ns.
6/ To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. If ARDY does
meet setup or hold time, it may be recognized in the current cycle or the next cycle. Thus, ARDY can be an asynchronous
input.
7/ The minimum delay is also the minimum output hold after CLKOUT1 high.
8/ When the PLL is used (CLKMODEx4), P = 1/CPU clock frequency; when running parts at 140 MHz, use P = 7.1 ns. For
CLKMODEx1, 0.5P is defined as PH (pulse duration of CLKIN high) for all output setup times; 0.5P is defined as PL (pulse
duration of CLKIN low) for all output hold times.
9/ For CLKMODEx1:
1.5P = P + PH, where P=1/CPU clock frequency, and PH = pulse duration of CLKIN high.
0.5P = PL, where PL = pulse duration of CLKIN low.
10/ HOLD is synchronized internally. If setup and hold times are not met, it will either be recognized in the current cycle or in the
next cycle. HOLD can be an asynchronous input.
11/ All pending EMIF transactions are allowed to complete before HOLDA is asserted. The worst cases for this is an
asynchronous read or write with external ARDY used or a minimum of eight consecutive SDRAM reads or writes when
RBTR8 = 1. If no bus transactions are occurring, then the minimum delay time can be achieved. The bus hold can be
indefinitely delayed by setting NOHOLD = 1.
12/ This parameter applies to CLKMODEx1 when CLKIN is stable and applies to CLKMODEx4 when CLKIN and PLL are
stable.
13/ This parameter only applies to CLKMODEx4. The RESET signal is not connected internally to the clock PLL circuit. The
PLL, however, may need up to 250 µs to stabilize following device power up or after PLL configuration has been changed.
During that time, RESET must be asserted to ensure proper device operation.
14/ Interrupt signals are synchronized internally and are potentially recognized one cycle later if setup and hold time are
violated. Also they can be connected to asynchronous inputs.
15/ When the PLL is used (CLKMODEx4), 0.5P = 1/(2x CPU clock frequency).
16/ For CLKMODEx1:0.5P = PH, where PH is the high period of CLKIN.
17/ HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
18/ HCS enables HRDY, and HRDY is always low when HCS is high. The case where HRDY goes high when HCS falls
indicates that HPI is busy completing a previous HPID WRITE or READ autoincrement.
19/ The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
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A
REVISION LEVEL
E
SHEET
20
TABLE I. Electrical performance characteristics – continued.
20/ This parameter is used during an HPID read. At the beginning of the first half -word transfer on the falling edge of
HSTROBE, the HPI sends the request to the DMA auxiliary channel, and HRDY remains high until the DMA auxiliary
channel loads the requested data into HPID.
21/ This parameter is used after the second half-word of an HPID write autoincrement read. HRDY remains low if the access is
not an HPID write or autoincrement read. Reading or writing to HPIC or HPIA does not affect the HRDY signal.
22/ CLKRP = CLKXP =FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal
are also inverted.
23/ Minimum delay times also represent minimum output hold times.
24/ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
25/ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave enable output. As a slave, the active-low
signal input on FSX and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP.
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP.
26/ FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge
of the master clock (CLKX).
27/ S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency).
= sample rate generator input clock = P_clks if CLKSM = 0(P_clks = CLKS period).
T = CLKX period = (1 + CLKGDV)*S.
H = CLKX high pulse width = (CLKGDV/2 + 1)*S if CLKGDV is even.
= (CLKGDV + 1)2* S if CLKGDV is odd or zero.
L = CLKX low pulse width = (CLKGDV/2)*S if CLKGDV is even.
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-98661
A
REVISION LEVEL
E
SHEET
21
CASE X
Case outline
Symbol
Min
A
A1
A2
b
D/E
D1/E1
e
0.50
1.00
0.60
26.80
X
Millimeters
Max
3.30
0.70
1.22
0.90
27.20
25.40 BSC
1.27 BSC
NOTE: All dimensions are in Millimeters.
FIGURE 2. Case outlines.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-98661
A
REVISION LEVEL
E
SHEET
22
CASE Y
Case outline
Y
Symbol
Millimeters
Min
Max
A
2.70
A1
1.03
1.25
b
0.81
0.91
D/E
26.80
27.20
D1/E1
25.40 BSC
e
1.27 BSC
NOTE: All dimensions are in Millimeters.
FIGURE 2. Case outlines - Continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-98661
A
REVISION LEVEL
E
SHEET
23
Case outline:
X and Y
Symbol number
Pin Symbol
Type
Symbol number
Pin Symbol
Type
A14
Y6
V9
B17
C17
C13
G11
F11
D12
G10
C12
K19
R12
R13
M20
N18
R20
T18
J20
K21
R16
P20
R15
R18
R11
T19
T20
T14
T16
G20
D19
H2
J6
H6
E4
G6
F6
D4
D11
B11
A11
G9
D10
A10
C10
B9
F9
C9
A9
B8
D9
CLKIN
CLKOUT1
CLKOUT2
CLKMODE1
CLKMODE0
PLLFREQ3
PLLFREQ2
PLLFREQ1
PLLV
PLLG
PLLF
TMS
TDO
TDI
TCK
TRST
EMU1
EMU0
RESET
NMI
EXT_INT7
EXT_INT6
EXT_INT5
EXT_INT4
IACK
INUM3
INUM2
INUM1
INUM0
LENDIAN
PD
HINT
HCNTL1
HCNTL0
HHWIL
HBE1
HBE0
HR/W
HD15
HD14
HD13
HD12
HD11
HD10
HD9
HD8
HD7
HD6
HD5
HD4
HD3
I
O
O
I
I
I
I
I
A
A
A
I
O/Z
I
I
I
I/O/Z
I/O/Z
I/O/Z
I
I
I
I
I
O
O
O
O
O
I
O
O/Z
I
I
I
I
I
I
I/OZ
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
D8
B7
C7
L6
C5
C4
K6
H3
B16
G14
F15
C18
D17
Y5
V3
T6
U2
R8
T3
T2
R2
L4
L3
J2
J1
K1
K2
L2
L1
M1
M2
M6
N4
N1
N2
N6
P4
P3
P2
P1
P6
U18
U20
T15
V18
V17
V16
T12
W17
T13
Y17
HD2
HD1
HD0
HAS
HCS
HDS1
HDS2
HRDY
BOOTMODE4
BOOTMODE3
BOOTMODE2
BOOTMODE1
BOOTMODE0
CE3
CE2
CE1
CE0
BE3
BE2
BE1
BE0
EA21
EA20
EA19
EA18
EA17
EA16
EA15
EA14
EA13
EA12
EA11
EA10
EA9
EA8
EA7
EA6
EA5
EA4
EA3
EA2
ED31
ED30
ED29
ED28
ED27
ED26
ED25
ED24
ED23
ED22
I/O/Z
I/O/Z
I/O/Z
I
I
I
I
O
I
I
I
I
I
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I = Input, O = Output, Z = High Impedance, S = Supply voltage, GND = Ground.
PPLV and PLLG signals are not part of external voltage supply or ground. See the CLOCK/PLL documentation for
information on how to connect those pins. A = Analog Signal (PLL Filter).
FIGURE 3. Terminal connections.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-98661
A
REVISION LEVEL
E
SHEET
24
Case outline:
X and Y
Symbol number
Pin Symbol
Type
Symbol number
Pin Symbol
Type
T11
Y16
W15
V14
Y15
R9
Y14
V13
AA13
T10
Y13
W12
Y12
Y11
V10
AA10
Y10
W10
Y9
AA9
Y8
W9
R7
T7
V5
R4
V8
W7
Y7
AA8
V7
V6
W5
T8
T9
R6
B15
G2
K3
M18
J18
E18
F19
E20
G16
ED21
ED20
ED19
ED18
ED17
ED16
ED15
ED14
ED13
ED12
ED11
ED10
ED9
ED8
ED7
ED6
ED5
ED4
ED3
ED2
ED1
ED0
ARE
AOE
AWE
ARDY
SSADS
SSOE
SSWE
SSCLK
SDA10
SDRAS
SDCAS
SDWE
SDCLK
HOLD
HOLDA
TOUT1
TINP1
TOUT0
TINP0
DMAC3
DMAC2
DMAC1
DMAC0
I/O/Z
I/O/Z
I/OZ
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
O/Z
O/Z
O/Z
I
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
I
O
O/Z
I
O/Z
I
O
O
O
O
F4
H4
J4
E2
G4
F3
F2
K18
L21
K20
J21
M21
P16
N16
N21
K16
B13
B14
F13
C15
F7
D7
B5
F16
C14
C8
E19
E3
H11
H13
H9
J10
J12
J14
J19
J3
J8
K11
K13
K15
K7
K9
L10
L12
L14
L8
CLKS1
CLKR1
CLKX1
DR1
DX1
FSR1
FSX1
CLKS0
CLKR0
CLKX0
DR0
DX0
FSR0
FSX0
RSV0
RSV1
RSV2
RSV3
RSV4
RSV5
RSV6
RSV7
RSV8
RSV9
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
I
I/O/Z
I/O/Z
I
O/Z
I/O/Z
I/O/Z
I
I/O/Z
I/O/Z
I
O/Z
I/O/Z
I/O/Z
I
I
I
I
I
O
I
I
I
O
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
DVDD = 3.3 V supply voltage
FIGURE 3. Terminal connections - continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-98661
A
REVISION LEVEL
E
SHEET
25
Case outline:
X and Y
Symbol number
Pin Symbol
Type
Symbol number
Pin Symbol
Type
M11
M13
M15
M7
M9
N0
N12
N14
N19
N3
N8
P11
P13
P9
U19
U3
W14
W8
A12
A13
B10
B12
B6
D15
D16
F10
F14
F8
G13
G7
G8
K4
M3
M4
A3
A5
A7
A16
A18
AA4
AA6
AA15
AA17
AA19
B2
B4
B19
C1
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
C3
C20
D2
D21
E1
E6
E8
E10
E12
E14
E16
F5
F17
F21
G1
H5
H17
K5
K17
M5
M17
P5
P17
R21
T1
T5
T17
U6
U8
U10
U12
U14
U16
U21
V1
V20
W2
W19
W21
Y3
Y18
Y20
AA11
AA12
F20
G18
H16
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
DVDD = 3.3 V supply voltage, CVDD = 1.9 V supply voltage
FIGURE 3. Terminal connections - continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-98661
A
REVISION LEVEL
E
SHEET
26
Case outline:
X and Y
Symbol number
Pin Symbol
Type
Symbol number
Pin Symbol
Type
H18
L18
L19
L20
N20
P18
P19
R10
R14
U4
V11
V12
V15
W13
C11
C16
C6
D5
G3
H10
H12
H14
H7
H8
J11
J13
J7
J9
K8
L7
L9
M8
N7
R3
A4
A6
A8
A15
A17
A19
AA3
AA5
AA7
AA14
AA16
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
S
S
S
S
S
S
S
S
S
S
S
S
S
S
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AA18
B3
B18
B20
C2
C19
C21
D1
D20
E5
E7
E9
E11
E13
E15
E17
E21
F1
G5
G17
G21
H1
J5
J17
L5
L17
N5
N17
P21
R1
R5
R17
T21
U1
U5
U7
U9
U11
U13
U15
U17
V2
V21
W1
W3
W20
Y2
Y4
Y19
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
CVDD = 1.9 V supply voltage
FIGURE 3. Terminal connections - continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-98661
A
REVISION LEVEL
E
SHEET
27
Case outline:
X and Y
Symbol number
Pin Symbol
Type
Symbol number
Pin Symbol
F18
G19
H15
J15
J16
K10
K12
K14
L11
L13
L15
M10
M12
M14
N11
N13
N15
N9
P10
P12
P14
P15
P7
P8
R19
T4
W11
W16
W6
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
D13
D14
D18
D3
D6
F12
G12
G15
H19
H20
H21
L16
M16
M19
V19
V4
W18
W4
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Type
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, NC = No connection
FIGURE 3. Terminal connections - continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-98661
A
REVISION LEVEL
E
SHEET
28
FIGURE 4. Block diagram.
Instruction name
Instruction code
IDCODE
0100
INT_SCAN
0111
EXTEST
0000
SAMPLE
0001
BYPASS
1111
FIGURE 5. Boundary scan instruction codes.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-98661
A
REVISION LEVEL
E
SHEET
29
Tester Pin Electronics
NOTE: All input and output timing parameters are referenced to 1.5 V for both “0” and “1” logic levels.
FIGURE 6. Timing waveforms.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-98661
A
REVISION LEVEL
E
SHEET
30
FIGURE 6. Timing waveforms - continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-98661
A
REVISION LEVEL
E
SHEET
31
FIGURE 6. Timing waveforms - continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-98661
A
REVISION LEVEL
E
SHEET
32
FIGURE 6. Timing waveforms - continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-98661
A
REVISION LEVEL
E
SHEET
33
FIGURE 6. Timing waveforms - continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-98661
A
REVISION LEVEL
E
SHEET
34
FIGURE 6. Timing waveforms - continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-98661
A
REVISION LEVEL
E
SHEET
35
FIGURE 6. Timing waveforms - continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-98661
A
REVISION LEVEL
E
SHEET
36
FIGURE 6. Timing waveforms - continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-98661
A
REVISION LEVEL
E
SHEET
37
NOTE:
EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SSADS, SSOE, SSWE, SDA10, SDRAS,
SDCAS, and SDWE.
NOTES:
Low group consists of: IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1.
High group consists of: HINT.
Z group consists of: EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS
SDWE, HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0,DX1, CLKR0, CLKR1, FSR0, and FSR1.
FIGURE 6. Timing waveforms - continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-98661
A
REVISION LEVEL
E
SHEET
38
FIGURE 6. Timing waveforms - continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-98661
A
REVISION LEVEL
E
SHEET
39
FIGURE 6. Timing waveforms - continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-98661
A
REVISION LEVEL
E
SHEET
40
FIGURE 6. Timing waveforms - continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-98661
A
REVISION LEVEL
E
SHEET
41
FIGURE 6. Timing waveforms - continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-98661
A
REVISION LEVEL
E
SHEET
42
FIGURE 6. Timing waveforms - continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-98661
A
REVISION LEVEL
E
SHEET
43
FIGURE 6. Timing waveforms - continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-98661
A
REVISION LEVEL
E
SHEET
44
FIGURE 6. Timing waveforms - continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-98661
A
REVISION LEVEL
E
SHEET
45
4. VERIFICATION
4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with
MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan
shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in
accordance with MIL-PRF-38535, appendix A.
4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted
on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in
accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection.
4.2.1 Additional criteria for device class M.
a.
Burn-in test, method 1015 of MIL-STD-883.
(1) Test condition D. The test circuit shall be maintained by the manufacturer under document revision level control
and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method
1015 of MIL-STD-883.
(2) TA = +125°C, minimum.
b.
Interim and final electrical test parameters shall be as specified in table II herein.
4.2.2 Additional criteria for device classes Q and V.
a.
The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the
device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under
document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
method 1015 of MIL-STD-883.
b.
Interim and final electrical test parameters shall be as specified in table II herein.
c.
Additional screening for device class V beyond the requirements of device class Q shall be as specified in
MIL-PRF-38535, appendix B.
4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in
accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups
A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).
4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with
MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified herein. Quality conformance inspection for
device class M shall be in accordance with MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed
for device class M shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections
(see 4.4.1 through 4.4.4).
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-98661
A
REVISION LEVEL
E
SHEET
46
4.4.1 Group A inspection.
a.
Tests shall be as specified in table II herein.
b.
Subgroup 4 (CIN, COUT) shall be measured only for the initial test and after process or design changes which may affect
input capacitance. One pin of each input/output driver (buffer) type shall be tested on each sample device. A
minimum sample size of 5 devices with zero rejects shall be required.
c.
For device class M, subgroups 7 and 8 tests shall be sufficient to verify the truth table. For device classes Q and V,
subgroups 7 and 8 shall include verifying the functionality of the device.
TABLE II. Electrical test requirements.
Test requirements
Subgroups
(in accordance with
MIL-STD-883,
method 5005, table I)
Device
class M
Interim electrical
parameters (see 4.2)
Final electrical
parameters (see 4.2)
Group A test
requirements (see 4.4)
Group C end-point electrical
parameters (see 4.4)
Group D end-point electrical
parameters (see 4.4)
Group E end-point electrical
parameters (see 4.4)
Subgroups
(in accordance with
MIL-PRF-38535, table III)
Device
class Q
Device
class V
1, 7
1, 7
1, 7
1/ 1, 2, 3,
7, 8, 9, 10, 11
1/ 1, 2, 3,
7, 8, 9, 10, 11
2/ 1, 2, 3,
7, 8, 9, 10, 11
1, 2, 3, 7, 8,
9, 10, 11
1, 2, 3, 7, 8,
9, 10, 11
1, 2, 3, 7, 8,
9, 10, 11
1, 7, 9
1, 7, 9
1, 7, 9
1, 7, 9
1, 7, 9
1, 7, 9
1/ PDA applies to subgroup 1.
2/ PDA applies to subgroups 1 and 7.
4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table II herein.
4.4.2.1 Additional criteria for device class M. Steady-state life test conditions, method 1005 of MIL-STD-883:
a.
Test condition D. The test circuit shall be maintained by the manufacturer under document revision level control
and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method
1005 of MIL-STD-883.
b.
TA = +125°C, minimum.
c.
Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-98661
A
REVISION LEVEL
E
SHEET
47
4.4.2.2 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature,
or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The
test circuit shall be maintained under document revision level control by the device manufacturer's TRB in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify
the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of
MIL-STD-883.
4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table II herein.
4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured
(see 3.5 herein).
a.
End-point electrical parameters shall be as specified in table II herein.
b.
For device classes Q and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as
specified in MIL-PRF-38535 for the RHA level being tested. For device class M, the devices shall be subjected to
radiation hardness assured tests as specified in MIL-PRF-38535, appendix A for the RHA level being tested. All device
classes must meet the postirradiation end-point electrical parameter limits as defined in table I at TA = +25°C ±5°C,
after exposure, to the subgroups specified in table II herein.
5. PACKAGING
5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes
Q and V or MIL-PRF-38535, appendix A for device class M.
6. NOTES
6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications
(original equipment), design applications, and logistics purposes.
6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor
prepared specification or drawing.
6.1.2 Substitutability. Device class Q devices will replace device class M devices.
6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for
the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal.
6.3 Record of users. Military and industrial users should inform Defense Supply Center Columbus (DSCC) when a system
application requires configuration control and which SMD's are applicable to that system. DSCC will maintain a record of users
and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering
microelectronic devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544.
6.4 Comments. Comments on this drawing should be directed to DSCC-VA, Columbus, Ohio 43218-3990, or telephone
(614) 692-0547.
6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in
MIL-PRF-38535 and MIL-HDBK-1331.
6.6 Sources of supply.
6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535.
The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DSCC-VA and have agreed to
this drawing.
6.6.2 Approved sources of supply for device class M. Approved sources of supply for class M are listed in MIL-HDBK-103.
The vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been
submitted to and accepted by DSCC-VA.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-98661
A
REVISION LEVEL
E
SHEET
48
STANDARD MICROCIRCUIT DRAWING BULLETIN
DATE: 09-07-28
Approved sources of supply for SMD 5962-98661 are listed below for immediate acquisition information only and
shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be
revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a
certificate of compliance has been submitted to and accepted by DSCC-VA. This information bulletin is superseded
by the next dated revision of MIL-HDBK-103 and QML-38535. DSCC maintains an online database of all current
sources of supply at http://www.dscc.dla.mil/Programs/Smcr/ .
1/
2/
3/
Standard
microcircuit drawing
PIN 1/
Vendor
CAGE
number
Vendor
similar
PIN 2/
5962-9866101QXA
01295
SMJ320C6701GLPW14
5962-9866101VXA
01295
SMV320C6701GLPW14
5962-9866102QXA
3/
SMJ320C6701
5962-9866102VXA
01295
SMV320C6701GLPM14
5962-9866102VYC
01295
SMV320C6701ZMBM14
The lead finish shown for each PIN representing a
hermetic package is the most readily available from the
manufacturer listed for that part. If the desired lead
finish is not listed contact the vendor to determine its
availability.
Caution. Do not use this number for item acquisition.
Items acquired to this number may not satisfy the
performance requirements of this drawing.
Not available from an approved source of supply.
Vendor CAGE
number
01295
Vendor name
and address
Texas Instruments, Inc.
Semiconductor Group
8505 Forest Lane
P.O. Box 660199
Dallas, TX 75243
Point of contact: U.S. Highway 75 South
P.O. Box 84, M/S 853
Sherman, TX 75090-9493
The information contained herein is disseminated for convenience only and the
Government assumes no liability whatsoever for any inaccuracies in the
information bulletin.
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